drivers/event/octeontx/timvf_evdev.h

   1 /*
   2  * SPDX-License-Identifier: BSD-3-Clause
   3  * Copyright(c) 2017 Cavium, Inc
   4  */
   5
   6 #ifndef __TIMVF_EVDEV_H__
   7 #define __TIMVF_EVDEV_H__
   8
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_debug.h>
  12 #include <rte_eal.h>
  13 #include <rte_eventdev.h>
  14 #include <rte_event_timer_adapter.h>
  15 #include <rte_event_timer_adapter_pmd.h>
  16 #include <rte_io.h>
  17 #include <rte_lcore.h>
  18 #include <rte_log.h>
  19 #include <rte_malloc.h>
  20 #include <rte_mbuf_pool_ops.h>
  21 #include <rte_mempool.h>
  22 #include <rte_memzone.h>
  23 #include <rte_pci.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_reciprocal.h>
  26
  27 #include <octeontx_mbox.h>
  28 #include <octeontx_fpavf.h>
  29
  30 #define timvf_log(level, fmt, args...) \
  31         rte_log(RTE_LOG_ ## level, otx_logtype_timvf, \
  32                         "[%s] %s() " fmt "\n", \
  33                         RTE_STR(event_timer_octeontx), __func__, ## args)
  34
  35 #define timvf_log_info(fmt, ...) timvf_log(INFO, fmt, ##__VA_ARGS__)
  36 #define timvf_log_dbg(fmt, ...) timvf_log(DEBUG, fmt, ##__VA_ARGS__)
  37 #define timvf_log_err(fmt, ...) timvf_log(ERR, fmt, ##__VA_ARGS__)
  38 #define timvf_func_trace timvf_log_dbg
  39
  40 #define TIM_COPROC                              (8)
  41 #define TIM_GET_DEV_INFO                        (1)
  42 #define TIM_GET_RING_INFO                       (2)
  43 #define TIM_SET_RING_INFO                       (3)
  44 #define TIM_RING_START_CYC_GET                  (4)
  45
  46 #define TIM_MAX_RINGS                           (64)
  47 #define TIM_DEV_PER_NODE                        (1)
  48 #define TIM_VF_PER_DEV                          (64)
  49 #define TIM_RING_PER_DEV                        (TIM_VF_PER_DEV)
  50 #define TIM_RING_NODE_SHIFT                     (6)
  51 #define TIM_RING_MASK                           ((TIM_RING_PER_DEV) - 1)
  52 #define TIM_RING_INVALID                        (-1)
  53
  54 #define TIM_MIN_INTERVAL                        (1E3)
  55 #define TIM_MAX_INTERVAL                        ((1ull << 32) - 1)
  56 #define TIM_MAX_BUCKETS                         (1ull << 20)
  57 #define TIM_CHUNK_SIZE                          (4096)
  58 #define TIM_MAX_CHUNKS_PER_BUCKET               (1ull << 32)
  59
  60 #define TIMVF_MAX_BURST                         (8)
  61
  62 /* TIM VF Control/Status registers (CSRs): */
  63 /* VF_BAR0: */
  64 #define TIM_VF_NRSPERR_INT                      (0x0)
  65 #define TIM_VF_NRSPERR_INT_W1S                  (0x8)
  66 #define TIM_VF_NRSPERR_ENA_W1C                  (0x10)
  67 #define TIM_VF_NRSPERR_ENA_W1S                  (0x18)
  68 #define TIM_VRING_FR_RN_CYCLES                  (0x20)
  69 #define TIM_VRING_FR_RN_GPIOS                   (0x28)
  70 #define TIM_VRING_FR_RN_GTI                     (0x30)
  71 #define TIM_VRING_FR_RN_PTP                     (0x38)
  72 #define TIM_VRING_CTL0                          (0x40)
  73 #define TIM_VRING_CTL1                          (0x50)
  74 #define TIM_VRING_CTL2                          (0x60)
  75 #define TIM_VRING_BASE                          (0x100)
  76 #define TIM_VRING_AURA                          (0x108)
  77 #define TIM_VRING_REL                           (0x110)
  78
  79 #define TIM_CTL1_W0_S_BUCKET                    20
  80 #define TIM_CTL1_W0_M_BUCKET                    ((1ull << (40 - 20)) - 1)
  81
  82 #define TIM_BUCKET_W1_S_NUM_ENTRIES             (0) /*Shift*/
  83 #define TIM_BUCKET_W1_M_NUM_ENTRIES             ((1ull << (32 - 0)) - 1)
  84 #define TIM_BUCKET_W1_S_SBT                     (32)
  85 #define TIM_BUCKET_W1_M_SBT                     ((1ull << (33 - 32)) - 1)
  86 #define TIM_BUCKET_W1_S_HBT                     (33)
  87 #define TIM_BUCKET_W1_M_HBT                     ((1ull << (34 - 33)) - 1)
  88 #define TIM_BUCKET_W1_S_BSK                     (34)
  89 #define TIM_BUCKET_W1_M_BSK                     ((1ull << (35 - 34)) - 1)
  90 #define TIM_BUCKET_W1_S_LOCK                    (40)
  91 #define TIM_BUCKET_W1_M_LOCK                    ((1ull << (48 - 40)) - 1)
  92 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER         (48)
  93 #define TIM_BUCKET_W1_M_CHUNK_REMAINDER         ((1ull << (64 - 48)) - 1)
  94
  95 #define TIM_BUCKET_SEMA \
  96         (TIM_BUCKET_CHUNK_REMAIN)
  97
  98 #define TIM_BUCKET_CHUNK_REMAIN \
  99         (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)
 100
 101 #define TIM_BUCKET_LOCK \
 102         (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)
 103
 104 #define TIM_BUCKET_SEMA_WLOCK \
 105         (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))
 106
 107 #define NSEC_PER_SEC 1E9
 108 #define NSEC2CLK(__ns, __freq) (((__ns) * (__freq)) / NSEC_PER_SEC)
 109 #define CLK2NSEC(__clk, __freq) (((__clk) * NSEC_PER_SEC) / (__freq))
 110
 111 #define timvf_read64 rte_read64_relaxed
 112 #define timvf_write64 rte_write64_relaxed
 113
 114 #define TIMVF_ENABLE_STATS_ARG               ("timvf_stats")
 115
 116 extern int otx_logtype_timvf;
 117 static const uint16_t nb_chunk_slots = (TIM_CHUNK_SIZE / 16) - 1;
 118
 119 struct timvf_info {
 120         uint16_t domain; /* Domain id */
 121         uint8_t total_timvfs; /* Total timvf available in domain */
 122 };
 123
 124 enum timvf_clk_src {
 125         TIM_CLK_SRC_SCLK = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
 126         TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
 127         TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
 128         TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
 129 };
 130
 131 /* TIM_MEM_BUCKET */
 132 struct tim_mem_bucket {
 133         uint64_t first_chunk;
 134         union {
 135                 uint64_t w1;
 136                 struct {
 137                         uint32_t nb_entry;
 138                         uint8_t sbt:1;
 139                         uint8_t hbt:1;
 140                         uint8_t bsk:1;
 141                         uint8_t rsvd:5;
 142                         uint8_t lock;
 143                         int16_t chunk_remainder;
 144                 };
 145         };
 146         uint64_t current_chunk;
 147         uint64_t pad;
 148 } __rte_packed;
 149
 150 struct tim_mem_entry {
 151         uint64_t w0;
 152         uint64_t wqe;
 153 } __rte_packed;
 154
 155 struct timvf_ctrl_reg {
 156         uint64_t rctrl0;
 157         uint64_t rctrl1;
 158         uint64_t rctrl2;
 159         uint8_t use_pmu;
 160 } __rte_packed;
 161
 162 struct timvf_ring;
 163
 164 typedef uint32_t (*bkt_id)(const uint32_t bkt_tcks, const uint32_t nb_bkts);
 165 typedef struct tim_mem_entry * (*refill_chunk)(
 166                 struct tim_mem_bucket * const bkt,
 167                 struct timvf_ring * const timr);
 168
 169 struct timvf_ring {
 170         bkt_id get_target_bkt;
 171         refill_chunk refill_chunk;
 172         struct rte_reciprocal_u64 fast_div;
 173         uint64_t ring_start_cyc;
 174         uint32_t nb_bkts;
 175         struct tim_mem_bucket *bkt;
 176         void *chunk_pool;
 177         uint64_t tck_int;
 178         volatile uint64_t tim_arm_cnt;
 179         uint64_t tck_nsec;
 180         void  *vbar0;
 181         void *bkt_pos;
 182         uint64_t max_tout;
 183         uint64_t nb_chunks;
 184         enum timvf_clk_src clk_src;
 185         uint16_t tim_ring_id;
 186 } __rte_cache_aligned;
 187
 188 static __rte_always_inline uint32_t
 189 bkt_mod(const uint32_t rel_bkt, const uint32_t nb_bkts)
 190 {
 191         return rel_bkt % nb_bkts;
 192 }
 193
 194 static __rte_always_inline uint32_t
 195 bkt_and(uint32_t rel_bkt, uint32_t nb_bkts)
 196 {
 197         return rel_bkt & (nb_bkts - 1);
 198 }
 199
 200 int timvf_info(struct timvf_info *tinfo);
 201 void *timvf_bar(uint8_t id, uint8_t bar);
 202 int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags,
 203                 uint32_t *caps, const struct rte_event_timer_adapter_ops **ops,
 204                 uint8_t enable_stats);
 205 uint16_t timvf_timer_cancel_burst(const struct rte_event_timer_adapter *adptr,
 206                 struct rte_event_timer **tim, const uint16_t nb_timers);
 207 uint16_t timvf_timer_arm_burst_sp(const struct rte_event_timer_adapter *adptr,
 208                 struct rte_event_timer **tim, const uint16_t nb_timers);
 209 uint16_t timvf_timer_arm_burst_sp_stats(
 210                 const struct rte_event_timer_adapter *adptr,
 211                 struct rte_event_timer **tim, const uint16_t nb_timers);
 212 uint16_t timvf_timer_arm_burst_mp(const struct rte_event_timer_adapter *adptr,
 213                 struct rte_event_timer **tim, const uint16_t nb_timers);
 214 uint16_t timvf_timer_arm_burst_mp_stats(
 215                 const struct rte_event_timer_adapter *adptr,
 216                 struct rte_event_timer **tim, const uint16_t nb_timers);
 217 uint16_t timvf_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr,
 218                 struct rte_event_timer **tim, const uint64_t timeout_tick,
 219                 const uint16_t nb_timers);
 220 uint16_t timvf_timer_arm_tmo_brst_stats(
 221                 const struct rte_event_timer_adapter *adptr,
 222                 struct rte_event_timer **tim, const uint64_t timeout_tick,
 223                 const uint16_t nb_timers);
 224 void timvf_set_chunk_refill(struct timvf_ring * const timr, uint8_t use_fpa);
 225
 226 #endif /* __TIMVF_EVDEV_H__ */