2 * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2017 Cavium, Inc
6 #ifndef __TIMVF_EVDEV_H__
7 #define __TIMVF_EVDEV_H__
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_debug.h>
13 #include <rte_eventdev.h>
14 #include <rte_event_timer_adapter.h>
15 #include <rte_event_timer_adapter_pmd.h>
17 #include <rte_lcore.h>
19 #include <rte_malloc.h>
20 #include <rte_mbuf_pool_ops.h>
21 #include <rte_mempool.h>
22 #include <rte_memzone.h>
24 #include <rte_prefetch.h>
25 #include <rte_reciprocal.h>
27 #include <octeontx_mbox.h>
29 #define timvf_log(level, fmt, args...) \
30 rte_log(RTE_LOG_ ## level, otx_logtype_timvf, \
31 "[%s] %s() " fmt "\n", \
32 RTE_STR(event_timer_octeontx), __func__, ## args)
34 #define timvf_log_info(fmt, ...) timvf_log(INFO, fmt, ##__VA_ARGS__)
35 #define timvf_log_dbg(fmt, ...) timvf_log(DEBUG, fmt, ##__VA_ARGS__)
36 #define timvf_log_err(fmt, ...) timvf_log(ERR, fmt, ##__VA_ARGS__)
37 #define timvf_func_trace timvf_log_dbg
39 #define TIM_COPROC (8)
40 #define TIM_GET_DEV_INFO (1)
41 #define TIM_GET_RING_INFO (2)
42 #define TIM_SET_RING_INFO (3)
43 #define TIM_RING_START_CYC_GET (4)
45 #define TIM_MAX_RINGS (64)
46 #define TIM_DEV_PER_NODE (1)
47 #define TIM_VF_PER_DEV (64)
48 #define TIM_RING_PER_DEV (TIM_VF_PER_DEV)
49 #define TIM_RING_NODE_SHIFT (6)
50 #define TIM_RING_MASK ((TIM_RING_PER_DEV) - 1)
51 #define TIM_RING_INVALID (-1)
53 #define TIM_MIN_INTERVAL (1E3)
54 #define TIM_MAX_INTERVAL ((1ull << 32) - 1)
55 #define TIM_MAX_BUCKETS (1ull << 20)
56 #define TIM_CHUNK_SIZE (4096)
57 #define TIM_MAX_CHUNKS_PER_BUCKET (1ull << 32)
59 #define TIMVF_MAX_BURST (8)
61 /* TIM VF Control/Status registers (CSRs): */
63 #define TIM_VF_NRSPERR_INT (0x0)
64 #define TIM_VF_NRSPERR_INT_W1S (0x8)
65 #define TIM_VF_NRSPERR_ENA_W1C (0x10)
66 #define TIM_VF_NRSPERR_ENA_W1S (0x18)
67 #define TIM_VRING_FR_RN_CYCLES (0x20)
68 #define TIM_VRING_FR_RN_GPIOS (0x28)
69 #define TIM_VRING_FR_RN_GTI (0x30)
70 #define TIM_VRING_FR_RN_PTP (0x38)
71 #define TIM_VRING_CTL0 (0x40)
72 #define TIM_VRING_CTL1 (0x50)
73 #define TIM_VRING_CTL2 (0x60)
74 #define TIM_VRING_BASE (0x100)
75 #define TIM_VRING_AURA (0x108)
76 #define TIM_VRING_REL (0x110)
79 #define NSEC_PER_SEC 1E9
80 #define NSEC2CLK(__ns, __freq) (((__ns) * (__freq)) / NSEC_PER_SEC)
81 #define CLK2NSEC(__clk, __freq) (((__clk) * NSEC_PER_SEC) / (__freq))
83 #define timvf_read64 rte_read64_relaxed
84 #define timvf_write64 rte_write64_relaxed
86 #define TIMVF_ENABLE_STATS_ARG ("timvf_stats")
88 extern int otx_logtype_timvf;
89 static const uint16_t nb_chunk_slots = (TIM_CHUNK_SIZE / 16) - 1;
92 uint16_t domain; /* Domain id */
93 uint8_t total_timvfs; /* Total timvf available in domain */
97 TIM_CLK_SRC_SCLK = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
98 TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
99 TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
100 TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
104 struct tim_mem_bucket {
105 uint64_t first_chunk;
115 int16_t chunk_remainder;
118 uint64_t current_chunk;
122 struct tim_mem_entry {
127 struct timvf_ctrl_reg {
136 typedef uint32_t (*bkt_id)(const uint32_t bkt_tcks, const uint32_t nb_bkts);
137 typedef struct tim_mem_entry * (*refill_chunk)(
138 struct tim_mem_bucket * const bkt,
139 struct timvf_ring * const timr);
142 bkt_id get_target_bkt;
143 refill_chunk refill_chunk;
144 struct rte_reciprocal_u64 fast_div;
145 uint64_t ring_start_cyc;
147 struct tim_mem_bucket *bkt;
150 volatile uint64_t tim_arm_cnt;
156 enum timvf_clk_src clk_src;
157 uint16_t tim_ring_id;
158 } __rte_cache_aligned;
160 static __rte_always_inline uint32_t
161 bkt_mod(const uint32_t rel_bkt, const uint32_t nb_bkts)
163 return rel_bkt % nb_bkts;
166 int timvf_info(struct timvf_info *tinfo);
167 void *timvf_bar(uint8_t id, uint8_t bar);
168 int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags,
169 uint32_t *caps, const struct rte_event_timer_adapter_ops **ops,
170 uint8_t enable_stats);
172 #endif /* __TIMVF_EVDEV_H__ */