1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <rte_eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev_stats.h"
16 #include "otx2_evdev.h"
20 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
22 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
23 uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
24 struct otx2_mbox *mbox = dev->mbox;
25 struct msix_offset_rsp *msix_rsp;
28 /* Get SSO and SSOW MSIX vector offsets */
29 otx2_mbox_alloc_msg_msix_offset(mbox);
30 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
32 for (i = 0; i < nb_ports; i++)
33 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
35 for (i = 0; i < dev->nb_event_queues; i++)
36 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
42 otx2_sso_info_get(struct rte_eventdev *event_dev,
43 struct rte_event_dev_info *dev_info)
45 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
47 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
48 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
49 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
50 dev_info->max_event_queues = dev->max_event_queues;
51 dev_info->max_event_queue_flows = (1ULL << 20);
52 dev_info->max_event_queue_priority_levels = 8;
53 dev_info->max_event_priority_levels = 1;
54 dev_info->max_event_ports = dev->max_event_ports;
55 dev_info->max_event_port_dequeue_depth = 1;
56 dev_info->max_event_port_enqueue_depth = 1;
57 dev_info->max_num_events = dev->max_num_events;
58 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
59 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
60 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
61 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
62 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
63 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
67 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
69 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
73 val |= 0ULL << 12; /* SET 0 */
74 val |= 0x8000800080000000; /* Dont modify rest of the masks */
75 val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */
77 otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
81 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
82 const uint8_t queues[], const uint8_t priorities[],
85 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
89 RTE_SET_USED(priorities);
90 for (link = 0; link < nb_links; link++) {
92 struct otx2_ssogws_dual *ws = port;
95 sso_port_link_modify((struct otx2_ssogws *)
96 &ws->ws_state[0], queues[link], true);
97 sso_port_link_modify((struct otx2_ssogws *)
98 &ws->ws_state[1], queues[link], true);
100 struct otx2_ssogws *ws = port;
103 sso_port_link_modify(ws, queues[link], true);
106 sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
108 return (int)nb_links;
112 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
113 uint8_t queues[], uint16_t nb_unlinks)
115 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
119 for (unlink = 0; unlink < nb_unlinks; unlink++) {
121 struct otx2_ssogws_dual *ws = port;
124 sso_port_link_modify((struct otx2_ssogws *)
125 &ws->ws_state[0], queues[unlink],
127 sso_port_link_modify((struct otx2_ssogws *)
128 &ws->ws_state[1], queues[unlink],
131 struct otx2_ssogws *ws = port;
134 sso_port_link_modify(ws, queues[unlink], false);
137 sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
139 return (int)nb_unlinks;
143 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
144 uint16_t nb_lf, uint8_t attach)
147 struct rsrc_attach_req *req;
149 req = otx2_mbox_alloc_msg_attach_resources(mbox);
161 if (otx2_mbox_process(mbox) < 0)
164 struct rsrc_detach_req *req;
166 req = otx2_mbox_alloc_msg_detach_resources(mbox);
178 if (otx2_mbox_process(mbox) < 0)
186 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
187 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
196 struct sso_lf_alloc_req *req_ggrp;
197 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
198 req_ggrp->hwgrps = nb_lf;
203 struct ssow_lf_alloc_req *req_hws;
204 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
205 req_hws->hws = nb_lf;
215 struct sso_lf_free_req *req_ggrp;
216 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
217 req_ggrp->hwgrps = nb_lf;
222 struct ssow_lf_free_req *req_hws;
223 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
224 req_hws->hws = nb_lf;
232 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
236 if (alloc && type == SSO_LF_GGRP) {
237 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
239 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
240 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
241 dev->iue = rsp_ggrp->in_unit_entries;
248 otx2_sso_port_release(void *port)
254 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
256 RTE_SET_USED(event_dev);
257 RTE_SET_USED(queue_id);
261 sso_clr_links(const struct rte_eventdev *event_dev)
263 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
266 for (i = 0; i < dev->nb_event_ports; i++) {
268 struct otx2_ssogws_dual *ws;
270 ws = event_dev->data->ports[i];
271 for (j = 0; j < dev->nb_event_queues; j++) {
272 sso_port_link_modify((struct otx2_ssogws *)
273 &ws->ws_state[0], j, false);
274 sso_port_link_modify((struct otx2_ssogws *)
275 &ws->ws_state[1], j, false);
278 struct otx2_ssogws *ws;
280 ws = event_dev->data->ports[i];
281 for (j = 0; j < dev->nb_event_queues; j++)
282 sso_port_link_modify(ws, j, false);
288 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
290 ws->tag_op = base + SSOW_LF_GWS_TAG;
291 ws->wqp_op = base + SSOW_LF_GWS_WQP;
292 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
293 ws->swtp_op = base + SSOW_LF_GWS_SWTP;
294 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
295 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
299 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
301 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
302 struct otx2_mbox *mbox = dev->mbox;
307 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
309 nb_lf = dev->nb_event_ports * 2;
310 /* Ask AF to attach required LFs. */
311 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
313 otx2_err("Failed to attach SSO GWS LF");
317 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
318 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
319 otx2_err("Failed to init SSO GWS LF");
323 for (i = 0; i < dev->nb_event_ports; i++) {
324 struct otx2_ssogws_dual *ws;
327 /* Free memory prior to re-allocation if needed */
328 if (event_dev->data->ports[i] != NULL) {
329 ws = event_dev->data->ports[i];
334 /* Allocate event port memory */
335 ws = rte_zmalloc_socket("otx2_sso_ws",
336 sizeof(struct otx2_ssogws_dual),
338 event_dev->data->socket_id);
340 otx2_err("Failed to alloc memory for port=%d", i);
346 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
347 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
350 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
351 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
354 event_dev->data->ports[i] = ws;
358 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
359 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
366 sso_configure_ports(const struct rte_eventdev *event_dev)
368 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
369 struct otx2_mbox *mbox = dev->mbox;
373 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
375 nb_lf = dev->nb_event_ports;
376 /* Ask AF to attach required LFs. */
377 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
379 otx2_err("Failed to attach SSO GWS LF");
383 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
384 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
385 otx2_err("Failed to init SSO GWS LF");
389 for (i = 0; i < nb_lf; i++) {
390 struct otx2_ssogws *ws;
393 /* Free memory prior to re-allocation if needed */
394 if (event_dev->data->ports[i] != NULL) {
395 ws = event_dev->data->ports[i];
400 /* Allocate event port memory */
401 ws = rte_zmalloc_socket("otx2_sso_ws",
402 sizeof(struct otx2_ssogws),
404 event_dev->data->socket_id);
406 otx2_err("Failed to alloc memory for port=%d", i);
412 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
413 sso_set_port_ops(ws, base);
415 event_dev->data->ports[i] = ws;
419 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
420 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
427 sso_configure_queues(const struct rte_eventdev *event_dev)
429 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
430 struct otx2_mbox *mbox = dev->mbox;
434 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
436 nb_lf = dev->nb_event_queues;
437 /* Ask AF to attach required LFs. */
438 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
440 otx2_err("Failed to attach SSO GGRP LF");
444 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
445 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
446 otx2_err("Failed to init SSO GGRP LF");
454 sso_xaq_allocate(struct otx2_sso_evdev *dev)
456 const struct rte_memzone *mz;
457 struct npa_aura_s *aura;
458 static int reconfig_cnt;
459 char pool_name[RTE_MEMZONE_NAMESIZE];
464 rte_mempool_free(dev->xaq_pool);
467 * Allocate memory for Add work backpressure.
469 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
471 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
473 sizeof(struct npa_aura_s),
475 RTE_MEMZONE_IOVA_CONTIG,
478 otx2_err("Failed to allocate mem for fcmem");
482 dev->fc_iova = mz->iova;
483 dev->fc_mem = mz->addr;
485 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
486 memset(aura, 0, sizeof(struct npa_aura_s));
489 aura->fc_addr = dev->fc_iova;
490 aura->fc_hyst_bits = 0; /* Store count on all updates */
492 /* Taken from HRM 14.3.3(4) */
493 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
495 xaq_cnt += dev->xae_cnt / dev->xae_waes;
497 xaq_cnt += (dev->iue / dev->xae_waes) +
498 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
500 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
501 /* Setup XAQ based on number of nb queues. */
502 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
503 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
504 xaq_cnt, dev->xaq_buf_size, 0, 0,
507 if (dev->xaq_pool == NULL) {
508 otx2_err("Unable to create empty mempool.");
509 rte_memzone_free(mz);
513 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
514 rte_mbuf_platform_mempool_ops(), aura);
516 otx2_err("Unable to set xaqpool ops.");
520 rc = rte_mempool_populate_default(dev->xaq_pool);
522 otx2_err("Unable to set populate xaqpool.");
526 /* When SW does addwork (enqueue) check if there is space in XAQ by
527 * comparing fc_addr above against the xaq_lmt calculated below.
528 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
529 * to request XAQ to cache them even before enqueue is called.
531 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
532 dev->nb_event_queues);
533 dev->nb_xaq_cfg = xaq_cnt;
537 rte_mempool_free(dev->xaq_pool);
538 rte_memzone_free(mz);
543 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
545 struct otx2_mbox *mbox = dev->mbox;
546 struct sso_hw_setconfig *req;
548 otx2_sso_dbg("Configuring XAQ for GGRPs");
549 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
550 req->npa_pf_func = otx2_npa_pf_func_get();
551 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
552 req->hwgrps = dev->nb_event_queues;
554 return otx2_mbox_process(mbox);
558 sso_lf_teardown(struct otx2_sso_evdev *dev,
559 enum otx2_sso_lf_type lf_type)
565 nb_lf = dev->nb_event_queues;
568 nb_lf = dev->nb_event_ports;
569 nb_lf *= dev->dual_ws ? 2 : 1;
575 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
576 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
580 otx2_sso_configure(const struct rte_eventdev *event_dev)
582 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
583 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
588 deq_tmo_ns = conf->dequeue_timeout_ns;
591 deq_tmo_ns = dev->min_dequeue_timeout_ns;
593 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
594 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
595 otx2_err("Unsupported dequeue timeout requested");
599 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
600 dev->is_timeout_deq = 1;
602 dev->deq_tmo_ns = deq_tmo_ns;
604 if (conf->nb_event_ports > dev->max_event_ports ||
605 conf->nb_event_queues > dev->max_event_queues) {
606 otx2_err("Unsupported event queues/ports requested");
610 if (conf->nb_event_port_dequeue_depth > 1) {
611 otx2_err("Unsupported event port deq depth requested");
615 if (conf->nb_event_port_enqueue_depth > 1) {
616 otx2_err("Unsupported event port enq depth requested");
621 sso_unregister_irqs(event_dev);
623 if (dev->nb_event_queues) {
624 /* Finit any previous queues. */
625 sso_lf_teardown(dev, SSO_LF_GGRP);
627 if (dev->nb_event_ports) {
628 /* Finit any previous ports. */
629 sso_lf_teardown(dev, SSO_LF_GWS);
632 dev->nb_event_queues = conf->nb_event_queues;
633 dev->nb_event_ports = conf->nb_event_ports;
636 rc = sso_configure_dual_ports(event_dev);
638 rc = sso_configure_ports(event_dev);
641 otx2_err("Failed to configure event ports");
645 if (sso_configure_queues(event_dev) < 0) {
646 otx2_err("Failed to configure event queues");
651 if (sso_xaq_allocate(dev) < 0) {
653 goto teardown_hwggrp;
656 /* Clear any prior port-queue mapping. */
657 sso_clr_links(event_dev);
658 rc = sso_ggrp_alloc_xaq(dev);
660 otx2_err("Failed to alloc xaq to ggrp %d", rc);
661 goto teardown_hwggrp;
664 rc = sso_get_msix_offsets(event_dev);
666 otx2_err("Failed to get msix offsets %d", rc);
667 goto teardown_hwggrp;
670 rc = sso_register_irqs(event_dev);
672 otx2_err("Failed to register irq %d", rc);
673 goto teardown_hwggrp;
681 sso_lf_teardown(dev, SSO_LF_GGRP);
683 sso_lf_teardown(dev, SSO_LF_GWS);
684 dev->nb_event_queues = 0;
685 dev->nb_event_ports = 0;
691 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
692 struct rte_event_queue_conf *queue_conf)
694 RTE_SET_USED(event_dev);
695 RTE_SET_USED(queue_id);
697 queue_conf->nb_atomic_flows = (1ULL << 20);
698 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
699 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
700 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
704 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
705 const struct rte_event_queue_conf *queue_conf)
707 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
708 struct otx2_mbox *mbox = dev->mbox;
709 struct sso_grp_priority *req;
712 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
714 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
717 req->affinity = 0xFF;
718 /* Normalize <0-255> to <0-7> */
719 req->priority = queue_conf->priority / 32;
721 rc = otx2_mbox_process(mbox);
723 otx2_err("Failed to set priority queue=%d", queue_id);
731 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
732 struct rte_event_port_conf *port_conf)
734 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
736 RTE_SET_USED(port_id);
737 port_conf->new_event_threshold = dev->max_num_events;
738 port_conf->dequeue_depth = 1;
739 port_conf->enqueue_depth = 1;
743 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
744 const struct rte_event_port_conf *port_conf)
746 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
747 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
751 sso_func_trace("Port=%d", port_id);
752 RTE_SET_USED(port_conf);
754 if (event_dev->data->ports[port_id] == NULL) {
755 otx2_err("Invalid port Id %d", port_id);
759 for (q = 0; q < dev->nb_event_queues; q++) {
760 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
761 if (grps_base[q] == 0) {
762 otx2_err("Failed to get grp[%d] base addr", q);
767 /* Set get_work timeout for HWS */
768 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
771 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
773 rte_memcpy(ws->grps_base, grps_base,
774 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
775 ws->fc_mem = dev->fc_mem;
776 ws->xaq_lmt = dev->xaq_lmt;
777 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
778 ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
779 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
780 ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
782 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
783 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
785 rte_memcpy(ws->grps_base, grps_base,
786 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
787 ws->fc_mem = dev->fc_mem;
788 ws->xaq_lmt = dev->xaq_lmt;
789 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
792 otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
798 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
801 RTE_SET_USED(event_dev);
802 *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
808 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
810 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
812 fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base);
813 fprintf(f, "SSOW_LF_GWS_LINKS 0x%" PRIx64 "\n",
814 otx2_read64(base + SSOW_LF_GWS_LINKS));
815 fprintf(f, "SSOW_LF_GWS_PENDWQP 0x%" PRIx64 "\n",
816 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
817 fprintf(f, "SSOW_LF_GWS_PENDSTATE 0x%" PRIx64 "\n",
818 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
819 fprintf(f, "SSOW_LF_GWS_NW_TIM 0x%" PRIx64 "\n",
820 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
821 fprintf(f, "SSOW_LF_GWS_TAG 0x%" PRIx64 "\n",
822 otx2_read64(base + SSOW_LF_GWS_TAG));
823 fprintf(f, "SSOW_LF_GWS_WQP 0x%" PRIx64 "\n",
824 otx2_read64(base + SSOW_LF_GWS_TAG));
825 fprintf(f, "SSOW_LF_GWS_SWTP 0x%" PRIx64 "\n",
826 otx2_read64(base + SSOW_LF_GWS_SWTP));
827 fprintf(f, "SSOW_LF_GWS_PENDTAG 0x%" PRIx64 "\n",
828 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
832 ssoggrp_dump(uintptr_t base, FILE *f)
834 fprintf(f, "SSO_LF_GGRP Base addr 0x%" PRIx64 "\n", (uint64_t)base);
835 fprintf(f, "SSO_LF_GGRP_QCTL 0x%" PRIx64 "\n",
836 otx2_read64(base + SSO_LF_GGRP_QCTL));
837 fprintf(f, "SSO_LF_GGRP_XAQ_CNT 0x%" PRIx64 "\n",
838 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
839 fprintf(f, "SSO_LF_GGRP_INT_THR 0x%" PRIx64 "\n",
840 otx2_read64(base + SSO_LF_GGRP_INT_THR));
841 fprintf(f, "SSO_LF_GGRP_INT_CNT 0x%" PRIX64 "\n",
842 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
843 fprintf(f, "SSO_LF_GGRP_AQ_CNT 0x%" PRIX64 "\n",
844 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
845 fprintf(f, "SSO_LF_GGRP_AQ_THR 0x%" PRIX64 "\n",
846 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
847 fprintf(f, "SSO_LF_GGRP_MISC_CNT 0x%" PRIx64 "\n",
848 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
852 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
854 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
858 fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
859 "dual_ws" : "single_ws");
860 /* Dump SSOW registers */
861 for (port = 0; port < dev->nb_event_ports; port++) {
863 struct otx2_ssogws_dual *ws =
864 event_dev->data->ports[port];
866 fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
868 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
869 fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
871 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
873 fprintf(f, "[%s]SSO single workslot[%d] dump\n",
875 ssogws_dump(event_dev->data->ports[port], f);
879 /* Dump SSO registers */
880 for (queue = 0; queue < dev->nb_event_queues; queue++) {
881 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
883 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
884 ssoggrp_dump(ws->grps_base[queue], f);
886 struct otx2_ssogws *ws = event_dev->data->ports[0];
887 ssoggrp_dump(ws->grps_base[queue], f);
892 /* Initialize and register event driver with DPDK Application */
893 static struct rte_eventdev_ops otx2_sso_ops = {
894 .dev_infos_get = otx2_sso_info_get,
895 .dev_configure = otx2_sso_configure,
896 .queue_def_conf = otx2_sso_queue_def_conf,
897 .queue_setup = otx2_sso_queue_setup,
898 .queue_release = otx2_sso_queue_release,
899 .port_def_conf = otx2_sso_port_def_conf,
900 .port_setup = otx2_sso_port_setup,
901 .port_release = otx2_sso_port_release,
902 .port_link = otx2_sso_port_link,
903 .port_unlink = otx2_sso_port_unlink,
904 .timeout_ticks = otx2_sso_timeout_ticks,
906 .xstats_get = otx2_sso_xstats_get,
907 .xstats_reset = otx2_sso_xstats_reset,
908 .xstats_get_names = otx2_sso_xstats_get_names,
910 .dump = otx2_sso_dump,
913 #define OTX2_SSO_XAE_CNT "xae_cnt"
916 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
918 struct rte_kvargs *kvlist;
922 kvlist = rte_kvargs_parse(devargs->args, NULL);
926 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
929 rte_kvargs_free(kvlist);
933 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
935 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
936 sizeof(struct otx2_sso_evdev),
941 otx2_sso_remove(struct rte_pci_device *pci_dev)
943 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
946 static const struct rte_pci_id pci_sso_map[] = {
948 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
949 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
956 static struct rte_pci_driver pci_sso = {
957 .id_table = pci_sso_map,
958 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
959 .probe = otx2_sso_probe,
960 .remove = otx2_sso_remove,
964 otx2_sso_init(struct rte_eventdev *event_dev)
966 struct free_rsrcs_rsp *rsrc_cnt;
967 struct rte_pci_device *pci_dev;
968 struct otx2_sso_evdev *dev;
971 event_dev->dev_ops = &otx2_sso_ops;
972 /* For secondary processes, the primary has done all the work */
973 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
976 dev = sso_pmd_priv(event_dev);
978 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
980 /* Initialize the base otx2_dev object */
981 rc = otx2_dev_init(pci_dev, dev);
983 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
987 /* Get SSO and SSOW MSIX rsrc cnt */
988 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
989 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
991 otx2_err("Unable to get free rsrc count");
992 goto otx2_dev_uninit;
994 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
995 rsrc_cnt->ssow, rsrc_cnt->npa);
997 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
998 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
999 /* Grab the NPA LF if required */
1000 rc = otx2_npa_lf_init(pci_dev, dev);
1002 otx2_err("Unable to init NPA lf. It might not be provisioned");
1003 goto otx2_dev_uninit;
1006 dev->drv_inited = true;
1007 dev->is_timeout_deq = 0;
1008 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1009 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1010 dev->max_num_events = -1;
1011 dev->nb_event_queues = 0;
1012 dev->nb_event_ports = 0;
1014 if (!dev->max_event_ports || !dev->max_event_queues) {
1015 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1016 dev->max_event_queues, dev->max_event_ports);
1018 goto otx2_npa_lf_uninit;
1022 sso_parse_devargs(dev, pci_dev->device.devargs);
1024 otx2_sso_dbg("Using dual workslot mode");
1025 dev->max_event_ports = dev->max_event_ports / 2;
1027 otx2_sso_dbg("Using single workslot mode");
1030 otx2_sso_pf_func_set(dev->pf_func);
1031 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1032 event_dev->data->name, dev->max_event_queues,
1033 dev->max_event_ports);
1041 otx2_dev_fini(pci_dev, dev);
1047 otx2_sso_fini(struct rte_eventdev *event_dev)
1049 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1050 struct rte_pci_device *pci_dev;
1052 /* For secondary processes, nothing to be done */
1053 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1056 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1058 if (!dev->drv_inited)
1061 dev->drv_inited = false;
1065 if (otx2_npa_lf_active(dev)) {
1066 otx2_info("Common resource in use by other devices");
1070 otx2_dev_fini(pci_dev, dev);
1075 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1076 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1077 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1078 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>");