1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <rte_eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev_stats.h"
16 #include "otx2_evdev.h"
18 #include "otx2_tim_evdev.h"
21 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
23 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
24 uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
25 struct otx2_mbox *mbox = dev->mbox;
26 struct msix_offset_rsp *msix_rsp;
29 /* Get SSO and SSOW MSIX vector offsets */
30 otx2_mbox_alloc_msg_msix_offset(mbox);
31 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
33 for (i = 0; i < nb_ports; i++)
34 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
36 for (i = 0; i < dev->nb_event_queues; i++)
37 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
43 sso_fastpath_fns_set(struct rte_eventdev *event_dev)
45 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
47 const event_dequeue_t ssogws_deq[2][2][2][2][2][2] = {
48 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
49 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_ ##name,
50 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
54 const event_dequeue_burst_t ssogws_deq_burst[2][2][2][2][2][2] = {
55 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
56 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_burst_ ##name,
57 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
61 const event_dequeue_t ssogws_deq_timeout[2][2][2][2][2][2] = {
62 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
63 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_timeout_ ##name,
64 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
68 const event_dequeue_burst_t
69 ssogws_deq_timeout_burst[2][2][2][2][2][2] = {
70 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
71 [f5][f4][f3][f2][f1][f0] = \
72 otx2_ssogws_deq_timeout_burst_ ##name,
73 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
77 const event_dequeue_t ssogws_deq_seg[2][2][2][2][2][2] = {
78 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
79 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_ ##name,
80 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
84 const event_dequeue_burst_t ssogws_deq_seg_burst[2][2][2][2][2][2] = {
85 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
86 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_burst_ ##name,
87 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
91 const event_dequeue_t ssogws_deq_seg_timeout[2][2][2][2][2][2] = {
92 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
93 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_timeout_ ##name,
94 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
98 const event_dequeue_burst_t
99 ssogws_deq_seg_timeout_burst[2][2][2][2][2][2] = {
100 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
101 [f5][f4][f3][f2][f1][f0] = \
102 otx2_ssogws_deq_seg_timeout_burst_ ##name,
103 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
109 const event_dequeue_t ssogws_dual_deq[2][2][2][2][2][2] = {
110 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
111 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_ ##name,
112 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
116 const event_dequeue_burst_t ssogws_dual_deq_burst[2][2][2][2][2][2] = {
117 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
118 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_burst_ ##name,
119 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
123 const event_dequeue_t ssogws_dual_deq_timeout[2][2][2][2][2][2] = {
124 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
125 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_timeout_ ##name,
126 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
130 const event_dequeue_burst_t
131 ssogws_dual_deq_timeout_burst[2][2][2][2][2][2] = {
132 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
133 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_timeout_burst_ ##name,
134 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
138 const event_dequeue_t ssogws_dual_deq_seg[2][2][2][2][2][2] = {
139 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
140 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_seg_ ##name,
141 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
145 const event_dequeue_burst_t
146 ssogws_dual_deq_seg_burst[2][2][2][2][2][2] = {
147 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
148 [f5][f4][f3][f2][f1][f0] = \
149 otx2_ssogws_dual_deq_seg_burst_ ##name,
150 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
154 const event_dequeue_t ssogws_dual_deq_seg_timeout[2][2][2][2][2][2] = {
155 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
156 [f5][f4][f3][f2][f1][f0] = \
157 otx2_ssogws_dual_deq_seg_timeout_ ##name,
158 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
162 const event_dequeue_burst_t
163 ssogws_dual_deq_seg_timeout_burst[2][2][2][2][2][2] = {
164 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
165 [f5][f4][f3][f2][f1][f0] = \
166 otx2_ssogws_dual_deq_seg_timeout_burst_ ##name,
167 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
172 const event_tx_adapter_enqueue ssogws_tx_adptr_enq[2][2][2][2][2][2] = {
173 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
174 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_tx_adptr_enq_ ## name,
175 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
179 const event_tx_adapter_enqueue
180 ssogws_tx_adptr_enq_seg[2][2][2][2][2][2] = {
181 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
182 [f5][f4][f3][f2][f1][f0] = \
183 otx2_ssogws_tx_adptr_enq_seg_ ## name,
184 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
188 const event_tx_adapter_enqueue
189 ssogws_dual_tx_adptr_enq[2][2][2][2][2][2] = {
190 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
191 [f5][f4][f3][f2][f1][f0] = \
192 otx2_ssogws_dual_tx_adptr_enq_ ## name,
193 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
197 const event_tx_adapter_enqueue
198 ssogws_dual_tx_adptr_enq_seg[2][2][2][2][2][2] = {
199 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
200 [f5][f4][f3][f2][f1][f0] = \
201 otx2_ssogws_dual_tx_adptr_enq_seg_ ## name,
202 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
206 event_dev->enqueue = otx2_ssogws_enq;
207 event_dev->enqueue_burst = otx2_ssogws_enq_burst;
208 event_dev->enqueue_new_burst = otx2_ssogws_enq_new_burst;
209 event_dev->enqueue_forward_burst = otx2_ssogws_enq_fwd_burst;
210 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
211 event_dev->dequeue = ssogws_deq_seg
212 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
213 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
214 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
215 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
216 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
217 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
218 event_dev->dequeue_burst = ssogws_deq_seg_burst
219 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
220 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
221 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
222 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
223 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
224 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
225 if (dev->is_timeout_deq) {
226 event_dev->dequeue = ssogws_deq_seg_timeout
227 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
228 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
229 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
230 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
231 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
232 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
233 event_dev->dequeue_burst =
234 ssogws_deq_seg_timeout_burst
235 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
236 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
237 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
238 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
239 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
240 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
243 event_dev->dequeue = ssogws_deq
244 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
245 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
246 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
247 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
248 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
249 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
250 event_dev->dequeue_burst = ssogws_deq_burst
251 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
252 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
253 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
254 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
255 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
256 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
257 if (dev->is_timeout_deq) {
258 event_dev->dequeue = ssogws_deq_timeout
259 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
260 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
261 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
262 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
263 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
264 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
265 event_dev->dequeue_burst =
266 ssogws_deq_timeout_burst
267 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
268 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
269 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
270 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
271 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
272 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
276 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
277 /* [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
278 event_dev->txa_enqueue = ssogws_tx_adptr_enq_seg
279 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
280 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
281 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
282 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
283 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
284 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
286 event_dev->txa_enqueue = ssogws_tx_adptr_enq
287 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
288 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
289 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
290 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
291 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
292 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
296 event_dev->enqueue = otx2_ssogws_dual_enq;
297 event_dev->enqueue_burst = otx2_ssogws_dual_enq_burst;
298 event_dev->enqueue_new_burst =
299 otx2_ssogws_dual_enq_new_burst;
300 event_dev->enqueue_forward_burst =
301 otx2_ssogws_dual_enq_fwd_burst;
303 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
304 event_dev->dequeue = ssogws_dual_deq_seg
305 [!!(dev->rx_offloads &
306 NIX_RX_OFFLOAD_TSTAMP_F)]
307 [!!(dev->rx_offloads &
308 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
309 [!!(dev->rx_offloads &
310 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
311 [!!(dev->rx_offloads &
312 NIX_RX_OFFLOAD_CHECKSUM_F)]
313 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
314 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
315 event_dev->dequeue_burst = ssogws_dual_deq_seg_burst
316 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
317 [!!(dev->rx_offloads &
318 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
319 [!!(dev->rx_offloads &
320 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
321 [!!(dev->rx_offloads &
322 NIX_RX_OFFLOAD_CHECKSUM_F)]
323 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
324 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
325 if (dev->is_timeout_deq) {
327 ssogws_dual_deq_seg_timeout
328 [!!(dev->rx_offloads &
329 NIX_RX_OFFLOAD_TSTAMP_F)]
330 [!!(dev->rx_offloads &
331 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
332 [!!(dev->rx_offloads &
333 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
334 [!!(dev->rx_offloads &
335 NIX_RX_OFFLOAD_CHECKSUM_F)]
336 [!!(dev->rx_offloads &
337 NIX_RX_OFFLOAD_PTYPE_F)]
338 [!!(dev->rx_offloads &
339 NIX_RX_OFFLOAD_RSS_F)];
340 event_dev->dequeue_burst =
341 ssogws_dual_deq_seg_timeout_burst
342 [!!(dev->rx_offloads &
343 NIX_RX_OFFLOAD_TSTAMP_F)]
344 [!!(dev->rx_offloads &
345 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
346 [!!(dev->rx_offloads &
347 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
348 [!!(dev->rx_offloads &
349 NIX_RX_OFFLOAD_CHECKSUM_F)]
350 [!!(dev->rx_offloads &
351 NIX_RX_OFFLOAD_PTYPE_F)]
352 [!!(dev->rx_offloads &
353 NIX_RX_OFFLOAD_RSS_F)];
356 event_dev->dequeue = ssogws_dual_deq
357 [!!(dev->rx_offloads &
358 NIX_RX_OFFLOAD_TSTAMP_F)]
359 [!!(dev->rx_offloads &
360 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
361 [!!(dev->rx_offloads &
362 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
363 [!!(dev->rx_offloads &
364 NIX_RX_OFFLOAD_CHECKSUM_F)]
365 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
366 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
367 event_dev->dequeue_burst = ssogws_dual_deq_burst
368 [!!(dev->rx_offloads &
369 NIX_RX_OFFLOAD_TSTAMP_F)]
370 [!!(dev->rx_offloads &
371 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
372 [!!(dev->rx_offloads &
373 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
374 [!!(dev->rx_offloads &
375 NIX_RX_OFFLOAD_CHECKSUM_F)]
376 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
377 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
378 if (dev->is_timeout_deq) {
380 ssogws_dual_deq_timeout
381 [!!(dev->rx_offloads &
382 NIX_RX_OFFLOAD_TSTAMP_F)]
383 [!!(dev->rx_offloads &
384 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
385 [!!(dev->rx_offloads &
386 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
387 [!!(dev->rx_offloads &
388 NIX_RX_OFFLOAD_CHECKSUM_F)]
389 [!!(dev->rx_offloads &
390 NIX_RX_OFFLOAD_PTYPE_F)]
391 [!!(dev->rx_offloads &
392 NIX_RX_OFFLOAD_RSS_F)];
393 event_dev->dequeue_burst =
394 ssogws_dual_deq_timeout_burst
395 [!!(dev->rx_offloads &
396 NIX_RX_OFFLOAD_TSTAMP_F)]
397 [!!(dev->rx_offloads &
398 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
399 [!!(dev->rx_offloads &
400 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
401 [!!(dev->rx_offloads &
402 NIX_RX_OFFLOAD_CHECKSUM_F)]
403 [!!(dev->rx_offloads &
404 NIX_RX_OFFLOAD_PTYPE_F)]
405 [!!(dev->rx_offloads &
406 NIX_RX_OFFLOAD_RSS_F)];
410 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
411 /* [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
412 event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq_seg
413 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
414 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
415 [!!(dev->tx_offloads &
416 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
417 [!!(dev->tx_offloads &
418 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
419 [!!(dev->tx_offloads &
420 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
421 [!!(dev->tx_offloads &
422 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
424 event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq
425 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
426 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
427 [!!(dev->tx_offloads &
428 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
429 [!!(dev->tx_offloads &
430 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
431 [!!(dev->tx_offloads &
432 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
433 [!!(dev->tx_offloads &
434 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
438 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
443 otx2_sso_info_get(struct rte_eventdev *event_dev,
444 struct rte_event_dev_info *dev_info)
446 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
448 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
449 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
450 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
451 dev_info->max_event_queues = dev->max_event_queues;
452 dev_info->max_event_queue_flows = (1ULL << 20);
453 dev_info->max_event_queue_priority_levels = 8;
454 dev_info->max_event_priority_levels = 1;
455 dev_info->max_event_ports = dev->max_event_ports;
456 dev_info->max_event_port_dequeue_depth = 1;
457 dev_info->max_event_port_enqueue_depth = 1;
458 dev_info->max_num_events = dev->max_num_events;
459 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
460 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
461 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
462 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
463 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
464 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
468 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
470 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
474 val |= 0ULL << 12; /* SET 0 */
475 val |= 0x8000800080000000; /* Dont modify rest of the masks */
476 val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */
478 otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
482 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
483 const uint8_t queues[], const uint8_t priorities[],
486 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
490 RTE_SET_USED(priorities);
491 for (link = 0; link < nb_links; link++) {
493 struct otx2_ssogws_dual *ws = port;
496 sso_port_link_modify((struct otx2_ssogws *)
497 &ws->ws_state[0], queues[link], true);
498 sso_port_link_modify((struct otx2_ssogws *)
499 &ws->ws_state[1], queues[link], true);
501 struct otx2_ssogws *ws = port;
504 sso_port_link_modify(ws, queues[link], true);
507 sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
509 return (int)nb_links;
513 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
514 uint8_t queues[], uint16_t nb_unlinks)
516 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
520 for (unlink = 0; unlink < nb_unlinks; unlink++) {
522 struct otx2_ssogws_dual *ws = port;
525 sso_port_link_modify((struct otx2_ssogws *)
526 &ws->ws_state[0], queues[unlink],
528 sso_port_link_modify((struct otx2_ssogws *)
529 &ws->ws_state[1], queues[unlink],
532 struct otx2_ssogws *ws = port;
535 sso_port_link_modify(ws, queues[unlink], false);
538 sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
540 return (int)nb_unlinks;
544 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
545 uint16_t nb_lf, uint8_t attach)
548 struct rsrc_attach_req *req;
550 req = otx2_mbox_alloc_msg_attach_resources(mbox);
562 if (otx2_mbox_process(mbox) < 0)
565 struct rsrc_detach_req *req;
567 req = otx2_mbox_alloc_msg_detach_resources(mbox);
579 if (otx2_mbox_process(mbox) < 0)
587 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
588 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
597 struct sso_lf_alloc_req *req_ggrp;
598 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
599 req_ggrp->hwgrps = nb_lf;
604 struct ssow_lf_alloc_req *req_hws;
605 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
606 req_hws->hws = nb_lf;
616 struct sso_lf_free_req *req_ggrp;
617 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
618 req_ggrp->hwgrps = nb_lf;
623 struct ssow_lf_free_req *req_hws;
624 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
625 req_hws->hws = nb_lf;
633 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
637 if (alloc && type == SSO_LF_GGRP) {
638 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
640 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
641 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
642 dev->iue = rsp_ggrp->in_unit_entries;
649 otx2_sso_port_release(void *port)
655 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
657 RTE_SET_USED(event_dev);
658 RTE_SET_USED(queue_id);
662 sso_clr_links(const struct rte_eventdev *event_dev)
664 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
667 for (i = 0; i < dev->nb_event_ports; i++) {
669 struct otx2_ssogws_dual *ws;
671 ws = event_dev->data->ports[i];
672 for (j = 0; j < dev->nb_event_queues; j++) {
673 sso_port_link_modify((struct otx2_ssogws *)
674 &ws->ws_state[0], j, false);
675 sso_port_link_modify((struct otx2_ssogws *)
676 &ws->ws_state[1], j, false);
679 struct otx2_ssogws *ws;
681 ws = event_dev->data->ports[i];
682 for (j = 0; j < dev->nb_event_queues; j++)
683 sso_port_link_modify(ws, j, false);
689 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
691 ws->tag_op = base + SSOW_LF_GWS_TAG;
692 ws->wqp_op = base + SSOW_LF_GWS_WQP;
693 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
694 ws->swtp_op = base + SSOW_LF_GWS_SWTP;
695 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
696 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
700 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
702 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
703 struct otx2_mbox *mbox = dev->mbox;
708 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
710 nb_lf = dev->nb_event_ports * 2;
711 /* Ask AF to attach required LFs. */
712 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
714 otx2_err("Failed to attach SSO GWS LF");
718 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
719 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
720 otx2_err("Failed to init SSO GWS LF");
724 for (i = 0; i < dev->nb_event_ports; i++) {
725 struct otx2_ssogws_dual *ws;
728 /* Free memory prior to re-allocation if needed */
729 if (event_dev->data->ports[i] != NULL) {
730 ws = event_dev->data->ports[i];
735 /* Allocate event port memory */
736 ws = rte_zmalloc_socket("otx2_sso_ws",
737 sizeof(struct otx2_ssogws_dual),
739 event_dev->data->socket_id);
741 otx2_err("Failed to alloc memory for port=%d", i);
747 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
748 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
751 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
752 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
755 event_dev->data->ports[i] = ws;
759 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
760 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
767 sso_configure_ports(const struct rte_eventdev *event_dev)
769 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
770 struct otx2_mbox *mbox = dev->mbox;
774 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
776 nb_lf = dev->nb_event_ports;
777 /* Ask AF to attach required LFs. */
778 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
780 otx2_err("Failed to attach SSO GWS LF");
784 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
785 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
786 otx2_err("Failed to init SSO GWS LF");
790 for (i = 0; i < nb_lf; i++) {
791 struct otx2_ssogws *ws;
794 /* Free memory prior to re-allocation if needed */
795 if (event_dev->data->ports[i] != NULL) {
796 ws = event_dev->data->ports[i];
801 /* Allocate event port memory */
802 ws = rte_zmalloc_socket("otx2_sso_ws",
803 sizeof(struct otx2_ssogws),
805 event_dev->data->socket_id);
807 otx2_err("Failed to alloc memory for port=%d", i);
813 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
814 sso_set_port_ops(ws, base);
816 event_dev->data->ports[i] = ws;
820 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
821 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
828 sso_configure_queues(const struct rte_eventdev *event_dev)
830 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
831 struct otx2_mbox *mbox = dev->mbox;
835 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
837 nb_lf = dev->nb_event_queues;
838 /* Ask AF to attach required LFs. */
839 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
841 otx2_err("Failed to attach SSO GGRP LF");
845 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
846 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
847 otx2_err("Failed to init SSO GGRP LF");
855 sso_xaq_allocate(struct otx2_sso_evdev *dev)
857 const struct rte_memzone *mz;
858 struct npa_aura_s *aura;
859 static int reconfig_cnt;
860 char pool_name[RTE_MEMZONE_NAMESIZE];
865 rte_mempool_free(dev->xaq_pool);
868 * Allocate memory for Add work backpressure.
870 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
872 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
874 sizeof(struct npa_aura_s),
876 RTE_MEMZONE_IOVA_CONTIG,
879 otx2_err("Failed to allocate mem for fcmem");
883 dev->fc_iova = mz->iova;
884 dev->fc_mem = mz->addr;
886 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
887 memset(aura, 0, sizeof(struct npa_aura_s));
890 aura->fc_addr = dev->fc_iova;
891 aura->fc_hyst_bits = 0; /* Store count on all updates */
893 /* Taken from HRM 14.3.3(4) */
894 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
896 xaq_cnt += dev->xae_cnt / dev->xae_waes;
897 else if (dev->adptr_xae_cnt)
898 xaq_cnt += (dev->adptr_xae_cnt / dev->xae_waes) +
899 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
901 xaq_cnt += (dev->iue / dev->xae_waes) +
902 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
904 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
905 /* Setup XAQ based on number of nb queues. */
906 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
907 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
908 xaq_cnt, dev->xaq_buf_size, 0, 0,
911 if (dev->xaq_pool == NULL) {
912 otx2_err("Unable to create empty mempool.");
913 rte_memzone_free(mz);
917 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
918 rte_mbuf_platform_mempool_ops(), aura);
920 otx2_err("Unable to set xaqpool ops.");
924 rc = rte_mempool_populate_default(dev->xaq_pool);
926 otx2_err("Unable to set populate xaqpool.");
930 /* When SW does addwork (enqueue) check if there is space in XAQ by
931 * comparing fc_addr above against the xaq_lmt calculated below.
932 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
933 * to request XAQ to cache them even before enqueue is called.
935 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
936 dev->nb_event_queues);
937 dev->nb_xaq_cfg = xaq_cnt;
941 rte_mempool_free(dev->xaq_pool);
942 rte_memzone_free(mz);
947 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
949 struct otx2_mbox *mbox = dev->mbox;
950 struct sso_hw_setconfig *req;
952 otx2_sso_dbg("Configuring XAQ for GGRPs");
953 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
954 req->npa_pf_func = otx2_npa_pf_func_get();
955 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
956 req->hwgrps = dev->nb_event_queues;
958 return otx2_mbox_process(mbox);
962 sso_lf_teardown(struct otx2_sso_evdev *dev,
963 enum otx2_sso_lf_type lf_type)
969 nb_lf = dev->nb_event_queues;
972 nb_lf = dev->nb_event_ports;
973 nb_lf *= dev->dual_ws ? 2 : 1;
979 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
980 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
984 otx2_sso_configure(const struct rte_eventdev *event_dev)
986 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
987 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
992 deq_tmo_ns = conf->dequeue_timeout_ns;
995 deq_tmo_ns = dev->min_dequeue_timeout_ns;
997 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
998 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
999 otx2_err("Unsupported dequeue timeout requested");
1003 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
1004 dev->is_timeout_deq = 1;
1006 dev->deq_tmo_ns = deq_tmo_ns;
1008 if (conf->nb_event_ports > dev->max_event_ports ||
1009 conf->nb_event_queues > dev->max_event_queues) {
1010 otx2_err("Unsupported event queues/ports requested");
1014 if (conf->nb_event_port_dequeue_depth > 1) {
1015 otx2_err("Unsupported event port deq depth requested");
1019 if (conf->nb_event_port_enqueue_depth > 1) {
1020 otx2_err("Unsupported event port enq depth requested");
1024 if (dev->configured)
1025 sso_unregister_irqs(event_dev);
1027 if (dev->nb_event_queues) {
1028 /* Finit any previous queues. */
1029 sso_lf_teardown(dev, SSO_LF_GGRP);
1031 if (dev->nb_event_ports) {
1032 /* Finit any previous ports. */
1033 sso_lf_teardown(dev, SSO_LF_GWS);
1036 dev->nb_event_queues = conf->nb_event_queues;
1037 dev->nb_event_ports = conf->nb_event_ports;
1040 rc = sso_configure_dual_ports(event_dev);
1042 rc = sso_configure_ports(event_dev);
1045 otx2_err("Failed to configure event ports");
1049 if (sso_configure_queues(event_dev) < 0) {
1050 otx2_err("Failed to configure event queues");
1055 if (sso_xaq_allocate(dev) < 0) {
1057 goto teardown_hwggrp;
1060 /* Clear any prior port-queue mapping. */
1061 sso_clr_links(event_dev);
1062 rc = sso_ggrp_alloc_xaq(dev);
1064 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1065 goto teardown_hwggrp;
1068 rc = sso_get_msix_offsets(event_dev);
1070 otx2_err("Failed to get msix offsets %d", rc);
1071 goto teardown_hwggrp;
1074 rc = sso_register_irqs(event_dev);
1076 otx2_err("Failed to register irq %d", rc);
1077 goto teardown_hwggrp;
1080 dev->configured = 1;
1085 sso_lf_teardown(dev, SSO_LF_GGRP);
1087 sso_lf_teardown(dev, SSO_LF_GWS);
1088 dev->nb_event_queues = 0;
1089 dev->nb_event_ports = 0;
1090 dev->configured = 0;
1095 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
1096 struct rte_event_queue_conf *queue_conf)
1098 RTE_SET_USED(event_dev);
1099 RTE_SET_USED(queue_id);
1101 queue_conf->nb_atomic_flows = (1ULL << 20);
1102 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
1103 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
1104 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
1108 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
1109 const struct rte_event_queue_conf *queue_conf)
1111 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1112 struct otx2_mbox *mbox = dev->mbox;
1113 struct sso_grp_priority *req;
1116 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
1118 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
1119 req->grp = queue_id;
1121 req->affinity = 0xFF;
1122 /* Normalize <0-255> to <0-7> */
1123 req->priority = queue_conf->priority / 32;
1125 rc = otx2_mbox_process(mbox);
1127 otx2_err("Failed to set priority queue=%d", queue_id);
1135 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
1136 struct rte_event_port_conf *port_conf)
1138 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1140 RTE_SET_USED(port_id);
1141 port_conf->new_event_threshold = dev->max_num_events;
1142 port_conf->dequeue_depth = 1;
1143 port_conf->enqueue_depth = 1;
1147 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
1148 const struct rte_event_port_conf *port_conf)
1150 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1151 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
1155 sso_func_trace("Port=%d", port_id);
1156 RTE_SET_USED(port_conf);
1158 if (event_dev->data->ports[port_id] == NULL) {
1159 otx2_err("Invalid port Id %d", port_id);
1163 for (q = 0; q < dev->nb_event_queues; q++) {
1164 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
1165 if (grps_base[q] == 0) {
1166 otx2_err("Failed to get grp[%d] base addr", q);
1171 /* Set get_work timeout for HWS */
1172 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
1175 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
1177 rte_memcpy(ws->grps_base, grps_base,
1178 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1179 ws->fc_mem = dev->fc_mem;
1180 ws->xaq_lmt = dev->xaq_lmt;
1181 ws->tstamp = dev->tstamp;
1182 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1183 ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1184 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1185 ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1187 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
1188 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1190 rte_memcpy(ws->grps_base, grps_base,
1191 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1192 ws->fc_mem = dev->fc_mem;
1193 ws->xaq_lmt = dev->xaq_lmt;
1194 ws->tstamp = dev->tstamp;
1195 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
1198 otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
1204 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
1205 uint64_t *tmo_ticks)
1207 RTE_SET_USED(event_dev);
1208 *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
1214 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
1216 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1218 fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base);
1219 fprintf(f, "SSOW_LF_GWS_LINKS 0x%" PRIx64 "\n",
1220 otx2_read64(base + SSOW_LF_GWS_LINKS));
1221 fprintf(f, "SSOW_LF_GWS_PENDWQP 0x%" PRIx64 "\n",
1222 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
1223 fprintf(f, "SSOW_LF_GWS_PENDSTATE 0x%" PRIx64 "\n",
1224 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
1225 fprintf(f, "SSOW_LF_GWS_NW_TIM 0x%" PRIx64 "\n",
1226 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
1227 fprintf(f, "SSOW_LF_GWS_TAG 0x%" PRIx64 "\n",
1228 otx2_read64(base + SSOW_LF_GWS_TAG));
1229 fprintf(f, "SSOW_LF_GWS_WQP 0x%" PRIx64 "\n",
1230 otx2_read64(base + SSOW_LF_GWS_TAG));
1231 fprintf(f, "SSOW_LF_GWS_SWTP 0x%" PRIx64 "\n",
1232 otx2_read64(base + SSOW_LF_GWS_SWTP));
1233 fprintf(f, "SSOW_LF_GWS_PENDTAG 0x%" PRIx64 "\n",
1234 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
1238 ssoggrp_dump(uintptr_t base, FILE *f)
1240 fprintf(f, "SSO_LF_GGRP Base addr 0x%" PRIx64 "\n", (uint64_t)base);
1241 fprintf(f, "SSO_LF_GGRP_QCTL 0x%" PRIx64 "\n",
1242 otx2_read64(base + SSO_LF_GGRP_QCTL));
1243 fprintf(f, "SSO_LF_GGRP_XAQ_CNT 0x%" PRIx64 "\n",
1244 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
1245 fprintf(f, "SSO_LF_GGRP_INT_THR 0x%" PRIx64 "\n",
1246 otx2_read64(base + SSO_LF_GGRP_INT_THR));
1247 fprintf(f, "SSO_LF_GGRP_INT_CNT 0x%" PRIX64 "\n",
1248 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
1249 fprintf(f, "SSO_LF_GGRP_AQ_CNT 0x%" PRIX64 "\n",
1250 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
1251 fprintf(f, "SSO_LF_GGRP_AQ_THR 0x%" PRIX64 "\n",
1252 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
1253 fprintf(f, "SSO_LF_GGRP_MISC_CNT 0x%" PRIx64 "\n",
1254 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
1258 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
1260 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1264 fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
1265 "dual_ws" : "single_ws");
1266 /* Dump SSOW registers */
1267 for (port = 0; port < dev->nb_event_ports; port++) {
1269 struct otx2_ssogws_dual *ws =
1270 event_dev->data->ports[port];
1272 fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
1274 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
1275 fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
1277 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
1279 fprintf(f, "[%s]SSO single workslot[%d] dump\n",
1281 ssogws_dump(event_dev->data->ports[port], f);
1285 /* Dump SSO registers */
1286 for (queue = 0; queue < dev->nb_event_queues; queue++) {
1287 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
1289 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1290 ssoggrp_dump(ws->grps_base[queue], f);
1292 struct otx2_ssogws *ws = event_dev->data->ports[0];
1293 ssoggrp_dump(ws->grps_base[queue], f);
1299 otx2_handle_event(void *arg, struct rte_event event)
1301 struct rte_eventdev *event_dev = arg;
1303 if (event_dev->dev_ops->dev_stop_flush != NULL)
1304 event_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,
1305 event, event_dev->data->dev_stop_flush_arg);
1309 sso_qos_cfg(struct rte_eventdev *event_dev)
1311 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1312 struct sso_grp_qos_cfg *req;
1315 for (i = 0; i < dev->qos_queue_cnt; i++) {
1316 uint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
1317 uint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
1318 uint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
1320 if (dev->qos_parse_data[i].queue >= dev->nb_event_queues)
1323 req = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);
1324 req->xaq_limit = (dev->nb_xaq_cfg *
1325 (xaq_prcnt ? xaq_prcnt : 100)) / 100;
1326 req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *
1327 (iaq_prcnt ? iaq_prcnt : 100)) / 100;
1328 req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *
1329 (taq_prcnt ? taq_prcnt : 100)) / 100;
1332 if (dev->qos_queue_cnt)
1333 otx2_mbox_process(dev->mbox);
1337 sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
1339 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1342 for (i = 0; i < dev->nb_event_ports; i++) {
1344 struct otx2_ssogws_dual *ws;
1346 ws = event_dev->data->ports[i];
1347 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);
1348 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
1351 ws->ws_state[0].cur_grp = 0;
1352 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1353 ws->ws_state[1].cur_grp = 0;
1354 ws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;
1356 struct otx2_ssogws *ws;
1358 ws = event_dev->data->ports[i];
1362 ws->cur_tt = SSO_SYNC_EMPTY;
1368 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1369 struct otx2_ssogws temp_ws;
1371 memcpy(&temp_ws, &ws->ws_state[0],
1372 sizeof(struct otx2_ssogws_state));
1373 for (i = 0; i < dev->nb_event_queues; i++) {
1374 /* Consume all the events through HWS0 */
1375 ssogws_flush_events(&temp_ws, i, ws->grps_base[i],
1376 otx2_handle_event, event_dev);
1377 /* Enable/Disable SSO GGRP */
1378 otx2_write64(enable, ws->grps_base[i] +
1381 ws->ws_state[0].cur_grp = 0;
1382 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1384 struct otx2_ssogws *ws = event_dev->data->ports[0];
1386 for (i = 0; i < dev->nb_event_queues; i++) {
1387 /* Consume all the events through HWS0 */
1388 ssogws_flush_events(ws, i, ws->grps_base[i],
1389 otx2_handle_event, event_dev);
1390 /* Enable/Disable SSO GGRP */
1391 otx2_write64(enable, ws->grps_base[i] +
1395 ws->cur_tt = SSO_SYNC_EMPTY;
1398 /* reset SSO GWS cache */
1399 otx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);
1400 otx2_mbox_process(dev->mbox);
1404 sso_xae_reconfigure(struct rte_eventdev *event_dev)
1406 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1407 struct rte_mempool *prev_xaq_pool;
1410 if (event_dev->data->dev_started)
1411 sso_cleanup(event_dev, 0);
1413 prev_xaq_pool = dev->xaq_pool;
1414 dev->xaq_pool = NULL;
1415 rc = sso_xaq_allocate(dev);
1417 otx2_err("Failed to alloc xaq pool %d", rc);
1418 rte_mempool_free(prev_xaq_pool);
1421 rc = sso_ggrp_alloc_xaq(dev);
1423 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1424 rte_mempool_free(prev_xaq_pool);
1428 rte_mempool_free(prev_xaq_pool);
1430 if (event_dev->data->dev_started)
1431 sso_cleanup(event_dev, 1);
1437 otx2_sso_start(struct rte_eventdev *event_dev)
1440 sso_qos_cfg(event_dev);
1441 sso_cleanup(event_dev, 1);
1442 sso_fastpath_fns_set(event_dev);
1448 otx2_sso_stop(struct rte_eventdev *event_dev)
1451 sso_cleanup(event_dev, 0);
1456 otx2_sso_close(struct rte_eventdev *event_dev)
1458 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1459 uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
1462 if (!dev->configured)
1465 sso_unregister_irqs(event_dev);
1467 for (i = 0; i < dev->nb_event_queues; i++)
1470 for (i = 0; i < dev->nb_event_ports; i++)
1471 otx2_sso_port_unlink(event_dev, event_dev->data->ports[i],
1472 all_queues, dev->nb_event_queues);
1474 sso_lf_teardown(dev, SSO_LF_GGRP);
1475 sso_lf_teardown(dev, SSO_LF_GWS);
1476 dev->nb_event_ports = 0;
1477 dev->nb_event_queues = 0;
1478 rte_mempool_free(dev->xaq_pool);
1479 rte_memzone_free(rte_memzone_lookup(OTX2_SSO_FC_NAME));
1484 /* Initialize and register event driver with DPDK Application */
1485 static struct rte_eventdev_ops otx2_sso_ops = {
1486 .dev_infos_get = otx2_sso_info_get,
1487 .dev_configure = otx2_sso_configure,
1488 .queue_def_conf = otx2_sso_queue_def_conf,
1489 .queue_setup = otx2_sso_queue_setup,
1490 .queue_release = otx2_sso_queue_release,
1491 .port_def_conf = otx2_sso_port_def_conf,
1492 .port_setup = otx2_sso_port_setup,
1493 .port_release = otx2_sso_port_release,
1494 .port_link = otx2_sso_port_link,
1495 .port_unlink = otx2_sso_port_unlink,
1496 .timeout_ticks = otx2_sso_timeout_ticks,
1498 .eth_rx_adapter_caps_get = otx2_sso_rx_adapter_caps_get,
1499 .eth_rx_adapter_queue_add = otx2_sso_rx_adapter_queue_add,
1500 .eth_rx_adapter_queue_del = otx2_sso_rx_adapter_queue_del,
1501 .eth_rx_adapter_start = otx2_sso_rx_adapter_start,
1502 .eth_rx_adapter_stop = otx2_sso_rx_adapter_stop,
1504 .eth_tx_adapter_caps_get = otx2_sso_tx_adapter_caps_get,
1505 .eth_tx_adapter_queue_add = otx2_sso_tx_adapter_queue_add,
1506 .eth_tx_adapter_queue_del = otx2_sso_tx_adapter_queue_del,
1508 .timer_adapter_caps_get = otx2_tim_caps_get,
1510 .xstats_get = otx2_sso_xstats_get,
1511 .xstats_reset = otx2_sso_xstats_reset,
1512 .xstats_get_names = otx2_sso_xstats_get_names,
1514 .dump = otx2_sso_dump,
1515 .dev_start = otx2_sso_start,
1516 .dev_stop = otx2_sso_stop,
1517 .dev_close = otx2_sso_close,
1518 .dev_selftest = otx2_sso_selftest,
1521 #define OTX2_SSO_XAE_CNT "xae_cnt"
1522 #define OTX2_SSO_SINGLE_WS "single_ws"
1523 #define OTX2_SSO_GGRP_QOS "qos"
1524 #define OTX2_SSO_SELFTEST "selftest"
1527 parse_queue_param(char *value, void *opaque)
1529 struct otx2_sso_qos queue_qos = {0};
1530 uint8_t *val = (uint8_t *)&queue_qos;
1531 struct otx2_sso_evdev *dev = opaque;
1532 char *tok = strtok(value, "-");
1533 struct otx2_sso_qos *old_ptr;
1538 while (tok != NULL) {
1540 tok = strtok(NULL, "-");
1544 if (val != (&queue_qos.iaq_prcnt + 1)) {
1545 otx2_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
1549 dev->qos_queue_cnt++;
1550 old_ptr = dev->qos_parse_data;
1551 dev->qos_parse_data = rte_realloc(dev->qos_parse_data,
1552 sizeof(struct otx2_sso_qos) *
1553 dev->qos_queue_cnt, 0);
1554 if (dev->qos_parse_data == NULL) {
1555 dev->qos_parse_data = old_ptr;
1556 dev->qos_queue_cnt--;
1559 dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
1563 parse_qos_list(const char *value, void *opaque)
1565 char *s = strdup(value);
1576 if (start && start < end) {
1578 parse_queue_param(start + 1, opaque);
1589 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
1593 /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
1594 * isn't allowed. Everything is expressed in percentages, 0 represents
1597 parse_qos_list(value, opaque);
1603 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
1605 struct rte_kvargs *kvlist;
1606 uint8_t single_ws = 0;
1608 if (devargs == NULL)
1610 kvlist = rte_kvargs_parse(devargs->args, NULL);
1614 rte_kvargs_process(kvlist, OTX2_SSO_SELFTEST, &parse_kvargs_flag,
1616 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
1618 rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
1620 rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
1623 dev->dual_ws = !single_ws;
1624 rte_kvargs_free(kvlist);
1628 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1630 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1631 sizeof(struct otx2_sso_evdev),
1636 otx2_sso_remove(struct rte_pci_device *pci_dev)
1638 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
1641 static const struct rte_pci_id pci_sso_map[] = {
1643 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1644 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
1651 static struct rte_pci_driver pci_sso = {
1652 .id_table = pci_sso_map,
1653 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1654 .probe = otx2_sso_probe,
1655 .remove = otx2_sso_remove,
1659 otx2_sso_init(struct rte_eventdev *event_dev)
1661 struct free_rsrcs_rsp *rsrc_cnt;
1662 struct rte_pci_device *pci_dev;
1663 struct otx2_sso_evdev *dev;
1666 event_dev->dev_ops = &otx2_sso_ops;
1667 /* For secondary processes, the primary has done all the work */
1668 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1669 sso_fastpath_fns_set(event_dev);
1673 dev = sso_pmd_priv(event_dev);
1675 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1677 /* Initialize the base otx2_dev object */
1678 rc = otx2_dev_init(pci_dev, dev);
1680 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1684 /* Get SSO and SSOW MSIX rsrc cnt */
1685 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
1686 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
1688 otx2_err("Unable to get free rsrc count");
1689 goto otx2_dev_uninit;
1691 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
1692 rsrc_cnt->ssow, rsrc_cnt->npa);
1694 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
1695 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
1696 /* Grab the NPA LF if required */
1697 rc = otx2_npa_lf_init(pci_dev, dev);
1699 otx2_err("Unable to init NPA lf. It might not be provisioned");
1700 goto otx2_dev_uninit;
1703 dev->drv_inited = true;
1704 dev->is_timeout_deq = 0;
1705 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1706 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1707 dev->max_num_events = -1;
1708 dev->nb_event_queues = 0;
1709 dev->nb_event_ports = 0;
1711 if (!dev->max_event_ports || !dev->max_event_queues) {
1712 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1713 dev->max_event_queues, dev->max_event_ports);
1715 goto otx2_npa_lf_uninit;
1719 sso_parse_devargs(dev, pci_dev->device.devargs);
1721 otx2_sso_dbg("Using dual workslot mode");
1722 dev->max_event_ports = dev->max_event_ports / 2;
1724 otx2_sso_dbg("Using single workslot mode");
1727 otx2_sso_pf_func_set(dev->pf_func);
1728 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1729 event_dev->data->name, dev->max_event_queues,
1730 dev->max_event_ports);
1731 if (dev->selftest) {
1732 event_dev->dev->driver = &pci_sso.driver;
1733 event_dev->dev_ops->dev_selftest();
1736 otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
1743 otx2_dev_fini(pci_dev, dev);
1749 otx2_sso_fini(struct rte_eventdev *event_dev)
1751 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1752 struct rte_pci_device *pci_dev;
1754 /* For secondary processes, nothing to be done */
1755 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1758 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1760 if (!dev->drv_inited)
1763 dev->drv_inited = false;
1767 if (otx2_npa_lf_active(dev)) {
1768 otx2_info("Common resource in use by other devices");
1773 otx2_dev_fini(pci_dev, dev);
1778 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1779 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1780 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1781 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
1782 OTX2_SSO_SINGLE_WS "=1"
1783 OTX2_SSO_GGRP_QOS "=<string>"
1784 OTX2_SSO_SELFTEST "=1");