1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <rte_eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev_stats.h"
16 #include "otx2_evdev.h"
20 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
22 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
23 uint8_t nb_ports = dev->nb_event_ports;
24 struct otx2_mbox *mbox = dev->mbox;
25 struct msix_offset_rsp *msix_rsp;
28 /* Get SSO and SSOW MSIX vector offsets */
29 otx2_mbox_alloc_msg_msix_offset(mbox);
30 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
32 for (i = 0; i < nb_ports; i++)
33 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
35 for (i = 0; i < dev->nb_event_queues; i++)
36 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
42 otx2_sso_info_get(struct rte_eventdev *event_dev,
43 struct rte_event_dev_info *dev_info)
45 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
47 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
48 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
49 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
50 dev_info->max_event_queues = dev->max_event_queues;
51 dev_info->max_event_queue_flows = (1ULL << 20);
52 dev_info->max_event_queue_priority_levels = 8;
53 dev_info->max_event_priority_levels = 1;
54 dev_info->max_event_ports = dev->max_event_ports;
55 dev_info->max_event_port_dequeue_depth = 1;
56 dev_info->max_event_port_enqueue_depth = 1;
57 dev_info->max_num_events = dev->max_num_events;
58 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
59 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
60 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
61 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
62 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
63 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
67 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
69 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
73 val |= 0ULL << 12; /* SET 0 */
74 val |= 0x8000800080000000; /* Dont modify rest of the masks */
75 val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */
77 otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
81 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
82 const uint8_t queues[], const uint8_t priorities[],
88 RTE_SET_USED(event_dev);
89 RTE_SET_USED(priorities);
90 for (link = 0; link < nb_links; link++) {
91 struct otx2_ssogws *ws = port;
94 sso_port_link_modify(ws, queues[link], true);
96 sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
102 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
103 uint8_t queues[], uint16_t nb_unlinks)
108 RTE_SET_USED(event_dev);
109 for (unlink = 0; unlink < nb_unlinks; unlink++) {
110 struct otx2_ssogws *ws = port;
113 sso_port_link_modify(ws, queues[unlink], false);
115 sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
117 return (int)nb_unlinks;
121 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
122 uint16_t nb_lf, uint8_t attach)
125 struct rsrc_attach_req *req;
127 req = otx2_mbox_alloc_msg_attach_resources(mbox);
139 if (otx2_mbox_process(mbox) < 0)
142 struct rsrc_detach_req *req;
144 req = otx2_mbox_alloc_msg_detach_resources(mbox);
156 if (otx2_mbox_process(mbox) < 0)
164 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
165 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
174 struct sso_lf_alloc_req *req_ggrp;
175 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
176 req_ggrp->hwgrps = nb_lf;
181 struct ssow_lf_alloc_req *req_hws;
182 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
183 req_hws->hws = nb_lf;
193 struct sso_lf_free_req *req_ggrp;
194 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
195 req_ggrp->hwgrps = nb_lf;
200 struct ssow_lf_free_req *req_hws;
201 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
202 req_hws->hws = nb_lf;
210 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
214 if (alloc && type == SSO_LF_GGRP) {
215 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
217 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
218 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
219 dev->iue = rsp_ggrp->in_unit_entries;
226 otx2_sso_port_release(void *port)
232 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
234 RTE_SET_USED(event_dev);
235 RTE_SET_USED(queue_id);
239 sso_clr_links(const struct rte_eventdev *event_dev)
241 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
244 for (i = 0; i < dev->nb_event_ports; i++) {
245 struct otx2_ssogws *ws;
247 ws = event_dev->data->ports[i];
248 for (j = 0; j < dev->nb_event_queues; j++)
249 sso_port_link_modify(ws, j, false);
254 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
256 ws->tag_op = base + SSOW_LF_GWS_TAG;
257 ws->wqp_op = base + SSOW_LF_GWS_WQP;
258 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
259 ws->swtp_op = base + SSOW_LF_GWS_SWTP;
260 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
261 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
265 sso_configure_ports(const struct rte_eventdev *event_dev)
267 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
268 struct otx2_mbox *mbox = dev->mbox;
272 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
274 nb_lf = dev->nb_event_ports;
275 /* Ask AF to attach required LFs. */
276 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
278 otx2_err("Failed to attach SSO GWS LF");
282 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
283 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
284 otx2_err("Failed to init SSO GWS LF");
288 for (i = 0; i < nb_lf; i++) {
289 struct otx2_ssogws *ws;
292 /* Free memory prior to re-allocation if needed */
293 if (event_dev->data->ports[i] != NULL) {
294 ws = event_dev->data->ports[i];
299 /* Allocate event port memory */
300 ws = rte_zmalloc_socket("otx2_sso_ws",
301 sizeof(struct otx2_ssogws),
303 event_dev->data->socket_id);
305 otx2_err("Failed to alloc memory for port=%d", i);
311 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
312 sso_set_port_ops(ws, base);
314 event_dev->data->ports[i] = ws;
318 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
319 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
326 sso_configure_queues(const struct rte_eventdev *event_dev)
328 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
329 struct otx2_mbox *mbox = dev->mbox;
333 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
335 nb_lf = dev->nb_event_queues;
336 /* Ask AF to attach required LFs. */
337 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
339 otx2_err("Failed to attach SSO GGRP LF");
343 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
344 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
345 otx2_err("Failed to init SSO GGRP LF");
353 sso_xaq_allocate(struct otx2_sso_evdev *dev)
355 const struct rte_memzone *mz;
356 struct npa_aura_s *aura;
357 static int reconfig_cnt;
358 char pool_name[RTE_MEMZONE_NAMESIZE];
363 rte_mempool_free(dev->xaq_pool);
366 * Allocate memory for Add work backpressure.
368 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
370 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
372 sizeof(struct npa_aura_s),
374 RTE_MEMZONE_IOVA_CONTIG,
377 otx2_err("Failed to allocate mem for fcmem");
381 dev->fc_iova = mz->iova;
382 dev->fc_mem = mz->addr;
384 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
385 memset(aura, 0, sizeof(struct npa_aura_s));
388 aura->fc_addr = dev->fc_iova;
389 aura->fc_hyst_bits = 0; /* Store count on all updates */
391 /* Taken from HRM 14.3.3(4) */
392 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
394 xaq_cnt += dev->xae_cnt / dev->xae_waes;
396 xaq_cnt += (dev->iue / dev->xae_waes) +
397 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
399 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
400 /* Setup XAQ based on number of nb queues. */
401 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
402 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
403 xaq_cnt, dev->xaq_buf_size, 0, 0,
406 if (dev->xaq_pool == NULL) {
407 otx2_err("Unable to create empty mempool.");
408 rte_memzone_free(mz);
412 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
413 rte_mbuf_platform_mempool_ops(), aura);
415 otx2_err("Unable to set xaqpool ops.");
419 rc = rte_mempool_populate_default(dev->xaq_pool);
421 otx2_err("Unable to set populate xaqpool.");
425 /* When SW does addwork (enqueue) check if there is space in XAQ by
426 * comparing fc_addr above against the xaq_lmt calculated below.
427 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
428 * to request XAQ to cache them even before enqueue is called.
430 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
431 dev->nb_event_queues);
432 dev->nb_xaq_cfg = xaq_cnt;
436 rte_mempool_free(dev->xaq_pool);
437 rte_memzone_free(mz);
442 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
444 struct otx2_mbox *mbox = dev->mbox;
445 struct sso_hw_setconfig *req;
447 otx2_sso_dbg("Configuring XAQ for GGRPs");
448 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
449 req->npa_pf_func = otx2_npa_pf_func_get();
450 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
451 req->hwgrps = dev->nb_event_queues;
453 return otx2_mbox_process(mbox);
457 sso_lf_teardown(struct otx2_sso_evdev *dev,
458 enum otx2_sso_lf_type lf_type)
464 nb_lf = dev->nb_event_queues;
467 nb_lf = dev->nb_event_ports;
473 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
474 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
478 otx2_sso_configure(const struct rte_eventdev *event_dev)
480 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
481 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
486 deq_tmo_ns = conf->dequeue_timeout_ns;
489 deq_tmo_ns = dev->min_dequeue_timeout_ns;
491 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
492 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
493 otx2_err("Unsupported dequeue timeout requested");
497 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
498 dev->is_timeout_deq = 1;
500 dev->deq_tmo_ns = deq_tmo_ns;
502 if (conf->nb_event_ports > dev->max_event_ports ||
503 conf->nb_event_queues > dev->max_event_queues) {
504 otx2_err("Unsupported event queues/ports requested");
508 if (conf->nb_event_port_dequeue_depth > 1) {
509 otx2_err("Unsupported event port deq depth requested");
513 if (conf->nb_event_port_enqueue_depth > 1) {
514 otx2_err("Unsupported event port enq depth requested");
519 sso_unregister_irqs(event_dev);
521 if (dev->nb_event_queues) {
522 /* Finit any previous queues. */
523 sso_lf_teardown(dev, SSO_LF_GGRP);
525 if (dev->nb_event_ports) {
526 /* Finit any previous ports. */
527 sso_lf_teardown(dev, SSO_LF_GWS);
530 dev->nb_event_queues = conf->nb_event_queues;
531 dev->nb_event_ports = conf->nb_event_ports;
533 if (sso_configure_ports(event_dev)) {
534 otx2_err("Failed to configure event ports");
538 if (sso_configure_queues(event_dev) < 0) {
539 otx2_err("Failed to configure event queues");
544 if (sso_xaq_allocate(dev) < 0) {
546 goto teardown_hwggrp;
549 /* Clear any prior port-queue mapping. */
550 sso_clr_links(event_dev);
551 rc = sso_ggrp_alloc_xaq(dev);
553 otx2_err("Failed to alloc xaq to ggrp %d", rc);
554 goto teardown_hwggrp;
557 rc = sso_get_msix_offsets(event_dev);
559 otx2_err("Failed to get msix offsets %d", rc);
560 goto teardown_hwggrp;
563 rc = sso_register_irqs(event_dev);
565 otx2_err("Failed to register irq %d", rc);
566 goto teardown_hwggrp;
574 sso_lf_teardown(dev, SSO_LF_GGRP);
576 sso_lf_teardown(dev, SSO_LF_GWS);
577 dev->nb_event_queues = 0;
578 dev->nb_event_ports = 0;
584 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
585 struct rte_event_queue_conf *queue_conf)
587 RTE_SET_USED(event_dev);
588 RTE_SET_USED(queue_id);
590 queue_conf->nb_atomic_flows = (1ULL << 20);
591 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
592 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
593 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
597 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
598 const struct rte_event_queue_conf *queue_conf)
600 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
601 struct otx2_mbox *mbox = dev->mbox;
602 struct sso_grp_priority *req;
605 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
607 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
610 req->affinity = 0xFF;
611 /* Normalize <0-255> to <0-7> */
612 req->priority = queue_conf->priority / 32;
614 rc = otx2_mbox_process(mbox);
616 otx2_err("Failed to set priority queue=%d", queue_id);
624 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
625 struct rte_event_port_conf *port_conf)
627 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
629 RTE_SET_USED(port_id);
630 port_conf->new_event_threshold = dev->max_num_events;
631 port_conf->dequeue_depth = 1;
632 port_conf->enqueue_depth = 1;
636 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
637 const struct rte_event_port_conf *port_conf)
639 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
640 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
644 sso_func_trace("Port=%d", port_id);
645 RTE_SET_USED(port_conf);
647 if (event_dev->data->ports[port_id] == NULL) {
648 otx2_err("Invalid port Id %d", port_id);
652 for (q = 0; q < dev->nb_event_queues; q++) {
653 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
654 if (grps_base[q] == 0) {
655 otx2_err("Failed to get grp[%d] base addr", q);
660 /* Set get_work timeout for HWS */
661 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
663 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
664 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
666 rte_memcpy(ws->grps_base, grps_base,
667 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
668 ws->fc_mem = dev->fc_mem;
669 ws->xaq_lmt = dev->xaq_lmt;
670 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
672 otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
678 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
681 RTE_SET_USED(event_dev);
682 *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
688 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
690 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
692 fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base);
693 fprintf(f, "SSOW_LF_GWS_LINKS 0x%" PRIx64 "\n",
694 otx2_read64(base + SSOW_LF_GWS_LINKS));
695 fprintf(f, "SSOW_LF_GWS_PENDWQP 0x%" PRIx64 "\n",
696 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
697 fprintf(f, "SSOW_LF_GWS_PENDSTATE 0x%" PRIx64 "\n",
698 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
699 fprintf(f, "SSOW_LF_GWS_NW_TIM 0x%" PRIx64 "\n",
700 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
701 fprintf(f, "SSOW_LF_GWS_TAG 0x%" PRIx64 "\n",
702 otx2_read64(base + SSOW_LF_GWS_TAG));
703 fprintf(f, "SSOW_LF_GWS_WQP 0x%" PRIx64 "\n",
704 otx2_read64(base + SSOW_LF_GWS_TAG));
705 fprintf(f, "SSOW_LF_GWS_SWTP 0x%" PRIx64 "\n",
706 otx2_read64(base + SSOW_LF_GWS_SWTP));
707 fprintf(f, "SSOW_LF_GWS_PENDTAG 0x%" PRIx64 "\n",
708 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
712 ssoggrp_dump(uintptr_t base, FILE *f)
714 fprintf(f, "SSO_LF_GGRP Base addr 0x%" PRIx64 "\n", (uint64_t)base);
715 fprintf(f, "SSO_LF_GGRP_QCTL 0x%" PRIx64 "\n",
716 otx2_read64(base + SSO_LF_GGRP_QCTL));
717 fprintf(f, "SSO_LF_GGRP_XAQ_CNT 0x%" PRIx64 "\n",
718 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
719 fprintf(f, "SSO_LF_GGRP_INT_THR 0x%" PRIx64 "\n",
720 otx2_read64(base + SSO_LF_GGRP_INT_THR));
721 fprintf(f, "SSO_LF_GGRP_INT_CNT 0x%" PRIX64 "\n",
722 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
723 fprintf(f, "SSO_LF_GGRP_AQ_CNT 0x%" PRIX64 "\n",
724 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
725 fprintf(f, "SSO_LF_GGRP_AQ_THR 0x%" PRIX64 "\n",
726 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
727 fprintf(f, "SSO_LF_GGRP_MISC_CNT 0x%" PRIx64 "\n",
728 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
732 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
734 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
738 /* Dump SSOW registers */
739 for (port = 0; port < dev->nb_event_ports; port++) {
740 fprintf(f, "[%s]SSO single workslot[%d] dump\n",
742 ssogws_dump(event_dev->data->ports[port], f);
745 /* Dump SSO registers */
746 for (queue = 0; queue < dev->nb_event_queues; queue++) {
747 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
748 struct otx2_ssogws *ws = event_dev->data->ports[0];
749 ssoggrp_dump(ws->grps_base[queue], f);
753 /* Initialize and register event driver with DPDK Application */
754 static struct rte_eventdev_ops otx2_sso_ops = {
755 .dev_infos_get = otx2_sso_info_get,
756 .dev_configure = otx2_sso_configure,
757 .queue_def_conf = otx2_sso_queue_def_conf,
758 .queue_setup = otx2_sso_queue_setup,
759 .queue_release = otx2_sso_queue_release,
760 .port_def_conf = otx2_sso_port_def_conf,
761 .port_setup = otx2_sso_port_setup,
762 .port_release = otx2_sso_port_release,
763 .port_link = otx2_sso_port_link,
764 .port_unlink = otx2_sso_port_unlink,
765 .timeout_ticks = otx2_sso_timeout_ticks,
767 .xstats_get = otx2_sso_xstats_get,
768 .xstats_reset = otx2_sso_xstats_reset,
769 .xstats_get_names = otx2_sso_xstats_get_names,
771 .dump = otx2_sso_dump,
774 #define OTX2_SSO_XAE_CNT "xae_cnt"
777 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
779 struct rte_kvargs *kvlist;
783 kvlist = rte_kvargs_parse(devargs->args, NULL);
787 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
790 rte_kvargs_free(kvlist);
794 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
796 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
797 sizeof(struct otx2_sso_evdev),
802 otx2_sso_remove(struct rte_pci_device *pci_dev)
804 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
807 static const struct rte_pci_id pci_sso_map[] = {
809 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
810 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
817 static struct rte_pci_driver pci_sso = {
818 .id_table = pci_sso_map,
819 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
820 .probe = otx2_sso_probe,
821 .remove = otx2_sso_remove,
825 otx2_sso_init(struct rte_eventdev *event_dev)
827 struct free_rsrcs_rsp *rsrc_cnt;
828 struct rte_pci_device *pci_dev;
829 struct otx2_sso_evdev *dev;
832 event_dev->dev_ops = &otx2_sso_ops;
833 /* For secondary processes, the primary has done all the work */
834 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
837 dev = sso_pmd_priv(event_dev);
839 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
841 /* Initialize the base otx2_dev object */
842 rc = otx2_dev_init(pci_dev, dev);
844 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
848 /* Get SSO and SSOW MSIX rsrc cnt */
849 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
850 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
852 otx2_err("Unable to get free rsrc count");
853 goto otx2_dev_uninit;
855 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
856 rsrc_cnt->ssow, rsrc_cnt->npa);
858 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
859 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
860 /* Grab the NPA LF if required */
861 rc = otx2_npa_lf_init(pci_dev, dev);
863 otx2_err("Unable to init NPA lf. It might not be provisioned");
864 goto otx2_dev_uninit;
867 dev->drv_inited = true;
868 dev->is_timeout_deq = 0;
869 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
870 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
871 dev->max_num_events = -1;
872 dev->nb_event_queues = 0;
873 dev->nb_event_ports = 0;
875 if (!dev->max_event_ports || !dev->max_event_queues) {
876 otx2_err("Not enough eventdev resource queues=%d ports=%d",
877 dev->max_event_queues, dev->max_event_ports);
879 goto otx2_npa_lf_uninit;
882 sso_parse_devargs(dev, pci_dev->device.devargs);
884 otx2_sso_pf_func_set(dev->pf_func);
885 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
886 event_dev->data->name, dev->max_event_queues,
887 dev->max_event_ports);
895 otx2_dev_fini(pci_dev, dev);
901 otx2_sso_fini(struct rte_eventdev *event_dev)
903 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
904 struct rte_pci_device *pci_dev;
906 /* For secondary processes, nothing to be done */
907 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
910 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
912 if (!dev->drv_inited)
915 dev->drv_inited = false;
919 if (otx2_npa_lf_active(dev)) {
920 otx2_info("Common resource in use by other devices");
924 otx2_dev_fini(pci_dev, dev);
929 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
930 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
931 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
932 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>");