1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <rte_eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev.h"
19 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
21 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
22 uint8_t nb_ports = dev->nb_event_ports;
23 struct otx2_mbox *mbox = dev->mbox;
24 struct msix_offset_rsp *msix_rsp;
27 /* Get SSO and SSOW MSIX vector offsets */
28 otx2_mbox_alloc_msg_msix_offset(mbox);
29 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
31 for (i = 0; i < nb_ports; i++)
32 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
34 for (i = 0; i < dev->nb_event_queues; i++)
35 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
41 otx2_sso_info_get(struct rte_eventdev *event_dev,
42 struct rte_event_dev_info *dev_info)
44 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
46 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
47 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
48 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
49 dev_info->max_event_queues = dev->max_event_queues;
50 dev_info->max_event_queue_flows = (1ULL << 20);
51 dev_info->max_event_queue_priority_levels = 8;
52 dev_info->max_event_priority_levels = 1;
53 dev_info->max_event_ports = dev->max_event_ports;
54 dev_info->max_event_port_dequeue_depth = 1;
55 dev_info->max_event_port_enqueue_depth = 1;
56 dev_info->max_num_events = dev->max_num_events;
57 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
58 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
59 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
60 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
61 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
62 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
66 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
68 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
72 val |= 0ULL << 12; /* SET 0 */
73 val |= 0x8000800080000000; /* Dont modify rest of the masks */
74 val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */
76 otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
80 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
81 const uint8_t queues[], const uint8_t priorities[],
87 RTE_SET_USED(event_dev);
88 RTE_SET_USED(priorities);
89 for (link = 0; link < nb_links; link++) {
90 struct otx2_ssogws *ws = port;
93 sso_port_link_modify(ws, queues[link], true);
95 sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
101 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
102 uint8_t queues[], uint16_t nb_unlinks)
107 RTE_SET_USED(event_dev);
108 for (unlink = 0; unlink < nb_unlinks; unlink++) {
109 struct otx2_ssogws *ws = port;
112 sso_port_link_modify(ws, queues[unlink], false);
114 sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
116 return (int)nb_unlinks;
120 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
121 uint16_t nb_lf, uint8_t attach)
124 struct rsrc_attach_req *req;
126 req = otx2_mbox_alloc_msg_attach_resources(mbox);
138 if (otx2_mbox_process(mbox) < 0)
141 struct rsrc_detach_req *req;
143 req = otx2_mbox_alloc_msg_detach_resources(mbox);
155 if (otx2_mbox_process(mbox) < 0)
163 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
164 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
173 struct sso_lf_alloc_req *req_ggrp;
174 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
175 req_ggrp->hwgrps = nb_lf;
180 struct ssow_lf_alloc_req *req_hws;
181 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
182 req_hws->hws = nb_lf;
192 struct sso_lf_free_req *req_ggrp;
193 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
194 req_ggrp->hwgrps = nb_lf;
199 struct ssow_lf_free_req *req_hws;
200 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
201 req_hws->hws = nb_lf;
209 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
213 if (alloc && type == SSO_LF_GGRP) {
214 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
216 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
217 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
218 dev->iue = rsp_ggrp->in_unit_entries;
225 otx2_sso_port_release(void *port)
231 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
233 RTE_SET_USED(event_dev);
234 RTE_SET_USED(queue_id);
238 sso_clr_links(const struct rte_eventdev *event_dev)
240 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
243 for (i = 0; i < dev->nb_event_ports; i++) {
244 struct otx2_ssogws *ws;
246 ws = event_dev->data->ports[i];
247 for (j = 0; j < dev->nb_event_queues; j++)
248 sso_port_link_modify(ws, j, false);
253 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
255 ws->tag_op = base + SSOW_LF_GWS_TAG;
256 ws->wqp_op = base + SSOW_LF_GWS_WQP;
257 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
258 ws->swtp_op = base + SSOW_LF_GWS_SWTP;
259 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
260 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
264 sso_configure_ports(const struct rte_eventdev *event_dev)
266 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
267 struct otx2_mbox *mbox = dev->mbox;
271 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
273 nb_lf = dev->nb_event_ports;
274 /* Ask AF to attach required LFs. */
275 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
277 otx2_err("Failed to attach SSO GWS LF");
281 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
282 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
283 otx2_err("Failed to init SSO GWS LF");
287 for (i = 0; i < nb_lf; i++) {
288 struct otx2_ssogws *ws;
291 /* Free memory prior to re-allocation if needed */
292 if (event_dev->data->ports[i] != NULL) {
293 ws = event_dev->data->ports[i];
298 /* Allocate event port memory */
299 ws = rte_zmalloc_socket("otx2_sso_ws",
300 sizeof(struct otx2_ssogws),
302 event_dev->data->socket_id);
304 otx2_err("Failed to alloc memory for port=%d", i);
310 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
311 sso_set_port_ops(ws, base);
313 event_dev->data->ports[i] = ws;
317 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
318 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
325 sso_configure_queues(const struct rte_eventdev *event_dev)
327 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
328 struct otx2_mbox *mbox = dev->mbox;
332 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
334 nb_lf = dev->nb_event_queues;
335 /* Ask AF to attach required LFs. */
336 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
338 otx2_err("Failed to attach SSO GGRP LF");
342 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
343 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
344 otx2_err("Failed to init SSO GGRP LF");
352 sso_xaq_allocate(struct otx2_sso_evdev *dev)
354 const struct rte_memzone *mz;
355 struct npa_aura_s *aura;
356 static int reconfig_cnt;
357 char pool_name[RTE_MEMZONE_NAMESIZE];
362 rte_mempool_free(dev->xaq_pool);
365 * Allocate memory for Add work backpressure.
367 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
369 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
371 sizeof(struct npa_aura_s),
373 RTE_MEMZONE_IOVA_CONTIG,
376 otx2_err("Failed to allocate mem for fcmem");
380 dev->fc_iova = mz->iova;
381 dev->fc_mem = mz->addr;
383 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
384 memset(aura, 0, sizeof(struct npa_aura_s));
387 aura->fc_addr = dev->fc_iova;
388 aura->fc_hyst_bits = 0; /* Store count on all updates */
390 /* Taken from HRM 14.3.3(4) */
391 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
393 xaq_cnt += dev->xae_cnt / dev->xae_waes;
395 xaq_cnt += (dev->iue / dev->xae_waes) +
396 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
398 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
399 /* Setup XAQ based on number of nb queues. */
400 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
401 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
402 xaq_cnt, dev->xaq_buf_size, 0, 0,
405 if (dev->xaq_pool == NULL) {
406 otx2_err("Unable to create empty mempool.");
407 rte_memzone_free(mz);
411 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
412 rte_mbuf_platform_mempool_ops(), aura);
414 otx2_err("Unable to set xaqpool ops.");
418 rc = rte_mempool_populate_default(dev->xaq_pool);
420 otx2_err("Unable to set populate xaqpool.");
424 /* When SW does addwork (enqueue) check if there is space in XAQ by
425 * comparing fc_addr above against the xaq_lmt calculated below.
426 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
427 * to request XAQ to cache them even before enqueue is called.
429 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
430 dev->nb_event_queues);
431 dev->nb_xaq_cfg = xaq_cnt;
435 rte_mempool_free(dev->xaq_pool);
436 rte_memzone_free(mz);
441 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
443 struct otx2_mbox *mbox = dev->mbox;
444 struct sso_hw_setconfig *req;
446 otx2_sso_dbg("Configuring XAQ for GGRPs");
447 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
448 req->npa_pf_func = otx2_npa_pf_func_get();
449 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
450 req->hwgrps = dev->nb_event_queues;
452 return otx2_mbox_process(mbox);
456 sso_lf_teardown(struct otx2_sso_evdev *dev,
457 enum otx2_sso_lf_type lf_type)
463 nb_lf = dev->nb_event_queues;
466 nb_lf = dev->nb_event_ports;
472 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
473 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
477 otx2_sso_configure(const struct rte_eventdev *event_dev)
479 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
480 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
485 deq_tmo_ns = conf->dequeue_timeout_ns;
488 deq_tmo_ns = dev->min_dequeue_timeout_ns;
490 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
491 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
492 otx2_err("Unsupported dequeue timeout requested");
496 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
497 dev->is_timeout_deq = 1;
499 dev->deq_tmo_ns = deq_tmo_ns;
501 if (conf->nb_event_ports > dev->max_event_ports ||
502 conf->nb_event_queues > dev->max_event_queues) {
503 otx2_err("Unsupported event queues/ports requested");
507 if (conf->nb_event_port_dequeue_depth > 1) {
508 otx2_err("Unsupported event port deq depth requested");
512 if (conf->nb_event_port_enqueue_depth > 1) {
513 otx2_err("Unsupported event port enq depth requested");
518 sso_unregister_irqs(event_dev);
520 if (dev->nb_event_queues) {
521 /* Finit any previous queues. */
522 sso_lf_teardown(dev, SSO_LF_GGRP);
524 if (dev->nb_event_ports) {
525 /* Finit any previous ports. */
526 sso_lf_teardown(dev, SSO_LF_GWS);
529 dev->nb_event_queues = conf->nb_event_queues;
530 dev->nb_event_ports = conf->nb_event_ports;
532 if (sso_configure_ports(event_dev)) {
533 otx2_err("Failed to configure event ports");
537 if (sso_configure_queues(event_dev) < 0) {
538 otx2_err("Failed to configure event queues");
543 if (sso_xaq_allocate(dev) < 0) {
545 goto teardown_hwggrp;
548 /* Clear any prior port-queue mapping. */
549 sso_clr_links(event_dev);
550 rc = sso_ggrp_alloc_xaq(dev);
552 otx2_err("Failed to alloc xaq to ggrp %d", rc);
553 goto teardown_hwggrp;
556 rc = sso_get_msix_offsets(event_dev);
558 otx2_err("Failed to get msix offsets %d", rc);
559 goto teardown_hwggrp;
562 rc = sso_register_irqs(event_dev);
564 otx2_err("Failed to register irq %d", rc);
565 goto teardown_hwggrp;
573 sso_lf_teardown(dev, SSO_LF_GGRP);
575 sso_lf_teardown(dev, SSO_LF_GWS);
576 dev->nb_event_queues = 0;
577 dev->nb_event_ports = 0;
583 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
584 struct rte_event_queue_conf *queue_conf)
586 RTE_SET_USED(event_dev);
587 RTE_SET_USED(queue_id);
589 queue_conf->nb_atomic_flows = (1ULL << 20);
590 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
591 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
592 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
596 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
597 const struct rte_event_queue_conf *queue_conf)
599 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
600 struct otx2_mbox *mbox = dev->mbox;
601 struct sso_grp_priority *req;
604 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
606 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
609 req->affinity = 0xFF;
610 /* Normalize <0-255> to <0-7> */
611 req->priority = queue_conf->priority / 32;
613 rc = otx2_mbox_process(mbox);
615 otx2_err("Failed to set priority queue=%d", queue_id);
623 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
624 struct rte_event_port_conf *port_conf)
626 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
628 RTE_SET_USED(port_id);
629 port_conf->new_event_threshold = dev->max_num_events;
630 port_conf->dequeue_depth = 1;
631 port_conf->enqueue_depth = 1;
635 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
636 const struct rte_event_port_conf *port_conf)
638 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
639 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
643 sso_func_trace("Port=%d", port_id);
644 RTE_SET_USED(port_conf);
646 if (event_dev->data->ports[port_id] == NULL) {
647 otx2_err("Invalid port Id %d", port_id);
651 for (q = 0; q < dev->nb_event_queues; q++) {
652 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
653 if (grps_base[q] == 0) {
654 otx2_err("Failed to get grp[%d] base addr", q);
659 /* Set get_work timeout for HWS */
660 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
662 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
663 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
665 rte_memcpy(ws->grps_base, grps_base,
666 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
667 ws->fc_mem = dev->fc_mem;
668 ws->xaq_lmt = dev->xaq_lmt;
669 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
671 otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
677 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
680 RTE_SET_USED(event_dev);
681 *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
687 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
689 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
691 fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base);
692 fprintf(f, "SSOW_LF_GWS_LINKS 0x%" PRIx64 "\n",
693 otx2_read64(base + SSOW_LF_GWS_LINKS));
694 fprintf(f, "SSOW_LF_GWS_PENDWQP 0x%" PRIx64 "\n",
695 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
696 fprintf(f, "SSOW_LF_GWS_PENDSTATE 0x%" PRIx64 "\n",
697 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
698 fprintf(f, "SSOW_LF_GWS_NW_TIM 0x%" PRIx64 "\n",
699 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
700 fprintf(f, "SSOW_LF_GWS_TAG 0x%" PRIx64 "\n",
701 otx2_read64(base + SSOW_LF_GWS_TAG));
702 fprintf(f, "SSOW_LF_GWS_WQP 0x%" PRIx64 "\n",
703 otx2_read64(base + SSOW_LF_GWS_TAG));
704 fprintf(f, "SSOW_LF_GWS_SWTP 0x%" PRIx64 "\n",
705 otx2_read64(base + SSOW_LF_GWS_SWTP));
706 fprintf(f, "SSOW_LF_GWS_PENDTAG 0x%" PRIx64 "\n",
707 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
711 ssoggrp_dump(uintptr_t base, FILE *f)
713 fprintf(f, "SSO_LF_GGRP Base addr 0x%" PRIx64 "\n", (uint64_t)base);
714 fprintf(f, "SSO_LF_GGRP_QCTL 0x%" PRIx64 "\n",
715 otx2_read64(base + SSO_LF_GGRP_QCTL));
716 fprintf(f, "SSO_LF_GGRP_XAQ_CNT 0x%" PRIx64 "\n",
717 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
718 fprintf(f, "SSO_LF_GGRP_INT_THR 0x%" PRIx64 "\n",
719 otx2_read64(base + SSO_LF_GGRP_INT_THR));
720 fprintf(f, "SSO_LF_GGRP_INT_CNT 0x%" PRIX64 "\n",
721 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
722 fprintf(f, "SSO_LF_GGRP_AQ_CNT 0x%" PRIX64 "\n",
723 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
724 fprintf(f, "SSO_LF_GGRP_AQ_THR 0x%" PRIX64 "\n",
725 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
726 fprintf(f, "SSO_LF_GGRP_MISC_CNT 0x%" PRIx64 "\n",
727 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
731 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
733 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
737 /* Dump SSOW registers */
738 for (port = 0; port < dev->nb_event_ports; port++) {
739 fprintf(f, "[%s]SSO single workslot[%d] dump\n",
741 ssogws_dump(event_dev->data->ports[port], f);
744 /* Dump SSO registers */
745 for (queue = 0; queue < dev->nb_event_queues; queue++) {
746 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
747 struct otx2_ssogws *ws = event_dev->data->ports[0];
748 ssoggrp_dump(ws->grps_base[queue], f);
752 /* Initialize and register event driver with DPDK Application */
753 static struct rte_eventdev_ops otx2_sso_ops = {
754 .dev_infos_get = otx2_sso_info_get,
755 .dev_configure = otx2_sso_configure,
756 .queue_def_conf = otx2_sso_queue_def_conf,
757 .queue_setup = otx2_sso_queue_setup,
758 .queue_release = otx2_sso_queue_release,
759 .port_def_conf = otx2_sso_port_def_conf,
760 .port_setup = otx2_sso_port_setup,
761 .port_release = otx2_sso_port_release,
762 .port_link = otx2_sso_port_link,
763 .port_unlink = otx2_sso_port_unlink,
764 .timeout_ticks = otx2_sso_timeout_ticks,
766 .dump = otx2_sso_dump,
769 #define OTX2_SSO_XAE_CNT "xae_cnt"
772 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
774 struct rte_kvargs *kvlist;
778 kvlist = rte_kvargs_parse(devargs->args, NULL);
782 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
785 rte_kvargs_free(kvlist);
789 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
791 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
792 sizeof(struct otx2_sso_evdev),
797 otx2_sso_remove(struct rte_pci_device *pci_dev)
799 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
802 static const struct rte_pci_id pci_sso_map[] = {
804 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
805 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
812 static struct rte_pci_driver pci_sso = {
813 .id_table = pci_sso_map,
814 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
815 .probe = otx2_sso_probe,
816 .remove = otx2_sso_remove,
820 otx2_sso_init(struct rte_eventdev *event_dev)
822 struct free_rsrcs_rsp *rsrc_cnt;
823 struct rte_pci_device *pci_dev;
824 struct otx2_sso_evdev *dev;
827 event_dev->dev_ops = &otx2_sso_ops;
828 /* For secondary processes, the primary has done all the work */
829 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
832 dev = sso_pmd_priv(event_dev);
834 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
836 /* Initialize the base otx2_dev object */
837 rc = otx2_dev_init(pci_dev, dev);
839 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
843 /* Get SSO and SSOW MSIX rsrc cnt */
844 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
845 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
847 otx2_err("Unable to get free rsrc count");
848 goto otx2_dev_uninit;
850 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
851 rsrc_cnt->ssow, rsrc_cnt->npa);
853 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
854 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
855 /* Grab the NPA LF if required */
856 rc = otx2_npa_lf_init(pci_dev, dev);
858 otx2_err("Unable to init NPA lf. It might not be provisioned");
859 goto otx2_dev_uninit;
862 dev->drv_inited = true;
863 dev->is_timeout_deq = 0;
864 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
865 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
866 dev->max_num_events = -1;
867 dev->nb_event_queues = 0;
868 dev->nb_event_ports = 0;
870 if (!dev->max_event_ports || !dev->max_event_queues) {
871 otx2_err("Not enough eventdev resource queues=%d ports=%d",
872 dev->max_event_queues, dev->max_event_ports);
874 goto otx2_npa_lf_uninit;
877 sso_parse_devargs(dev, pci_dev->device.devargs);
879 otx2_sso_pf_func_set(dev->pf_func);
880 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
881 event_dev->data->name, dev->max_event_queues,
882 dev->max_event_ports);
890 otx2_dev_fini(pci_dev, dev);
896 otx2_sso_fini(struct rte_eventdev *event_dev)
898 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
899 struct rte_pci_device *pci_dev;
901 /* For secondary processes, nothing to be done */
902 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
905 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
907 if (!dev->drv_inited)
910 dev->drv_inited = false;
914 if (otx2_npa_lf_active(dev)) {
915 otx2_info("Common resource in use by other devices");
919 otx2_dev_fini(pci_dev, dev);
924 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
925 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
926 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
927 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>");