1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev_stats.h"
16 #include "otx2_evdev.h"
18 #include "otx2_tim_evdev.h"
21 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
23 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
24 uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
25 struct otx2_mbox *mbox = dev->mbox;
26 struct msix_offset_rsp *msix_rsp;
29 /* Get SSO and SSOW MSIX vector offsets */
30 otx2_mbox_alloc_msg_msix_offset(mbox);
31 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
33 for (i = 0; i < nb_ports; i++)
34 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
36 for (i = 0; i < dev->nb_event_queues; i++)
37 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
43 sso_fastpath_fns_set(struct rte_eventdev *event_dev)
45 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
47 const event_dequeue_t ssogws_deq[2][2][2][2][2][2][2] = {
48 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
49 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_ ##name,
50 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
54 const event_dequeue_burst_t ssogws_deq_burst[2][2][2][2][2][2][2] = {
55 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
56 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_burst_ ##name,
57 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
61 const event_dequeue_t ssogws_deq_timeout[2][2][2][2][2][2][2] = {
62 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
63 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_timeout_ ##name,
64 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
68 const event_dequeue_burst_t
69 ssogws_deq_timeout_burst[2][2][2][2][2][2][2] = {
70 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
71 [f6][f5][f4][f3][f2][f1][f0] = \
72 otx2_ssogws_deq_timeout_burst_ ##name,
73 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
77 const event_dequeue_t ssogws_deq_seg[2][2][2][2][2][2][2] = {
78 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
79 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_ ##name,
80 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
84 const event_dequeue_burst_t
85 ssogws_deq_seg_burst[2][2][2][2][2][2][2] = {
86 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
87 [f6][f5][f4][f3][f2][f1][f0] = \
88 otx2_ssogws_deq_seg_burst_ ##name,
89 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
93 const event_dequeue_t ssogws_deq_seg_timeout[2][2][2][2][2][2][2] = {
94 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
95 [f6][f5][f4][f3][f2][f1][f0] = \
96 otx2_ssogws_deq_seg_timeout_ ##name,
97 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
101 const event_dequeue_burst_t
102 ssogws_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
103 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
104 [f6][f5][f4][f3][f2][f1][f0] = \
105 otx2_ssogws_deq_seg_timeout_burst_ ##name,
106 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
112 const event_dequeue_t ssogws_dual_deq[2][2][2][2][2][2][2] = {
113 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
114 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_ ##name,
115 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
119 const event_dequeue_burst_t
120 ssogws_dual_deq_burst[2][2][2][2][2][2][2] = {
121 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
122 [f6][f5][f4][f3][f2][f1][f0] = \
123 otx2_ssogws_dual_deq_burst_ ##name,
124 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
128 const event_dequeue_t ssogws_dual_deq_timeout[2][2][2][2][2][2][2] = {
129 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
130 [f6][f5][f4][f3][f2][f1][f0] = \
131 otx2_ssogws_dual_deq_timeout_ ##name,
132 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
136 const event_dequeue_burst_t
137 ssogws_dual_deq_timeout_burst[2][2][2][2][2][2][2] = {
138 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
139 [f6][f5][f4][f3][f2][f1][f0] = \
140 otx2_ssogws_dual_deq_timeout_burst_ ##name,
141 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
145 const event_dequeue_t ssogws_dual_deq_seg[2][2][2][2][2][2][2] = {
146 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
147 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_seg_ ##name,
148 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
152 const event_dequeue_burst_t
153 ssogws_dual_deq_seg_burst[2][2][2][2][2][2][2] = {
154 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
155 [f6][f5][f4][f3][f2][f1][f0] = \
156 otx2_ssogws_dual_deq_seg_burst_ ##name,
157 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
161 const event_dequeue_t
162 ssogws_dual_deq_seg_timeout[2][2][2][2][2][2][2] = {
163 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
164 [f6][f5][f4][f3][f2][f1][f0] = \
165 otx2_ssogws_dual_deq_seg_timeout_ ##name,
166 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
170 const event_dequeue_burst_t
171 ssogws_dual_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
172 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
173 [f6][f5][f4][f3][f2][f1][f0] = \
174 otx2_ssogws_dual_deq_seg_timeout_burst_ ##name,
175 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
180 const event_tx_adapter_enqueue
181 ssogws_tx_adptr_enq[2][2][2][2][2][2][2] = {
182 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
183 [f6][f5][f4][f3][f2][f1][f0] = \
184 otx2_ssogws_tx_adptr_enq_ ## name,
185 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
189 const event_tx_adapter_enqueue
190 ssogws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
191 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
192 [f6][f5][f4][f3][f2][f1][f0] = \
193 otx2_ssogws_tx_adptr_enq_seg_ ## name,
194 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
198 const event_tx_adapter_enqueue
199 ssogws_dual_tx_adptr_enq[2][2][2][2][2][2][2] = {
200 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
201 [f6][f5][f4][f3][f2][f1][f0] = \
202 otx2_ssogws_dual_tx_adptr_enq_ ## name,
203 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
207 const event_tx_adapter_enqueue
208 ssogws_dual_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
209 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
210 [f6][f5][f4][f3][f2][f1][f0] = \
211 otx2_ssogws_dual_tx_adptr_enq_seg_ ## name,
212 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
216 event_dev->enqueue = otx2_ssogws_enq;
217 event_dev->enqueue_burst = otx2_ssogws_enq_burst;
218 event_dev->enqueue_new_burst = otx2_ssogws_enq_new_burst;
219 event_dev->enqueue_forward_burst = otx2_ssogws_enq_fwd_burst;
220 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
221 event_dev->dequeue = ssogws_deq_seg
222 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
223 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
224 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
225 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
226 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
227 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
228 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
229 event_dev->dequeue_burst = ssogws_deq_seg_burst
230 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
231 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
232 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
233 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
234 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
235 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
236 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
237 if (dev->is_timeout_deq) {
238 event_dev->dequeue = ssogws_deq_seg_timeout
239 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
240 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
241 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
242 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
243 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
244 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
245 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
246 event_dev->dequeue_burst =
247 ssogws_deq_seg_timeout_burst
248 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
249 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
250 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
251 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
252 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
253 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
254 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
257 event_dev->dequeue = ssogws_deq
258 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
259 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
260 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
261 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
262 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
263 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
264 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
265 event_dev->dequeue_burst = ssogws_deq_burst
266 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
267 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
268 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
269 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
270 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
271 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
272 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
273 if (dev->is_timeout_deq) {
274 event_dev->dequeue = ssogws_deq_timeout
275 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
276 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
277 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
278 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
279 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
280 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
281 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
282 event_dev->dequeue_burst =
283 ssogws_deq_timeout_burst
284 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
285 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
286 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
287 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
288 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
289 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
290 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
294 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
295 /* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
296 event_dev->txa_enqueue = ssogws_tx_adptr_enq_seg
297 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]
298 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
299 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
300 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
301 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
302 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
303 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
305 event_dev->txa_enqueue = ssogws_tx_adptr_enq
306 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]
307 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
308 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
309 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
310 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
311 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
312 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
316 event_dev->enqueue = otx2_ssogws_dual_enq;
317 event_dev->enqueue_burst = otx2_ssogws_dual_enq_burst;
318 event_dev->enqueue_new_burst =
319 otx2_ssogws_dual_enq_new_burst;
320 event_dev->enqueue_forward_burst =
321 otx2_ssogws_dual_enq_fwd_burst;
323 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
324 event_dev->dequeue = ssogws_dual_deq_seg
325 [!!(dev->rx_offloads &
326 NIX_RX_OFFLOAD_SECURITY_F)]
327 [!!(dev->rx_offloads &
328 NIX_RX_OFFLOAD_TSTAMP_F)]
329 [!!(dev->rx_offloads &
330 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
331 [!!(dev->rx_offloads &
332 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
333 [!!(dev->rx_offloads &
334 NIX_RX_OFFLOAD_CHECKSUM_F)]
335 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
336 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
337 event_dev->dequeue_burst = ssogws_dual_deq_seg_burst
338 [!!(dev->rx_offloads &
339 NIX_RX_OFFLOAD_SECURITY_F)]
340 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
341 [!!(dev->rx_offloads &
342 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
343 [!!(dev->rx_offloads &
344 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
345 [!!(dev->rx_offloads &
346 NIX_RX_OFFLOAD_CHECKSUM_F)]
347 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
348 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
349 if (dev->is_timeout_deq) {
351 ssogws_dual_deq_seg_timeout
352 [!!(dev->rx_offloads &
353 NIX_RX_OFFLOAD_SECURITY_F)]
354 [!!(dev->rx_offloads &
355 NIX_RX_OFFLOAD_TSTAMP_F)]
356 [!!(dev->rx_offloads &
357 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
358 [!!(dev->rx_offloads &
359 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
360 [!!(dev->rx_offloads &
361 NIX_RX_OFFLOAD_CHECKSUM_F)]
362 [!!(dev->rx_offloads &
363 NIX_RX_OFFLOAD_PTYPE_F)]
364 [!!(dev->rx_offloads &
365 NIX_RX_OFFLOAD_RSS_F)];
366 event_dev->dequeue_burst =
367 ssogws_dual_deq_seg_timeout_burst
368 [!!(dev->rx_offloads &
369 NIX_RX_OFFLOAD_SECURITY_F)]
370 [!!(dev->rx_offloads &
371 NIX_RX_OFFLOAD_TSTAMP_F)]
372 [!!(dev->rx_offloads &
373 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
374 [!!(dev->rx_offloads &
375 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
376 [!!(dev->rx_offloads &
377 NIX_RX_OFFLOAD_CHECKSUM_F)]
378 [!!(dev->rx_offloads &
379 NIX_RX_OFFLOAD_PTYPE_F)]
380 [!!(dev->rx_offloads &
381 NIX_RX_OFFLOAD_RSS_F)];
384 event_dev->dequeue = ssogws_dual_deq
385 [!!(dev->rx_offloads &
386 NIX_RX_OFFLOAD_SECURITY_F)]
387 [!!(dev->rx_offloads &
388 NIX_RX_OFFLOAD_TSTAMP_F)]
389 [!!(dev->rx_offloads &
390 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
391 [!!(dev->rx_offloads &
392 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
393 [!!(dev->rx_offloads &
394 NIX_RX_OFFLOAD_CHECKSUM_F)]
395 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
396 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
397 event_dev->dequeue_burst = ssogws_dual_deq_burst
398 [!!(dev->rx_offloads &
399 NIX_RX_OFFLOAD_SECURITY_F)]
400 [!!(dev->rx_offloads &
401 NIX_RX_OFFLOAD_TSTAMP_F)]
402 [!!(dev->rx_offloads &
403 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
404 [!!(dev->rx_offloads &
405 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
406 [!!(dev->rx_offloads &
407 NIX_RX_OFFLOAD_CHECKSUM_F)]
408 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
409 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
410 if (dev->is_timeout_deq) {
412 ssogws_dual_deq_timeout
413 [!!(dev->rx_offloads &
414 NIX_RX_OFFLOAD_SECURITY_F)]
415 [!!(dev->rx_offloads &
416 NIX_RX_OFFLOAD_TSTAMP_F)]
417 [!!(dev->rx_offloads &
418 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
419 [!!(dev->rx_offloads &
420 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
421 [!!(dev->rx_offloads &
422 NIX_RX_OFFLOAD_CHECKSUM_F)]
423 [!!(dev->rx_offloads &
424 NIX_RX_OFFLOAD_PTYPE_F)]
425 [!!(dev->rx_offloads &
426 NIX_RX_OFFLOAD_RSS_F)];
427 event_dev->dequeue_burst =
428 ssogws_dual_deq_timeout_burst
429 [!!(dev->rx_offloads &
430 NIX_RX_OFFLOAD_SECURITY_F)]
431 [!!(dev->rx_offloads &
432 NIX_RX_OFFLOAD_TSTAMP_F)]
433 [!!(dev->rx_offloads &
434 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
435 [!!(dev->rx_offloads &
436 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
437 [!!(dev->rx_offloads &
438 NIX_RX_OFFLOAD_CHECKSUM_F)]
439 [!!(dev->rx_offloads &
440 NIX_RX_OFFLOAD_PTYPE_F)]
441 [!!(dev->rx_offloads &
442 NIX_RX_OFFLOAD_RSS_F)];
446 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
447 /* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
448 event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq_seg
449 [!!(dev->tx_offloads &
450 NIX_TX_OFFLOAD_SECURITY_F)]
451 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
452 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
453 [!!(dev->tx_offloads &
454 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
455 [!!(dev->tx_offloads &
456 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
457 [!!(dev->tx_offloads &
458 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
459 [!!(dev->tx_offloads &
460 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
462 event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq
463 [!!(dev->tx_offloads &
464 NIX_TX_OFFLOAD_SECURITY_F)]
465 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
466 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
467 [!!(dev->tx_offloads &
468 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
469 [!!(dev->tx_offloads &
470 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
471 [!!(dev->tx_offloads &
472 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
473 [!!(dev->tx_offloads &
474 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
478 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
483 otx2_sso_info_get(struct rte_eventdev *event_dev,
484 struct rte_event_dev_info *dev_info)
486 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
488 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
489 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
490 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
491 dev_info->max_event_queues = dev->max_event_queues;
492 dev_info->max_event_queue_flows = (1ULL << 20);
493 dev_info->max_event_queue_priority_levels = 8;
494 dev_info->max_event_priority_levels = 1;
495 dev_info->max_event_ports = dev->max_event_ports;
496 dev_info->max_event_port_dequeue_depth = 1;
497 dev_info->max_event_port_enqueue_depth = 1;
498 dev_info->max_num_events = dev->max_num_events;
499 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
500 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
501 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
502 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
503 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
504 RTE_EVENT_DEV_CAP_NONSEQ_MODE |
505 RTE_EVENT_DEV_CAP_CARRY_FLOW_ID;
509 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
511 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
515 val |= 0ULL << 12; /* SET 0 */
516 val |= 0x8000800080000000; /* Dont modify rest of the masks */
517 val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */
519 otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
523 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
524 const uint8_t queues[], const uint8_t priorities[],
527 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
531 RTE_SET_USED(priorities);
532 for (link = 0; link < nb_links; link++) {
534 struct otx2_ssogws_dual *ws = port;
537 sso_port_link_modify((struct otx2_ssogws *)
538 &ws->ws_state[0], queues[link], true);
539 sso_port_link_modify((struct otx2_ssogws *)
540 &ws->ws_state[1], queues[link], true);
542 struct otx2_ssogws *ws = port;
545 sso_port_link_modify(ws, queues[link], true);
548 sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
550 return (int)nb_links;
554 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
555 uint8_t queues[], uint16_t nb_unlinks)
557 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
561 for (unlink = 0; unlink < nb_unlinks; unlink++) {
563 struct otx2_ssogws_dual *ws = port;
566 sso_port_link_modify((struct otx2_ssogws *)
567 &ws->ws_state[0], queues[unlink],
569 sso_port_link_modify((struct otx2_ssogws *)
570 &ws->ws_state[1], queues[unlink],
573 struct otx2_ssogws *ws = port;
576 sso_port_link_modify(ws, queues[unlink], false);
579 sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
581 return (int)nb_unlinks;
585 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
586 uint16_t nb_lf, uint8_t attach)
589 struct rsrc_attach_req *req;
591 req = otx2_mbox_alloc_msg_attach_resources(mbox);
603 if (otx2_mbox_process(mbox) < 0)
606 struct rsrc_detach_req *req;
608 req = otx2_mbox_alloc_msg_detach_resources(mbox);
620 if (otx2_mbox_process(mbox) < 0)
628 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
629 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
638 struct sso_lf_alloc_req *req_ggrp;
639 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
640 req_ggrp->hwgrps = nb_lf;
645 struct ssow_lf_alloc_req *req_hws;
646 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
647 req_hws->hws = nb_lf;
657 struct sso_lf_free_req *req_ggrp;
658 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
659 req_ggrp->hwgrps = nb_lf;
664 struct ssow_lf_free_req *req_hws;
665 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
666 req_hws->hws = nb_lf;
674 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
678 if (alloc && type == SSO_LF_GGRP) {
679 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
681 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
682 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
683 dev->iue = rsp_ggrp->in_unit_entries;
690 otx2_sso_port_release(void *port)
692 struct otx2_ssogws_cookie *gws_cookie = ssogws_get_cookie(port);
693 struct otx2_sso_evdev *dev;
696 if (!gws_cookie->configured)
699 dev = sso_pmd_priv(gws_cookie->event_dev);
701 struct otx2_ssogws_dual *ws = port;
703 for (i = 0; i < dev->nb_event_queues; i++) {
704 sso_port_link_modify((struct otx2_ssogws *)
705 &ws->ws_state[0], i, false);
706 sso_port_link_modify((struct otx2_ssogws *)
707 &ws->ws_state[1], i, false);
709 memset(ws, 0, sizeof(*ws));
711 struct otx2_ssogws *ws = port;
713 for (i = 0; i < dev->nb_event_queues; i++)
714 sso_port_link_modify(ws, i, false);
715 memset(ws, 0, sizeof(*ws));
718 memset(gws_cookie, 0, sizeof(*gws_cookie));
721 rte_free(gws_cookie);
725 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
727 RTE_SET_USED(event_dev);
728 RTE_SET_USED(queue_id);
732 sso_restore_links(const struct rte_eventdev *event_dev)
734 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
738 for (i = 0; i < dev->nb_event_ports; i++) {
739 links_map = event_dev->data->links_map;
740 /* Point links_map to this port specific area */
741 links_map += (i * RTE_EVENT_MAX_QUEUES_PER_DEV);
743 struct otx2_ssogws_dual *ws;
745 ws = event_dev->data->ports[i];
746 for (j = 0; j < dev->nb_event_queues; j++) {
747 if (links_map[j] == 0xdead)
749 sso_port_link_modify((struct otx2_ssogws *)
750 &ws->ws_state[0], j, true);
751 sso_port_link_modify((struct otx2_ssogws *)
752 &ws->ws_state[1], j, true);
753 sso_func_trace("Restoring port %d queue %d "
757 struct otx2_ssogws *ws;
759 ws = event_dev->data->ports[i];
760 for (j = 0; j < dev->nb_event_queues; j++) {
761 if (links_map[j] == 0xdead)
763 sso_port_link_modify(ws, j, true);
764 sso_func_trace("Restoring port %d queue %d "
772 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
774 ws->tag_op = base + SSOW_LF_GWS_TAG;
775 ws->wqp_op = base + SSOW_LF_GWS_WQP;
776 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
777 ws->swtag_flush_op = base + SSOW_LF_GWS_OP_SWTAG_FLUSH;
778 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
779 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
783 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
785 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
786 struct otx2_mbox *mbox = dev->mbox;
791 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
793 nb_lf = dev->nb_event_ports * 2;
794 /* Ask AF to attach required LFs. */
795 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
797 otx2_err("Failed to attach SSO GWS LF");
801 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
802 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
803 otx2_err("Failed to init SSO GWS LF");
807 for (i = 0; i < dev->nb_event_ports; i++) {
808 struct otx2_ssogws_cookie *gws_cookie;
809 struct otx2_ssogws_dual *ws;
812 if (event_dev->data->ports[i] != NULL) {
813 ws = event_dev->data->ports[i];
815 /* Allocate event port memory */
816 ws = rte_zmalloc_socket("otx2_sso_ws",
817 sizeof(struct otx2_ssogws_dual) +
820 event_dev->data->socket_id);
822 otx2_err("Failed to alloc memory for port=%d",
828 /* First cache line is reserved for cookie */
829 ws = (struct otx2_ssogws_dual *)
830 ((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
834 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
835 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
839 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
840 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
844 gws_cookie = ssogws_get_cookie(ws);
845 gws_cookie->event_dev = event_dev;
846 gws_cookie->configured = 1;
848 event_dev->data->ports[i] = ws;
852 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
853 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
860 sso_configure_ports(const struct rte_eventdev *event_dev)
862 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
863 struct otx2_mbox *mbox = dev->mbox;
867 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
869 nb_lf = dev->nb_event_ports;
870 /* Ask AF to attach required LFs. */
871 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
873 otx2_err("Failed to attach SSO GWS LF");
877 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
878 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
879 otx2_err("Failed to init SSO GWS LF");
883 for (i = 0; i < nb_lf; i++) {
884 struct otx2_ssogws_cookie *gws_cookie;
885 struct otx2_ssogws *ws;
888 /* Free memory prior to re-allocation if needed */
889 if (event_dev->data->ports[i] != NULL) {
890 ws = event_dev->data->ports[i];
891 rte_free(ssogws_get_cookie(ws));
895 /* Allocate event port memory */
896 ws = rte_zmalloc_socket("otx2_sso_ws",
897 sizeof(struct otx2_ssogws) +
900 event_dev->data->socket_id);
902 otx2_err("Failed to alloc memory for port=%d", i);
907 /* First cache line is reserved for cookie */
908 ws = (struct otx2_ssogws *)
909 ((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
912 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
913 sso_set_port_ops(ws, base);
916 gws_cookie = ssogws_get_cookie(ws);
917 gws_cookie->event_dev = event_dev;
918 gws_cookie->configured = 1;
920 event_dev->data->ports[i] = ws;
924 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
925 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
932 sso_configure_queues(const struct rte_eventdev *event_dev)
934 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
935 struct otx2_mbox *mbox = dev->mbox;
939 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
941 nb_lf = dev->nb_event_queues;
942 /* Ask AF to attach required LFs. */
943 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
945 otx2_err("Failed to attach SSO GGRP LF");
949 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
950 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
951 otx2_err("Failed to init SSO GGRP LF");
959 sso_xaq_allocate(struct otx2_sso_evdev *dev)
961 const struct rte_memzone *mz;
962 struct npa_aura_s *aura;
963 static int reconfig_cnt;
964 char pool_name[RTE_MEMZONE_NAMESIZE];
969 rte_mempool_free(dev->xaq_pool);
972 * Allocate memory for Add work backpressure.
974 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
976 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
978 sizeof(struct npa_aura_s),
980 RTE_MEMZONE_IOVA_CONTIG,
983 otx2_err("Failed to allocate mem for fcmem");
987 dev->fc_iova = mz->iova;
988 dev->fc_mem = mz->addr;
990 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
991 memset(aura, 0, sizeof(struct npa_aura_s));
994 aura->fc_addr = dev->fc_iova;
995 aura->fc_hyst_bits = 0; /* Store count on all updates */
997 /* Taken from HRM 14.3.3(4) */
998 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
1000 xaq_cnt += dev->xae_cnt / dev->xae_waes;
1001 else if (dev->adptr_xae_cnt)
1002 xaq_cnt += (dev->adptr_xae_cnt / dev->xae_waes) +
1003 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
1005 xaq_cnt += (dev->iue / dev->xae_waes) +
1006 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
1008 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
1009 /* Setup XAQ based on number of nb queues. */
1010 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
1011 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
1012 xaq_cnt, dev->xaq_buf_size, 0, 0,
1013 rte_socket_id(), 0);
1015 if (dev->xaq_pool == NULL) {
1016 otx2_err("Unable to create empty mempool.");
1017 rte_memzone_free(mz);
1021 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
1022 rte_mbuf_platform_mempool_ops(), aura);
1024 otx2_err("Unable to set xaqpool ops.");
1028 rc = rte_mempool_populate_default(dev->xaq_pool);
1030 otx2_err("Unable to set populate xaqpool.");
1034 /* When SW does addwork (enqueue) check if there is space in XAQ by
1035 * comparing fc_addr above against the xaq_lmt calculated below.
1036 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
1037 * to request XAQ to cache them even before enqueue is called.
1039 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
1040 dev->nb_event_queues);
1041 dev->nb_xaq_cfg = xaq_cnt;
1045 rte_mempool_free(dev->xaq_pool);
1046 rte_memzone_free(mz);
1051 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
1053 struct otx2_mbox *mbox = dev->mbox;
1054 struct sso_hw_setconfig *req;
1056 otx2_sso_dbg("Configuring XAQ for GGRPs");
1057 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
1058 req->npa_pf_func = otx2_npa_pf_func_get();
1059 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
1060 req->hwgrps = dev->nb_event_queues;
1062 return otx2_mbox_process(mbox);
1066 sso_ggrp_free_xaq(struct otx2_sso_evdev *dev)
1068 struct otx2_mbox *mbox = dev->mbox;
1069 struct sso_release_xaq *req;
1071 otx2_sso_dbg("Freeing XAQ for GGRPs");
1072 req = otx2_mbox_alloc_msg_sso_hw_release_xaq_aura(mbox);
1073 req->hwgrps = dev->nb_event_queues;
1075 return otx2_mbox_process(mbox);
1079 sso_lf_teardown(struct otx2_sso_evdev *dev,
1080 enum otx2_sso_lf_type lf_type)
1086 nb_lf = dev->nb_event_queues;
1089 nb_lf = dev->nb_event_ports;
1090 nb_lf *= dev->dual_ws ? 2 : 1;
1096 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
1097 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
1101 otx2_sso_configure(const struct rte_eventdev *event_dev)
1103 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
1104 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1105 uint32_t deq_tmo_ns;
1109 deq_tmo_ns = conf->dequeue_timeout_ns;
1111 if (deq_tmo_ns == 0)
1112 deq_tmo_ns = dev->min_dequeue_timeout_ns;
1114 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
1115 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
1116 otx2_err("Unsupported dequeue timeout requested");
1120 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
1121 dev->is_timeout_deq = 1;
1123 dev->deq_tmo_ns = deq_tmo_ns;
1125 if (conf->nb_event_ports > dev->max_event_ports ||
1126 conf->nb_event_queues > dev->max_event_queues) {
1127 otx2_err("Unsupported event queues/ports requested");
1131 if (conf->nb_event_port_dequeue_depth > 1) {
1132 otx2_err("Unsupported event port deq depth requested");
1136 if (conf->nb_event_port_enqueue_depth > 1) {
1137 otx2_err("Unsupported event port enq depth requested");
1141 if (dev->configured)
1142 sso_unregister_irqs(event_dev);
1144 if (dev->nb_event_queues) {
1145 /* Finit any previous queues. */
1146 sso_lf_teardown(dev, SSO_LF_GGRP);
1148 if (dev->nb_event_ports) {
1149 /* Finit any previous ports. */
1150 sso_lf_teardown(dev, SSO_LF_GWS);
1153 dev->nb_event_queues = conf->nb_event_queues;
1154 dev->nb_event_ports = conf->nb_event_ports;
1157 rc = sso_configure_dual_ports(event_dev);
1159 rc = sso_configure_ports(event_dev);
1162 otx2_err("Failed to configure event ports");
1166 if (sso_configure_queues(event_dev) < 0) {
1167 otx2_err("Failed to configure event queues");
1172 if (sso_xaq_allocate(dev) < 0) {
1174 goto teardown_hwggrp;
1177 /* Restore any prior port-queue mapping. */
1178 sso_restore_links(event_dev);
1179 rc = sso_ggrp_alloc_xaq(dev);
1181 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1182 goto teardown_hwggrp;
1185 rc = sso_get_msix_offsets(event_dev);
1187 otx2_err("Failed to get msix offsets %d", rc);
1188 goto teardown_hwggrp;
1191 rc = sso_register_irqs(event_dev);
1193 otx2_err("Failed to register irq %d", rc);
1194 goto teardown_hwggrp;
1197 dev->configured = 1;
1202 sso_lf_teardown(dev, SSO_LF_GGRP);
1204 sso_lf_teardown(dev, SSO_LF_GWS);
1205 dev->nb_event_queues = 0;
1206 dev->nb_event_ports = 0;
1207 dev->configured = 0;
1212 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
1213 struct rte_event_queue_conf *queue_conf)
1215 RTE_SET_USED(event_dev);
1216 RTE_SET_USED(queue_id);
1218 queue_conf->nb_atomic_flows = (1ULL << 20);
1219 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
1220 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
1221 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
1225 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
1226 const struct rte_event_queue_conf *queue_conf)
1228 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1229 struct otx2_mbox *mbox = dev->mbox;
1230 struct sso_grp_priority *req;
1233 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
1235 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
1236 req->grp = queue_id;
1238 req->affinity = 0xFF;
1239 /* Normalize <0-255> to <0-7> */
1240 req->priority = queue_conf->priority / 32;
1242 rc = otx2_mbox_process(mbox);
1244 otx2_err("Failed to set priority queue=%d", queue_id);
1252 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
1253 struct rte_event_port_conf *port_conf)
1255 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1257 RTE_SET_USED(port_id);
1258 port_conf->new_event_threshold = dev->max_num_events;
1259 port_conf->dequeue_depth = 1;
1260 port_conf->enqueue_depth = 1;
1264 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
1265 const struct rte_event_port_conf *port_conf)
1267 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1268 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
1272 sso_func_trace("Port=%d", port_id);
1273 RTE_SET_USED(port_conf);
1275 if (event_dev->data->ports[port_id] == NULL) {
1276 otx2_err("Invalid port Id %d", port_id);
1280 for (q = 0; q < dev->nb_event_queues; q++) {
1281 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
1282 if (grps_base[q] == 0) {
1283 otx2_err("Failed to get grp[%d] base addr", q);
1288 /* Set get_work timeout for HWS */
1289 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
1292 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
1294 rte_memcpy(ws->grps_base, grps_base,
1295 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1296 ws->fc_mem = dev->fc_mem;
1297 ws->xaq_lmt = dev->xaq_lmt;
1298 ws->tstamp = dev->tstamp;
1299 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1300 ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1301 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1302 ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1304 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
1305 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1307 rte_memcpy(ws->grps_base, grps_base,
1308 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1309 ws->fc_mem = dev->fc_mem;
1310 ws->xaq_lmt = dev->xaq_lmt;
1311 ws->tstamp = dev->tstamp;
1312 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
1315 otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
1321 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
1322 uint64_t *tmo_ticks)
1324 RTE_SET_USED(event_dev);
1325 *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
1331 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
1333 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1335 fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base);
1336 fprintf(f, "SSOW_LF_GWS_LINKS 0x%" PRIx64 "\n",
1337 otx2_read64(base + SSOW_LF_GWS_LINKS));
1338 fprintf(f, "SSOW_LF_GWS_PENDWQP 0x%" PRIx64 "\n",
1339 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
1340 fprintf(f, "SSOW_LF_GWS_PENDSTATE 0x%" PRIx64 "\n",
1341 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
1342 fprintf(f, "SSOW_LF_GWS_NW_TIM 0x%" PRIx64 "\n",
1343 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
1344 fprintf(f, "SSOW_LF_GWS_TAG 0x%" PRIx64 "\n",
1345 otx2_read64(base + SSOW_LF_GWS_TAG));
1346 fprintf(f, "SSOW_LF_GWS_WQP 0x%" PRIx64 "\n",
1347 otx2_read64(base + SSOW_LF_GWS_TAG));
1348 fprintf(f, "SSOW_LF_GWS_SWTP 0x%" PRIx64 "\n",
1349 otx2_read64(base + SSOW_LF_GWS_SWTP));
1350 fprintf(f, "SSOW_LF_GWS_PENDTAG 0x%" PRIx64 "\n",
1351 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
1355 ssoggrp_dump(uintptr_t base, FILE *f)
1357 fprintf(f, "SSO_LF_GGRP Base addr 0x%" PRIx64 "\n", (uint64_t)base);
1358 fprintf(f, "SSO_LF_GGRP_QCTL 0x%" PRIx64 "\n",
1359 otx2_read64(base + SSO_LF_GGRP_QCTL));
1360 fprintf(f, "SSO_LF_GGRP_XAQ_CNT 0x%" PRIx64 "\n",
1361 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
1362 fprintf(f, "SSO_LF_GGRP_INT_THR 0x%" PRIx64 "\n",
1363 otx2_read64(base + SSO_LF_GGRP_INT_THR));
1364 fprintf(f, "SSO_LF_GGRP_INT_CNT 0x%" PRIX64 "\n",
1365 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
1366 fprintf(f, "SSO_LF_GGRP_AQ_CNT 0x%" PRIX64 "\n",
1367 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
1368 fprintf(f, "SSO_LF_GGRP_AQ_THR 0x%" PRIX64 "\n",
1369 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
1370 fprintf(f, "SSO_LF_GGRP_MISC_CNT 0x%" PRIx64 "\n",
1371 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
1375 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
1377 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1381 fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
1382 "dual_ws" : "single_ws");
1383 /* Dump SSOW registers */
1384 for (port = 0; port < dev->nb_event_ports; port++) {
1386 struct otx2_ssogws_dual *ws =
1387 event_dev->data->ports[port];
1389 fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
1391 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
1392 fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
1394 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
1396 fprintf(f, "[%s]SSO single workslot[%d] dump\n",
1398 ssogws_dump(event_dev->data->ports[port], f);
1402 /* Dump SSO registers */
1403 for (queue = 0; queue < dev->nb_event_queues; queue++) {
1404 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
1406 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1407 ssoggrp_dump(ws->grps_base[queue], f);
1409 struct otx2_ssogws *ws = event_dev->data->ports[0];
1410 ssoggrp_dump(ws->grps_base[queue], f);
1416 otx2_handle_event(void *arg, struct rte_event event)
1418 struct rte_eventdev *event_dev = arg;
1420 if (event_dev->dev_ops->dev_stop_flush != NULL)
1421 event_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,
1422 event, event_dev->data->dev_stop_flush_arg);
1426 sso_qos_cfg(struct rte_eventdev *event_dev)
1428 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1429 struct sso_grp_qos_cfg *req;
1432 for (i = 0; i < dev->qos_queue_cnt; i++) {
1433 uint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
1434 uint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
1435 uint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
1437 if (dev->qos_parse_data[i].queue >= dev->nb_event_queues)
1440 req = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);
1441 req->xaq_limit = (dev->nb_xaq_cfg *
1442 (xaq_prcnt ? xaq_prcnt : 100)) / 100;
1443 req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *
1444 (iaq_prcnt ? iaq_prcnt : 100)) / 100;
1445 req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *
1446 (taq_prcnt ? taq_prcnt : 100)) / 100;
1449 if (dev->qos_queue_cnt)
1450 otx2_mbox_process(dev->mbox);
1454 sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
1456 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1459 for (i = 0; i < dev->nb_event_ports; i++) {
1461 struct otx2_ssogws_dual *ws;
1463 ws = event_dev->data->ports[i];
1464 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);
1465 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
1468 ws->fc_mem = dev->fc_mem;
1469 ws->xaq_lmt = dev->xaq_lmt;
1471 struct otx2_ssogws *ws;
1473 ws = event_dev->data->ports[i];
1476 ws->fc_mem = dev->fc_mem;
1477 ws->xaq_lmt = dev->xaq_lmt;
1483 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1484 struct otx2_ssogws temp_ws;
1486 memcpy(&temp_ws, &ws->ws_state[0],
1487 sizeof(struct otx2_ssogws_state));
1488 for (i = 0; i < dev->nb_event_queues; i++) {
1489 /* Consume all the events through HWS0 */
1490 ssogws_flush_events(&temp_ws, i, ws->grps_base[i],
1491 otx2_handle_event, event_dev);
1492 /* Enable/Disable SSO GGRP */
1493 otx2_write64(enable, ws->grps_base[i] +
1497 struct otx2_ssogws *ws = event_dev->data->ports[0];
1499 for (i = 0; i < dev->nb_event_queues; i++) {
1500 /* Consume all the events through HWS0 */
1501 ssogws_flush_events(ws, i, ws->grps_base[i],
1502 otx2_handle_event, event_dev);
1503 /* Enable/Disable SSO GGRP */
1504 otx2_write64(enable, ws->grps_base[i] +
1509 /* reset SSO GWS cache */
1510 otx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);
1511 otx2_mbox_process(dev->mbox);
1515 sso_xae_reconfigure(struct rte_eventdev *event_dev)
1517 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1520 if (event_dev->data->dev_started)
1521 sso_cleanup(event_dev, 0);
1523 rc = sso_ggrp_free_xaq(dev);
1525 otx2_err("Failed to free XAQ\n");
1529 rte_mempool_free(dev->xaq_pool);
1530 dev->xaq_pool = NULL;
1531 rc = sso_xaq_allocate(dev);
1533 otx2_err("Failed to alloc xaq pool %d", rc);
1536 rc = sso_ggrp_alloc_xaq(dev);
1538 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1543 if (event_dev->data->dev_started)
1544 sso_cleanup(event_dev, 1);
1550 otx2_sso_start(struct rte_eventdev *event_dev)
1553 sso_qos_cfg(event_dev);
1554 sso_cleanup(event_dev, 1);
1555 sso_fastpath_fns_set(event_dev);
1561 otx2_sso_stop(struct rte_eventdev *event_dev)
1564 sso_cleanup(event_dev, 0);
1569 otx2_sso_close(struct rte_eventdev *event_dev)
1571 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1572 uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
1575 if (!dev->configured)
1578 sso_unregister_irqs(event_dev);
1580 for (i = 0; i < dev->nb_event_queues; i++)
1583 for (i = 0; i < dev->nb_event_ports; i++)
1584 otx2_sso_port_unlink(event_dev, event_dev->data->ports[i],
1585 all_queues, dev->nb_event_queues);
1587 sso_lf_teardown(dev, SSO_LF_GGRP);
1588 sso_lf_teardown(dev, SSO_LF_GWS);
1589 dev->nb_event_ports = 0;
1590 dev->nb_event_queues = 0;
1591 rte_mempool_free(dev->xaq_pool);
1592 rte_memzone_free(rte_memzone_lookup(OTX2_SSO_FC_NAME));
1597 /* Initialize and register event driver with DPDK Application */
1598 static struct rte_eventdev_ops otx2_sso_ops = {
1599 .dev_infos_get = otx2_sso_info_get,
1600 .dev_configure = otx2_sso_configure,
1601 .queue_def_conf = otx2_sso_queue_def_conf,
1602 .queue_setup = otx2_sso_queue_setup,
1603 .queue_release = otx2_sso_queue_release,
1604 .port_def_conf = otx2_sso_port_def_conf,
1605 .port_setup = otx2_sso_port_setup,
1606 .port_release = otx2_sso_port_release,
1607 .port_link = otx2_sso_port_link,
1608 .port_unlink = otx2_sso_port_unlink,
1609 .timeout_ticks = otx2_sso_timeout_ticks,
1611 .eth_rx_adapter_caps_get = otx2_sso_rx_adapter_caps_get,
1612 .eth_rx_adapter_queue_add = otx2_sso_rx_adapter_queue_add,
1613 .eth_rx_adapter_queue_del = otx2_sso_rx_adapter_queue_del,
1614 .eth_rx_adapter_start = otx2_sso_rx_adapter_start,
1615 .eth_rx_adapter_stop = otx2_sso_rx_adapter_stop,
1617 .eth_tx_adapter_caps_get = otx2_sso_tx_adapter_caps_get,
1618 .eth_tx_adapter_queue_add = otx2_sso_tx_adapter_queue_add,
1619 .eth_tx_adapter_queue_del = otx2_sso_tx_adapter_queue_del,
1621 .timer_adapter_caps_get = otx2_tim_caps_get,
1623 .crypto_adapter_caps_get = otx2_ca_caps_get,
1624 .crypto_adapter_queue_pair_add = otx2_ca_qp_add,
1625 .crypto_adapter_queue_pair_del = otx2_ca_qp_del,
1627 .xstats_get = otx2_sso_xstats_get,
1628 .xstats_reset = otx2_sso_xstats_reset,
1629 .xstats_get_names = otx2_sso_xstats_get_names,
1631 .dump = otx2_sso_dump,
1632 .dev_start = otx2_sso_start,
1633 .dev_stop = otx2_sso_stop,
1634 .dev_close = otx2_sso_close,
1635 .dev_selftest = otx2_sso_selftest,
1638 #define OTX2_SSO_XAE_CNT "xae_cnt"
1639 #define OTX2_SSO_SINGLE_WS "single_ws"
1640 #define OTX2_SSO_GGRP_QOS "qos"
1643 parse_queue_param(char *value, void *opaque)
1645 struct otx2_sso_qos queue_qos = {0};
1646 uint8_t *val = (uint8_t *)&queue_qos;
1647 struct otx2_sso_evdev *dev = opaque;
1648 char *tok = strtok(value, "-");
1649 struct otx2_sso_qos *old_ptr;
1654 while (tok != NULL) {
1656 tok = strtok(NULL, "-");
1660 if (val != (&queue_qos.iaq_prcnt + 1)) {
1661 otx2_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
1665 dev->qos_queue_cnt++;
1666 old_ptr = dev->qos_parse_data;
1667 dev->qos_parse_data = rte_realloc(dev->qos_parse_data,
1668 sizeof(struct otx2_sso_qos) *
1669 dev->qos_queue_cnt, 0);
1670 if (dev->qos_parse_data == NULL) {
1671 dev->qos_parse_data = old_ptr;
1672 dev->qos_queue_cnt--;
1675 dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
1679 parse_qos_list(const char *value, void *opaque)
1681 char *s = strdup(value);
1692 if (start && start < end) {
1694 parse_queue_param(start + 1, opaque);
1705 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
1709 /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
1710 * isn't allowed. Everything is expressed in percentages, 0 represents
1713 parse_qos_list(value, opaque);
1719 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
1721 struct rte_kvargs *kvlist;
1722 uint8_t single_ws = 0;
1724 if (devargs == NULL)
1726 kvlist = rte_kvargs_parse(devargs->args, NULL);
1730 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
1732 rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
1734 rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
1736 otx2_parse_common_devargs(kvlist);
1737 dev->dual_ws = !single_ws;
1738 rte_kvargs_free(kvlist);
1742 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1744 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1745 sizeof(struct otx2_sso_evdev),
1750 otx2_sso_remove(struct rte_pci_device *pci_dev)
1752 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
1755 static const struct rte_pci_id pci_sso_map[] = {
1757 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1758 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
1765 static struct rte_pci_driver pci_sso = {
1766 .id_table = pci_sso_map,
1767 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1768 .probe = otx2_sso_probe,
1769 .remove = otx2_sso_remove,
1773 otx2_sso_init(struct rte_eventdev *event_dev)
1775 struct free_rsrcs_rsp *rsrc_cnt;
1776 struct rte_pci_device *pci_dev;
1777 struct otx2_sso_evdev *dev;
1780 event_dev->dev_ops = &otx2_sso_ops;
1781 /* For secondary processes, the primary has done all the work */
1782 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1783 sso_fastpath_fns_set(event_dev);
1787 dev = sso_pmd_priv(event_dev);
1789 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1791 /* Initialize the base otx2_dev object */
1792 rc = otx2_dev_init(pci_dev, dev);
1794 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1798 /* Get SSO and SSOW MSIX rsrc cnt */
1799 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
1800 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
1802 otx2_err("Unable to get free rsrc count");
1803 goto otx2_dev_uninit;
1805 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
1806 rsrc_cnt->ssow, rsrc_cnt->npa);
1808 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
1809 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
1810 /* Grab the NPA LF if required */
1811 rc = otx2_npa_lf_init(pci_dev, dev);
1813 otx2_err("Unable to init NPA lf. It might not be provisioned");
1814 goto otx2_dev_uninit;
1817 dev->drv_inited = true;
1818 dev->is_timeout_deq = 0;
1819 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1820 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1821 dev->max_num_events = -1;
1822 dev->nb_event_queues = 0;
1823 dev->nb_event_ports = 0;
1825 if (!dev->max_event_ports || !dev->max_event_queues) {
1826 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1827 dev->max_event_queues, dev->max_event_ports);
1829 goto otx2_npa_lf_uninit;
1833 sso_parse_devargs(dev, pci_dev->device.devargs);
1835 otx2_sso_dbg("Using dual workslot mode");
1836 dev->max_event_ports = dev->max_event_ports / 2;
1838 otx2_sso_dbg("Using single workslot mode");
1841 otx2_sso_pf_func_set(dev->pf_func);
1842 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1843 event_dev->data->name, dev->max_event_queues,
1844 dev->max_event_ports);
1846 otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
1853 otx2_dev_fini(pci_dev, dev);
1859 otx2_sso_fini(struct rte_eventdev *event_dev)
1861 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1862 struct rte_pci_device *pci_dev;
1864 /* For secondary processes, nothing to be done */
1865 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1868 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1870 if (!dev->drv_inited)
1873 dev->drv_inited = false;
1877 if (otx2_npa_lf_active(dev)) {
1878 otx2_info("Common resource in use by other devices");
1883 otx2_dev_fini(pci_dev, dev);
1888 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1889 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1890 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1891 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
1892 OTX2_SSO_SINGLE_WS "=1"
1893 OTX2_SSO_GGRP_QOS "=<string>"
1894 OTX2_NPA_LOCK_MASK "=<1-65535>");