1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <rte_eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev_stats.h"
16 #include "otx2_evdev.h"
18 #include "otx2_tim_evdev.h"
21 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
23 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
24 uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
25 struct otx2_mbox *mbox = dev->mbox;
26 struct msix_offset_rsp *msix_rsp;
29 /* Get SSO and SSOW MSIX vector offsets */
30 otx2_mbox_alloc_msg_msix_offset(mbox);
31 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
33 for (i = 0; i < nb_ports; i++)
34 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
36 for (i = 0; i < dev->nb_event_queues; i++)
37 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
43 sso_fastpath_fns_set(struct rte_eventdev *event_dev)
45 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
47 event_dev->enqueue = otx2_ssogws_enq;
48 event_dev->enqueue_burst = otx2_ssogws_enq_burst;
49 event_dev->enqueue_new_burst = otx2_ssogws_enq_new_burst;
50 event_dev->enqueue_forward_burst = otx2_ssogws_enq_fwd_burst;
52 event_dev->dequeue = otx2_ssogws_deq;
53 event_dev->dequeue_burst = otx2_ssogws_deq_burst;
54 if (dev->is_timeout_deq) {
55 event_dev->dequeue = otx2_ssogws_deq_timeout;
56 event_dev->dequeue_burst = otx2_ssogws_deq_timeout_burst;
60 event_dev->enqueue = otx2_ssogws_dual_enq;
61 event_dev->enqueue_burst = otx2_ssogws_dual_enq_burst;
62 event_dev->enqueue_new_burst =
63 otx2_ssogws_dual_enq_new_burst;
64 event_dev->enqueue_forward_burst =
65 otx2_ssogws_dual_enq_fwd_burst;
66 event_dev->dequeue = otx2_ssogws_dual_deq;
67 event_dev->dequeue_burst = otx2_ssogws_dual_deq_burst;
68 if (dev->is_timeout_deq) {
69 event_dev->dequeue = otx2_ssogws_dual_deq_timeout;
70 event_dev->dequeue_burst =
71 otx2_ssogws_dual_deq_timeout_burst;
78 otx2_sso_info_get(struct rte_eventdev *event_dev,
79 struct rte_event_dev_info *dev_info)
81 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
83 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
84 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
85 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
86 dev_info->max_event_queues = dev->max_event_queues;
87 dev_info->max_event_queue_flows = (1ULL << 20);
88 dev_info->max_event_queue_priority_levels = 8;
89 dev_info->max_event_priority_levels = 1;
90 dev_info->max_event_ports = dev->max_event_ports;
91 dev_info->max_event_port_dequeue_depth = 1;
92 dev_info->max_event_port_enqueue_depth = 1;
93 dev_info->max_num_events = dev->max_num_events;
94 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
95 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
96 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
97 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
98 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
99 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
103 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
105 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
109 val |= 0ULL << 12; /* SET 0 */
110 val |= 0x8000800080000000; /* Dont modify rest of the masks */
111 val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */
113 otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
117 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
118 const uint8_t queues[], const uint8_t priorities[],
121 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
125 RTE_SET_USED(priorities);
126 for (link = 0; link < nb_links; link++) {
128 struct otx2_ssogws_dual *ws = port;
131 sso_port_link_modify((struct otx2_ssogws *)
132 &ws->ws_state[0], queues[link], true);
133 sso_port_link_modify((struct otx2_ssogws *)
134 &ws->ws_state[1], queues[link], true);
136 struct otx2_ssogws *ws = port;
139 sso_port_link_modify(ws, queues[link], true);
142 sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
144 return (int)nb_links;
148 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
149 uint8_t queues[], uint16_t nb_unlinks)
151 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
155 for (unlink = 0; unlink < nb_unlinks; unlink++) {
157 struct otx2_ssogws_dual *ws = port;
160 sso_port_link_modify((struct otx2_ssogws *)
161 &ws->ws_state[0], queues[unlink],
163 sso_port_link_modify((struct otx2_ssogws *)
164 &ws->ws_state[1], queues[unlink],
167 struct otx2_ssogws *ws = port;
170 sso_port_link_modify(ws, queues[unlink], false);
173 sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
175 return (int)nb_unlinks;
179 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
180 uint16_t nb_lf, uint8_t attach)
183 struct rsrc_attach_req *req;
185 req = otx2_mbox_alloc_msg_attach_resources(mbox);
197 if (otx2_mbox_process(mbox) < 0)
200 struct rsrc_detach_req *req;
202 req = otx2_mbox_alloc_msg_detach_resources(mbox);
214 if (otx2_mbox_process(mbox) < 0)
222 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
223 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
232 struct sso_lf_alloc_req *req_ggrp;
233 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
234 req_ggrp->hwgrps = nb_lf;
239 struct ssow_lf_alloc_req *req_hws;
240 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
241 req_hws->hws = nb_lf;
251 struct sso_lf_free_req *req_ggrp;
252 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
253 req_ggrp->hwgrps = nb_lf;
258 struct ssow_lf_free_req *req_hws;
259 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
260 req_hws->hws = nb_lf;
268 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
272 if (alloc && type == SSO_LF_GGRP) {
273 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
275 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
276 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
277 dev->iue = rsp_ggrp->in_unit_entries;
284 otx2_sso_port_release(void *port)
290 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
292 RTE_SET_USED(event_dev);
293 RTE_SET_USED(queue_id);
297 sso_clr_links(const struct rte_eventdev *event_dev)
299 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
302 for (i = 0; i < dev->nb_event_ports; i++) {
304 struct otx2_ssogws_dual *ws;
306 ws = event_dev->data->ports[i];
307 for (j = 0; j < dev->nb_event_queues; j++) {
308 sso_port_link_modify((struct otx2_ssogws *)
309 &ws->ws_state[0], j, false);
310 sso_port_link_modify((struct otx2_ssogws *)
311 &ws->ws_state[1], j, false);
314 struct otx2_ssogws *ws;
316 ws = event_dev->data->ports[i];
317 for (j = 0; j < dev->nb_event_queues; j++)
318 sso_port_link_modify(ws, j, false);
324 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
326 ws->tag_op = base + SSOW_LF_GWS_TAG;
327 ws->wqp_op = base + SSOW_LF_GWS_WQP;
328 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
329 ws->swtp_op = base + SSOW_LF_GWS_SWTP;
330 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
331 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
335 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
337 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
338 struct otx2_mbox *mbox = dev->mbox;
343 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
345 nb_lf = dev->nb_event_ports * 2;
346 /* Ask AF to attach required LFs. */
347 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
349 otx2_err("Failed to attach SSO GWS LF");
353 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
354 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
355 otx2_err("Failed to init SSO GWS LF");
359 for (i = 0; i < dev->nb_event_ports; i++) {
360 struct otx2_ssogws_dual *ws;
363 /* Free memory prior to re-allocation if needed */
364 if (event_dev->data->ports[i] != NULL) {
365 ws = event_dev->data->ports[i];
370 /* Allocate event port memory */
371 ws = rte_zmalloc_socket("otx2_sso_ws",
372 sizeof(struct otx2_ssogws_dual),
374 event_dev->data->socket_id);
376 otx2_err("Failed to alloc memory for port=%d", i);
382 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
383 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
386 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
387 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
390 event_dev->data->ports[i] = ws;
394 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
395 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
402 sso_configure_ports(const struct rte_eventdev *event_dev)
404 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
405 struct otx2_mbox *mbox = dev->mbox;
409 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
411 nb_lf = dev->nb_event_ports;
412 /* Ask AF to attach required LFs. */
413 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
415 otx2_err("Failed to attach SSO GWS LF");
419 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
420 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
421 otx2_err("Failed to init SSO GWS LF");
425 for (i = 0; i < nb_lf; i++) {
426 struct otx2_ssogws *ws;
429 /* Free memory prior to re-allocation if needed */
430 if (event_dev->data->ports[i] != NULL) {
431 ws = event_dev->data->ports[i];
436 /* Allocate event port memory */
437 ws = rte_zmalloc_socket("otx2_sso_ws",
438 sizeof(struct otx2_ssogws),
440 event_dev->data->socket_id);
442 otx2_err("Failed to alloc memory for port=%d", i);
448 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
449 sso_set_port_ops(ws, base);
451 event_dev->data->ports[i] = ws;
455 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
456 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
463 sso_configure_queues(const struct rte_eventdev *event_dev)
465 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
466 struct otx2_mbox *mbox = dev->mbox;
470 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
472 nb_lf = dev->nb_event_queues;
473 /* Ask AF to attach required LFs. */
474 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
476 otx2_err("Failed to attach SSO GGRP LF");
480 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
481 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
482 otx2_err("Failed to init SSO GGRP LF");
490 sso_xaq_allocate(struct otx2_sso_evdev *dev)
492 const struct rte_memzone *mz;
493 struct npa_aura_s *aura;
494 static int reconfig_cnt;
495 char pool_name[RTE_MEMZONE_NAMESIZE];
500 rte_mempool_free(dev->xaq_pool);
503 * Allocate memory for Add work backpressure.
505 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
507 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
509 sizeof(struct npa_aura_s),
511 RTE_MEMZONE_IOVA_CONTIG,
514 otx2_err("Failed to allocate mem for fcmem");
518 dev->fc_iova = mz->iova;
519 dev->fc_mem = mz->addr;
521 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
522 memset(aura, 0, sizeof(struct npa_aura_s));
525 aura->fc_addr = dev->fc_iova;
526 aura->fc_hyst_bits = 0; /* Store count on all updates */
528 /* Taken from HRM 14.3.3(4) */
529 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
531 xaq_cnt += dev->xae_cnt / dev->xae_waes;
532 else if (dev->adptr_xae_cnt)
533 xaq_cnt += (dev->adptr_xae_cnt / dev->xae_waes) +
534 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
536 xaq_cnt += (dev->iue / dev->xae_waes) +
537 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
539 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
540 /* Setup XAQ based on number of nb queues. */
541 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
542 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
543 xaq_cnt, dev->xaq_buf_size, 0, 0,
546 if (dev->xaq_pool == NULL) {
547 otx2_err("Unable to create empty mempool.");
548 rte_memzone_free(mz);
552 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
553 rte_mbuf_platform_mempool_ops(), aura);
555 otx2_err("Unable to set xaqpool ops.");
559 rc = rte_mempool_populate_default(dev->xaq_pool);
561 otx2_err("Unable to set populate xaqpool.");
565 /* When SW does addwork (enqueue) check if there is space in XAQ by
566 * comparing fc_addr above against the xaq_lmt calculated below.
567 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
568 * to request XAQ to cache them even before enqueue is called.
570 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
571 dev->nb_event_queues);
572 dev->nb_xaq_cfg = xaq_cnt;
576 rte_mempool_free(dev->xaq_pool);
577 rte_memzone_free(mz);
582 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
584 struct otx2_mbox *mbox = dev->mbox;
585 struct sso_hw_setconfig *req;
587 otx2_sso_dbg("Configuring XAQ for GGRPs");
588 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
589 req->npa_pf_func = otx2_npa_pf_func_get();
590 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
591 req->hwgrps = dev->nb_event_queues;
593 return otx2_mbox_process(mbox);
597 sso_lf_teardown(struct otx2_sso_evdev *dev,
598 enum otx2_sso_lf_type lf_type)
604 nb_lf = dev->nb_event_queues;
607 nb_lf = dev->nb_event_ports;
608 nb_lf *= dev->dual_ws ? 2 : 1;
614 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
615 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
619 otx2_sso_configure(const struct rte_eventdev *event_dev)
621 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
622 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
627 deq_tmo_ns = conf->dequeue_timeout_ns;
630 deq_tmo_ns = dev->min_dequeue_timeout_ns;
632 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
633 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
634 otx2_err("Unsupported dequeue timeout requested");
638 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
639 dev->is_timeout_deq = 1;
641 dev->deq_tmo_ns = deq_tmo_ns;
643 if (conf->nb_event_ports > dev->max_event_ports ||
644 conf->nb_event_queues > dev->max_event_queues) {
645 otx2_err("Unsupported event queues/ports requested");
649 if (conf->nb_event_port_dequeue_depth > 1) {
650 otx2_err("Unsupported event port deq depth requested");
654 if (conf->nb_event_port_enqueue_depth > 1) {
655 otx2_err("Unsupported event port enq depth requested");
660 sso_unregister_irqs(event_dev);
662 if (dev->nb_event_queues) {
663 /* Finit any previous queues. */
664 sso_lf_teardown(dev, SSO_LF_GGRP);
666 if (dev->nb_event_ports) {
667 /* Finit any previous ports. */
668 sso_lf_teardown(dev, SSO_LF_GWS);
671 dev->nb_event_queues = conf->nb_event_queues;
672 dev->nb_event_ports = conf->nb_event_ports;
675 rc = sso_configure_dual_ports(event_dev);
677 rc = sso_configure_ports(event_dev);
680 otx2_err("Failed to configure event ports");
684 if (sso_configure_queues(event_dev) < 0) {
685 otx2_err("Failed to configure event queues");
690 if (sso_xaq_allocate(dev) < 0) {
692 goto teardown_hwggrp;
695 /* Clear any prior port-queue mapping. */
696 sso_clr_links(event_dev);
697 rc = sso_ggrp_alloc_xaq(dev);
699 otx2_err("Failed to alloc xaq to ggrp %d", rc);
700 goto teardown_hwggrp;
703 rc = sso_get_msix_offsets(event_dev);
705 otx2_err("Failed to get msix offsets %d", rc);
706 goto teardown_hwggrp;
709 rc = sso_register_irqs(event_dev);
711 otx2_err("Failed to register irq %d", rc);
712 goto teardown_hwggrp;
720 sso_lf_teardown(dev, SSO_LF_GGRP);
722 sso_lf_teardown(dev, SSO_LF_GWS);
723 dev->nb_event_queues = 0;
724 dev->nb_event_ports = 0;
730 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
731 struct rte_event_queue_conf *queue_conf)
733 RTE_SET_USED(event_dev);
734 RTE_SET_USED(queue_id);
736 queue_conf->nb_atomic_flows = (1ULL << 20);
737 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
738 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
739 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
743 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
744 const struct rte_event_queue_conf *queue_conf)
746 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
747 struct otx2_mbox *mbox = dev->mbox;
748 struct sso_grp_priority *req;
751 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
753 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
756 req->affinity = 0xFF;
757 /* Normalize <0-255> to <0-7> */
758 req->priority = queue_conf->priority / 32;
760 rc = otx2_mbox_process(mbox);
762 otx2_err("Failed to set priority queue=%d", queue_id);
770 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
771 struct rte_event_port_conf *port_conf)
773 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
775 RTE_SET_USED(port_id);
776 port_conf->new_event_threshold = dev->max_num_events;
777 port_conf->dequeue_depth = 1;
778 port_conf->enqueue_depth = 1;
782 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
783 const struct rte_event_port_conf *port_conf)
785 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
786 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
790 sso_func_trace("Port=%d", port_id);
791 RTE_SET_USED(port_conf);
793 if (event_dev->data->ports[port_id] == NULL) {
794 otx2_err("Invalid port Id %d", port_id);
798 for (q = 0; q < dev->nb_event_queues; q++) {
799 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
800 if (grps_base[q] == 0) {
801 otx2_err("Failed to get grp[%d] base addr", q);
806 /* Set get_work timeout for HWS */
807 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
810 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
812 rte_memcpy(ws->grps_base, grps_base,
813 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
814 ws->fc_mem = dev->fc_mem;
815 ws->xaq_lmt = dev->xaq_lmt;
816 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
817 ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
818 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
819 ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
821 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
822 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
824 rte_memcpy(ws->grps_base, grps_base,
825 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
826 ws->fc_mem = dev->fc_mem;
827 ws->xaq_lmt = dev->xaq_lmt;
828 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
831 otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
837 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
840 RTE_SET_USED(event_dev);
841 *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
847 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
849 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
851 fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base);
852 fprintf(f, "SSOW_LF_GWS_LINKS 0x%" PRIx64 "\n",
853 otx2_read64(base + SSOW_LF_GWS_LINKS));
854 fprintf(f, "SSOW_LF_GWS_PENDWQP 0x%" PRIx64 "\n",
855 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
856 fprintf(f, "SSOW_LF_GWS_PENDSTATE 0x%" PRIx64 "\n",
857 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
858 fprintf(f, "SSOW_LF_GWS_NW_TIM 0x%" PRIx64 "\n",
859 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
860 fprintf(f, "SSOW_LF_GWS_TAG 0x%" PRIx64 "\n",
861 otx2_read64(base + SSOW_LF_GWS_TAG));
862 fprintf(f, "SSOW_LF_GWS_WQP 0x%" PRIx64 "\n",
863 otx2_read64(base + SSOW_LF_GWS_TAG));
864 fprintf(f, "SSOW_LF_GWS_SWTP 0x%" PRIx64 "\n",
865 otx2_read64(base + SSOW_LF_GWS_SWTP));
866 fprintf(f, "SSOW_LF_GWS_PENDTAG 0x%" PRIx64 "\n",
867 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
871 ssoggrp_dump(uintptr_t base, FILE *f)
873 fprintf(f, "SSO_LF_GGRP Base addr 0x%" PRIx64 "\n", (uint64_t)base);
874 fprintf(f, "SSO_LF_GGRP_QCTL 0x%" PRIx64 "\n",
875 otx2_read64(base + SSO_LF_GGRP_QCTL));
876 fprintf(f, "SSO_LF_GGRP_XAQ_CNT 0x%" PRIx64 "\n",
877 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
878 fprintf(f, "SSO_LF_GGRP_INT_THR 0x%" PRIx64 "\n",
879 otx2_read64(base + SSO_LF_GGRP_INT_THR));
880 fprintf(f, "SSO_LF_GGRP_INT_CNT 0x%" PRIX64 "\n",
881 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
882 fprintf(f, "SSO_LF_GGRP_AQ_CNT 0x%" PRIX64 "\n",
883 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
884 fprintf(f, "SSO_LF_GGRP_AQ_THR 0x%" PRIX64 "\n",
885 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
886 fprintf(f, "SSO_LF_GGRP_MISC_CNT 0x%" PRIx64 "\n",
887 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
891 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
893 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
897 fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
898 "dual_ws" : "single_ws");
899 /* Dump SSOW registers */
900 for (port = 0; port < dev->nb_event_ports; port++) {
902 struct otx2_ssogws_dual *ws =
903 event_dev->data->ports[port];
905 fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
907 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
908 fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
910 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
912 fprintf(f, "[%s]SSO single workslot[%d] dump\n",
914 ssogws_dump(event_dev->data->ports[port], f);
918 /* Dump SSO registers */
919 for (queue = 0; queue < dev->nb_event_queues; queue++) {
920 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
922 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
923 ssoggrp_dump(ws->grps_base[queue], f);
925 struct otx2_ssogws *ws = event_dev->data->ports[0];
926 ssoggrp_dump(ws->grps_base[queue], f);
932 otx2_handle_event(void *arg, struct rte_event event)
934 struct rte_eventdev *event_dev = arg;
936 if (event_dev->dev_ops->dev_stop_flush != NULL)
937 event_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,
938 event, event_dev->data->dev_stop_flush_arg);
942 sso_qos_cfg(struct rte_eventdev *event_dev)
944 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
945 struct sso_grp_qos_cfg *req;
948 for (i = 0; i < dev->qos_queue_cnt; i++) {
949 uint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
950 uint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
951 uint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
953 if (dev->qos_parse_data[i].queue >= dev->nb_event_queues)
956 req = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);
957 req->xaq_limit = (dev->nb_xaq_cfg *
958 (xaq_prcnt ? xaq_prcnt : 100)) / 100;
959 req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *
960 (iaq_prcnt ? iaq_prcnt : 100)) / 100;
961 req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *
962 (taq_prcnt ? taq_prcnt : 100)) / 100;
965 if (dev->qos_queue_cnt)
966 otx2_mbox_process(dev->mbox);
970 sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
972 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
975 for (i = 0; i < dev->nb_event_ports; i++) {
977 struct otx2_ssogws_dual *ws;
979 ws = event_dev->data->ports[i];
980 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);
981 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
984 ws->ws_state[0].cur_grp = 0;
985 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
986 ws->ws_state[1].cur_grp = 0;
987 ws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;
989 struct otx2_ssogws *ws;
991 ws = event_dev->data->ports[i];
995 ws->cur_tt = SSO_SYNC_EMPTY;
1001 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1002 struct otx2_ssogws temp_ws;
1004 memcpy(&temp_ws, &ws->ws_state[0],
1005 sizeof(struct otx2_ssogws_state));
1006 for (i = 0; i < dev->nb_event_queues; i++) {
1007 /* Consume all the events through HWS0 */
1008 ssogws_flush_events(&temp_ws, i, ws->grps_base[i],
1009 otx2_handle_event, event_dev);
1010 /* Enable/Disable SSO GGRP */
1011 otx2_write64(enable, ws->grps_base[i] +
1014 ws->ws_state[0].cur_grp = 0;
1015 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1017 struct otx2_ssogws *ws = event_dev->data->ports[0];
1019 for (i = 0; i < dev->nb_event_queues; i++) {
1020 /* Consume all the events through HWS0 */
1021 ssogws_flush_events(ws, i, ws->grps_base[i],
1022 otx2_handle_event, event_dev);
1023 /* Enable/Disable SSO GGRP */
1024 otx2_write64(enable, ws->grps_base[i] +
1028 ws->cur_tt = SSO_SYNC_EMPTY;
1031 /* reset SSO GWS cache */
1032 otx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);
1033 otx2_mbox_process(dev->mbox);
1037 sso_xae_reconfigure(struct rte_eventdev *event_dev)
1039 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1040 struct rte_mempool *prev_xaq_pool;
1043 if (event_dev->data->dev_started)
1044 sso_cleanup(event_dev, 0);
1046 prev_xaq_pool = dev->xaq_pool;
1047 dev->xaq_pool = NULL;
1048 sso_xaq_allocate(dev);
1049 rc = sso_ggrp_alloc_xaq(dev);
1051 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1052 rte_mempool_free(prev_xaq_pool);
1056 rte_mempool_free(prev_xaq_pool);
1058 if (event_dev->data->dev_started)
1059 sso_cleanup(event_dev, 1);
1065 otx2_sso_start(struct rte_eventdev *event_dev)
1068 sso_qos_cfg(event_dev);
1069 sso_cleanup(event_dev, 1);
1070 sso_fastpath_fns_set(event_dev);
1076 otx2_sso_stop(struct rte_eventdev *event_dev)
1079 sso_cleanup(event_dev, 0);
1084 otx2_sso_close(struct rte_eventdev *event_dev)
1086 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1087 uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
1090 if (!dev->configured)
1093 sso_unregister_irqs(event_dev);
1095 for (i = 0; i < dev->nb_event_queues; i++)
1098 for (i = 0; i < dev->nb_event_ports; i++)
1099 otx2_sso_port_unlink(event_dev, event_dev->data->ports[i],
1100 all_queues, dev->nb_event_queues);
1102 sso_lf_teardown(dev, SSO_LF_GGRP);
1103 sso_lf_teardown(dev, SSO_LF_GWS);
1104 dev->nb_event_ports = 0;
1105 dev->nb_event_queues = 0;
1106 rte_mempool_free(dev->xaq_pool);
1107 rte_memzone_free(rte_memzone_lookup(OTX2_SSO_FC_NAME));
1112 /* Initialize and register event driver with DPDK Application */
1113 static struct rte_eventdev_ops otx2_sso_ops = {
1114 .dev_infos_get = otx2_sso_info_get,
1115 .dev_configure = otx2_sso_configure,
1116 .queue_def_conf = otx2_sso_queue_def_conf,
1117 .queue_setup = otx2_sso_queue_setup,
1118 .queue_release = otx2_sso_queue_release,
1119 .port_def_conf = otx2_sso_port_def_conf,
1120 .port_setup = otx2_sso_port_setup,
1121 .port_release = otx2_sso_port_release,
1122 .port_link = otx2_sso_port_link,
1123 .port_unlink = otx2_sso_port_unlink,
1124 .timeout_ticks = otx2_sso_timeout_ticks,
1126 .timer_adapter_caps_get = otx2_tim_caps_get,
1128 .xstats_get = otx2_sso_xstats_get,
1129 .xstats_reset = otx2_sso_xstats_reset,
1130 .xstats_get_names = otx2_sso_xstats_get_names,
1132 .dump = otx2_sso_dump,
1133 .dev_start = otx2_sso_start,
1134 .dev_stop = otx2_sso_stop,
1135 .dev_close = otx2_sso_close,
1136 .dev_selftest = otx2_sso_selftest,
1139 #define OTX2_SSO_XAE_CNT "xae_cnt"
1140 #define OTX2_SSO_SINGLE_WS "single_ws"
1141 #define OTX2_SSO_GGRP_QOS "qos"
1142 #define OTX2_SSO_SELFTEST "selftest"
1145 parse_queue_param(char *value, void *opaque)
1147 struct otx2_sso_qos queue_qos = {0};
1148 uint8_t *val = (uint8_t *)&queue_qos;
1149 struct otx2_sso_evdev *dev = opaque;
1150 char *tok = strtok(value, "-");
1155 while (tok != NULL) {
1157 tok = strtok(NULL, "-");
1161 if (val != (&queue_qos.iaq_prcnt + 1)) {
1162 otx2_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
1166 dev->qos_queue_cnt++;
1167 dev->qos_parse_data = rte_realloc(dev->qos_parse_data,
1168 sizeof(struct otx2_sso_qos) *
1169 dev->qos_queue_cnt, 0);
1170 dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
1174 parse_qos_list(const char *value, void *opaque)
1176 char *s = strdup(value);
1187 if (start < end && *start) {
1189 parse_queue_param(start + 1, opaque);
1200 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
1204 /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
1205 * isn't allowed. Everything is expressed in percentages, 0 represents
1208 parse_qos_list(value, opaque);
1214 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
1216 struct rte_kvargs *kvlist;
1217 uint8_t single_ws = 0;
1219 if (devargs == NULL)
1221 kvlist = rte_kvargs_parse(devargs->args, NULL);
1225 rte_kvargs_process(kvlist, OTX2_SSO_SELFTEST, &parse_kvargs_flag,
1227 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
1229 rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
1231 rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
1234 dev->dual_ws = !single_ws;
1235 rte_kvargs_free(kvlist);
1239 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1241 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1242 sizeof(struct otx2_sso_evdev),
1247 otx2_sso_remove(struct rte_pci_device *pci_dev)
1249 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
1252 static const struct rte_pci_id pci_sso_map[] = {
1254 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1255 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
1262 static struct rte_pci_driver pci_sso = {
1263 .id_table = pci_sso_map,
1264 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1265 .probe = otx2_sso_probe,
1266 .remove = otx2_sso_remove,
1270 otx2_sso_init(struct rte_eventdev *event_dev)
1272 struct free_rsrcs_rsp *rsrc_cnt;
1273 struct rte_pci_device *pci_dev;
1274 struct otx2_sso_evdev *dev;
1277 event_dev->dev_ops = &otx2_sso_ops;
1278 /* For secondary processes, the primary has done all the work */
1279 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1280 sso_fastpath_fns_set(event_dev);
1284 dev = sso_pmd_priv(event_dev);
1286 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1288 /* Initialize the base otx2_dev object */
1289 rc = otx2_dev_init(pci_dev, dev);
1291 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1295 /* Get SSO and SSOW MSIX rsrc cnt */
1296 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
1297 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
1299 otx2_err("Unable to get free rsrc count");
1300 goto otx2_dev_uninit;
1302 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
1303 rsrc_cnt->ssow, rsrc_cnt->npa);
1305 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
1306 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
1307 /* Grab the NPA LF if required */
1308 rc = otx2_npa_lf_init(pci_dev, dev);
1310 otx2_err("Unable to init NPA lf. It might not be provisioned");
1311 goto otx2_dev_uninit;
1314 dev->drv_inited = true;
1315 dev->is_timeout_deq = 0;
1316 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1317 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1318 dev->max_num_events = -1;
1319 dev->nb_event_queues = 0;
1320 dev->nb_event_ports = 0;
1322 if (!dev->max_event_ports || !dev->max_event_queues) {
1323 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1324 dev->max_event_queues, dev->max_event_ports);
1326 goto otx2_npa_lf_uninit;
1330 sso_parse_devargs(dev, pci_dev->device.devargs);
1332 otx2_sso_dbg("Using dual workslot mode");
1333 dev->max_event_ports = dev->max_event_ports / 2;
1335 otx2_sso_dbg("Using single workslot mode");
1338 otx2_sso_pf_func_set(dev->pf_func);
1339 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1340 event_dev->data->name, dev->max_event_queues,
1341 dev->max_event_ports);
1342 if (dev->selftest) {
1343 event_dev->dev->driver = &pci_sso.driver;
1344 event_dev->dev_ops->dev_selftest();
1347 otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
1354 otx2_dev_fini(pci_dev, dev);
1360 otx2_sso_fini(struct rte_eventdev *event_dev)
1362 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1363 struct rte_pci_device *pci_dev;
1365 /* For secondary processes, nothing to be done */
1366 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1369 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1371 if (!dev->drv_inited)
1374 dev->drv_inited = false;
1378 if (otx2_npa_lf_active(dev)) {
1379 otx2_info("Common resource in use by other devices");
1384 otx2_dev_fini(pci_dev, dev);
1389 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1390 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1391 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1392 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
1393 OTX2_SSO_SINGLE_WS "=1"
1394 OTX2_SSO_GGRP_QOS "=<string>"
1395 OTX2_SSO_SELFTEST "=1");