1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <rte_eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev.h"
18 otx2_sso_info_get(struct rte_eventdev *event_dev,
19 struct rte_event_dev_info *dev_info)
21 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
23 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
24 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
25 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
26 dev_info->max_event_queues = dev->max_event_queues;
27 dev_info->max_event_queue_flows = (1ULL << 20);
28 dev_info->max_event_queue_priority_levels = 8;
29 dev_info->max_event_priority_levels = 1;
30 dev_info->max_event_ports = dev->max_event_ports;
31 dev_info->max_event_port_dequeue_depth = 1;
32 dev_info->max_event_port_enqueue_depth = 1;
33 dev_info->max_num_events = dev->max_num_events;
34 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
35 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
36 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
37 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
38 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
39 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
43 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
44 uint16_t nb_lf, uint8_t attach)
47 struct rsrc_attach_req *req;
49 req = otx2_mbox_alloc_msg_attach_resources(mbox);
61 if (otx2_mbox_process(mbox) < 0)
64 struct rsrc_detach_req *req;
66 req = otx2_mbox_alloc_msg_detach_resources(mbox);
78 if (otx2_mbox_process(mbox) < 0)
86 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
87 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
96 struct sso_lf_alloc_req *req_ggrp;
97 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
98 req_ggrp->hwgrps = nb_lf;
103 struct ssow_lf_alloc_req *req_hws;
104 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
105 req_hws->hws = nb_lf;
115 struct sso_lf_free_req *req_ggrp;
116 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
117 req_ggrp->hwgrps = nb_lf;
122 struct ssow_lf_free_req *req_hws;
123 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
124 req_hws->hws = nb_lf;
132 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
136 if (alloc && type == SSO_LF_GGRP) {
137 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
139 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
140 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
141 dev->iue = rsp_ggrp->in_unit_entries;
148 otx2_sso_port_release(void *port)
154 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
156 RTE_SET_USED(event_dev);
157 RTE_SET_USED(queue_id);
161 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
163 ws->tag_op = base + SSOW_LF_GWS_TAG;
164 ws->wqp_op = base + SSOW_LF_GWS_WQP;
165 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
166 ws->swtp_op = base + SSOW_LF_GWS_SWTP;
167 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
168 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
172 sso_configure_ports(const struct rte_eventdev *event_dev)
174 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
175 struct otx2_mbox *mbox = dev->mbox;
179 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
181 nb_lf = dev->nb_event_ports;
182 /* Ask AF to attach required LFs. */
183 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
185 otx2_err("Failed to attach SSO GWS LF");
189 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
190 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
191 otx2_err("Failed to init SSO GWS LF");
195 for (i = 0; i < nb_lf; i++) {
196 struct otx2_ssogws *ws;
199 /* Free memory prior to re-allocation if needed */
200 if (event_dev->data->ports[i] != NULL) {
201 ws = event_dev->data->ports[i];
206 /* Allocate event port memory */
207 ws = rte_zmalloc_socket("otx2_sso_ws",
208 sizeof(struct otx2_ssogws),
210 event_dev->data->socket_id);
212 otx2_err("Failed to alloc memory for port=%d", i);
218 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
219 sso_set_port_ops(ws, base);
221 event_dev->data->ports[i] = ws;
225 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
226 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
233 sso_configure_queues(const struct rte_eventdev *event_dev)
235 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
236 struct otx2_mbox *mbox = dev->mbox;
240 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
242 nb_lf = dev->nb_event_queues;
243 /* Ask AF to attach required LFs. */
244 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
246 otx2_err("Failed to attach SSO GGRP LF");
250 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
251 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
252 otx2_err("Failed to init SSO GGRP LF");
260 sso_xaq_allocate(struct otx2_sso_evdev *dev)
262 const struct rte_memzone *mz;
263 struct npa_aura_s *aura;
264 static int reconfig_cnt;
265 char pool_name[RTE_MEMZONE_NAMESIZE];
270 rte_mempool_free(dev->xaq_pool);
273 * Allocate memory for Add work backpressure.
275 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
277 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
279 sizeof(struct npa_aura_s),
281 RTE_MEMZONE_IOVA_CONTIG,
284 otx2_err("Failed to allocate mem for fcmem");
288 dev->fc_iova = mz->iova;
289 dev->fc_mem = mz->addr;
291 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
292 memset(aura, 0, sizeof(struct npa_aura_s));
295 aura->fc_addr = dev->fc_iova;
296 aura->fc_hyst_bits = 0; /* Store count on all updates */
298 /* Taken from HRM 14.3.3(4) */
299 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
301 xaq_cnt += dev->xae_cnt / dev->xae_waes;
303 xaq_cnt += (dev->iue / dev->xae_waes) +
304 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
306 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
307 /* Setup XAQ based on number of nb queues. */
308 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
309 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
310 xaq_cnt, dev->xaq_buf_size, 0, 0,
313 if (dev->xaq_pool == NULL) {
314 otx2_err("Unable to create empty mempool.");
315 rte_memzone_free(mz);
319 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
320 rte_mbuf_platform_mempool_ops(), aura);
322 otx2_err("Unable to set xaqpool ops.");
326 rc = rte_mempool_populate_default(dev->xaq_pool);
328 otx2_err("Unable to set populate xaqpool.");
332 /* When SW does addwork (enqueue) check if there is space in XAQ by
333 * comparing fc_addr above against the xaq_lmt calculated below.
334 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
335 * to request XAQ to cache them even before enqueue is called.
337 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
338 dev->nb_event_queues);
339 dev->nb_xaq_cfg = xaq_cnt;
343 rte_mempool_free(dev->xaq_pool);
344 rte_memzone_free(mz);
349 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
351 struct otx2_mbox *mbox = dev->mbox;
352 struct sso_hw_setconfig *req;
354 otx2_sso_dbg("Configuring XAQ for GGRPs");
355 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
356 req->npa_pf_func = otx2_npa_pf_func_get();
357 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
358 req->hwgrps = dev->nb_event_queues;
360 return otx2_mbox_process(mbox);
364 sso_lf_teardown(struct otx2_sso_evdev *dev,
365 enum otx2_sso_lf_type lf_type)
371 nb_lf = dev->nb_event_queues;
374 nb_lf = dev->nb_event_ports;
380 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
381 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
385 otx2_sso_configure(const struct rte_eventdev *event_dev)
387 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
388 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
393 deq_tmo_ns = conf->dequeue_timeout_ns;
396 deq_tmo_ns = dev->min_dequeue_timeout_ns;
398 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
399 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
400 otx2_err("Unsupported dequeue timeout requested");
404 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
405 dev->is_timeout_deq = 1;
407 dev->deq_tmo_ns = deq_tmo_ns;
409 if (conf->nb_event_ports > dev->max_event_ports ||
410 conf->nb_event_queues > dev->max_event_queues) {
411 otx2_err("Unsupported event queues/ports requested");
415 if (conf->nb_event_port_dequeue_depth > 1) {
416 otx2_err("Unsupported event port deq depth requested");
420 if (conf->nb_event_port_enqueue_depth > 1) {
421 otx2_err("Unsupported event port enq depth requested");
425 if (dev->nb_event_queues) {
426 /* Finit any previous queues. */
427 sso_lf_teardown(dev, SSO_LF_GGRP);
429 if (dev->nb_event_ports) {
430 /* Finit any previous ports. */
431 sso_lf_teardown(dev, SSO_LF_GWS);
434 dev->nb_event_queues = conf->nb_event_queues;
435 dev->nb_event_ports = conf->nb_event_ports;
437 if (sso_configure_ports(event_dev)) {
438 otx2_err("Failed to configure event ports");
442 if (sso_configure_queues(event_dev) < 0) {
443 otx2_err("Failed to configure event queues");
448 if (sso_xaq_allocate(dev) < 0) {
450 goto teardown_hwggrp;
453 rc = sso_ggrp_alloc_xaq(dev);
455 otx2_err("Failed to alloc xaq to ggrp %d", rc);
456 goto teardown_hwggrp;
464 sso_lf_teardown(dev, SSO_LF_GGRP);
466 sso_lf_teardown(dev, SSO_LF_GWS);
467 dev->nb_event_queues = 0;
468 dev->nb_event_ports = 0;
474 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
475 struct rte_event_queue_conf *queue_conf)
477 RTE_SET_USED(event_dev);
478 RTE_SET_USED(queue_id);
480 queue_conf->nb_atomic_flows = (1ULL << 20);
481 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
482 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
483 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
487 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
488 const struct rte_event_queue_conf *queue_conf)
490 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
491 struct otx2_mbox *mbox = dev->mbox;
492 struct sso_grp_priority *req;
495 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
497 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
500 req->affinity = 0xFF;
501 /* Normalize <0-255> to <0-7> */
502 req->priority = queue_conf->priority / 32;
504 rc = otx2_mbox_process(mbox);
506 otx2_err("Failed to set priority queue=%d", queue_id);
514 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
515 struct rte_event_port_conf *port_conf)
517 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
519 RTE_SET_USED(port_id);
520 port_conf->new_event_threshold = dev->max_num_events;
521 port_conf->dequeue_depth = 1;
522 port_conf->enqueue_depth = 1;
526 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
527 const struct rte_event_port_conf *port_conf)
529 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
530 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
534 sso_func_trace("Port=%d", port_id);
535 RTE_SET_USED(port_conf);
537 if (event_dev->data->ports[port_id] == NULL) {
538 otx2_err("Invalid port Id %d", port_id);
542 for (q = 0; q < dev->nb_event_queues; q++) {
543 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
544 if (grps_base[q] == 0) {
545 otx2_err("Failed to get grp[%d] base addr", q);
550 /* Set get_work timeout for HWS */
551 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
553 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
554 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
556 rte_memcpy(ws->grps_base, grps_base,
557 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
558 ws->fc_mem = dev->fc_mem;
559 ws->xaq_lmt = dev->xaq_lmt;
560 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
562 otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
567 /* Initialize and register event driver with DPDK Application */
568 static struct rte_eventdev_ops otx2_sso_ops = {
569 .dev_infos_get = otx2_sso_info_get,
570 .dev_configure = otx2_sso_configure,
571 .queue_def_conf = otx2_sso_queue_def_conf,
572 .queue_setup = otx2_sso_queue_setup,
573 .queue_release = otx2_sso_queue_release,
574 .port_def_conf = otx2_sso_port_def_conf,
575 .port_setup = otx2_sso_port_setup,
576 .port_release = otx2_sso_port_release,
579 #define OTX2_SSO_XAE_CNT "xae_cnt"
582 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
584 struct rte_kvargs *kvlist;
588 kvlist = rte_kvargs_parse(devargs->args, NULL);
592 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
595 rte_kvargs_free(kvlist);
599 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
601 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
602 sizeof(struct otx2_sso_evdev),
607 otx2_sso_remove(struct rte_pci_device *pci_dev)
609 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
612 static const struct rte_pci_id pci_sso_map[] = {
614 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
615 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
622 static struct rte_pci_driver pci_sso = {
623 .id_table = pci_sso_map,
624 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
625 .probe = otx2_sso_probe,
626 .remove = otx2_sso_remove,
630 otx2_sso_init(struct rte_eventdev *event_dev)
632 struct free_rsrcs_rsp *rsrc_cnt;
633 struct rte_pci_device *pci_dev;
634 struct otx2_sso_evdev *dev;
637 event_dev->dev_ops = &otx2_sso_ops;
638 /* For secondary processes, the primary has done all the work */
639 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
642 dev = sso_pmd_priv(event_dev);
644 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
646 /* Initialize the base otx2_dev object */
647 rc = otx2_dev_init(pci_dev, dev);
649 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
653 /* Get SSO and SSOW MSIX rsrc cnt */
654 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
655 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
657 otx2_err("Unable to get free rsrc count");
658 goto otx2_dev_uninit;
660 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
661 rsrc_cnt->ssow, rsrc_cnt->npa);
663 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
664 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
665 /* Grab the NPA LF if required */
666 rc = otx2_npa_lf_init(pci_dev, dev);
668 otx2_err("Unable to init NPA lf. It might not be provisioned");
669 goto otx2_dev_uninit;
672 dev->drv_inited = true;
673 dev->is_timeout_deq = 0;
674 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
675 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
676 dev->max_num_events = -1;
677 dev->nb_event_queues = 0;
678 dev->nb_event_ports = 0;
680 if (!dev->max_event_ports || !dev->max_event_queues) {
681 otx2_err("Not enough eventdev resource queues=%d ports=%d",
682 dev->max_event_queues, dev->max_event_ports);
684 goto otx2_npa_lf_uninit;
687 sso_parse_devargs(dev, pci_dev->device.devargs);
689 otx2_sso_pf_func_set(dev->pf_func);
690 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
691 event_dev->data->name, dev->max_event_queues,
692 dev->max_event_ports);
700 otx2_dev_fini(pci_dev, dev);
706 otx2_sso_fini(struct rte_eventdev *event_dev)
708 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
709 struct rte_pci_device *pci_dev;
711 /* For secondary processes, nothing to be done */
712 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
715 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
717 if (!dev->drv_inited)
720 dev->drv_inited = false;
724 if (otx2_npa_lf_active(dev)) {
725 otx2_info("Common resource in use by other devices");
729 otx2_dev_fini(pci_dev, dev);
734 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
735 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
736 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
737 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>");