1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <rte_eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev_stats.h"
16 #include "otx2_evdev.h"
18 #include "otx2_tim_evdev.h"
21 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
23 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
24 uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
25 struct otx2_mbox *mbox = dev->mbox;
26 struct msix_offset_rsp *msix_rsp;
29 /* Get SSO and SSOW MSIX vector offsets */
30 otx2_mbox_alloc_msg_msix_offset(mbox);
31 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
33 for (i = 0; i < nb_ports; i++)
34 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
36 for (i = 0; i < dev->nb_event_queues; i++)
37 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
43 sso_fastpath_fns_set(struct rte_eventdev *event_dev)
45 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
47 const event_dequeue_t ssogws_deq[2][2][2][2][2][2][2] = {
48 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
49 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_ ##name,
50 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
54 const event_dequeue_burst_t ssogws_deq_burst[2][2][2][2][2][2][2] = {
55 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
56 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_burst_ ##name,
57 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
61 const event_dequeue_t ssogws_deq_timeout[2][2][2][2][2][2][2] = {
62 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
63 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_timeout_ ##name,
64 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
68 const event_dequeue_burst_t
69 ssogws_deq_timeout_burst[2][2][2][2][2][2][2] = {
70 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
71 [f6][f5][f4][f3][f2][f1][f0] = \
72 otx2_ssogws_deq_timeout_burst_ ##name,
73 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
77 const event_dequeue_t ssogws_deq_seg[2][2][2][2][2][2][2] = {
78 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
79 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_ ##name,
80 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
84 const event_dequeue_burst_t
85 ssogws_deq_seg_burst[2][2][2][2][2][2][2] = {
86 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
87 [f6][f5][f4][f3][f2][f1][f0] = \
88 otx2_ssogws_deq_seg_burst_ ##name,
89 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
93 const event_dequeue_t ssogws_deq_seg_timeout[2][2][2][2][2][2][2] = {
94 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
95 [f6][f5][f4][f3][f2][f1][f0] = \
96 otx2_ssogws_deq_seg_timeout_ ##name,
97 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
101 const event_dequeue_burst_t
102 ssogws_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
103 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
104 [f6][f5][f4][f3][f2][f1][f0] = \
105 otx2_ssogws_deq_seg_timeout_burst_ ##name,
106 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
112 const event_dequeue_t ssogws_dual_deq[2][2][2][2][2][2][2] = {
113 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
114 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_ ##name,
115 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
119 const event_dequeue_burst_t
120 ssogws_dual_deq_burst[2][2][2][2][2][2][2] = {
121 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
122 [f6][f5][f4][f3][f2][f1][f0] = \
123 otx2_ssogws_dual_deq_burst_ ##name,
124 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
128 const event_dequeue_t ssogws_dual_deq_timeout[2][2][2][2][2][2][2] = {
129 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
130 [f6][f5][f4][f3][f2][f1][f0] = \
131 otx2_ssogws_dual_deq_timeout_ ##name,
132 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
136 const event_dequeue_burst_t
137 ssogws_dual_deq_timeout_burst[2][2][2][2][2][2][2] = {
138 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
139 [f6][f5][f4][f3][f2][f1][f0] = \
140 otx2_ssogws_dual_deq_timeout_burst_ ##name,
141 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
145 const event_dequeue_t ssogws_dual_deq_seg[2][2][2][2][2][2][2] = {
146 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
147 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_seg_ ##name,
148 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
152 const event_dequeue_burst_t
153 ssogws_dual_deq_seg_burst[2][2][2][2][2][2][2] = {
154 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
155 [f6][f5][f4][f3][f2][f1][f0] = \
156 otx2_ssogws_dual_deq_seg_burst_ ##name,
157 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
161 const event_dequeue_t
162 ssogws_dual_deq_seg_timeout[2][2][2][2][2][2][2] = {
163 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
164 [f6][f5][f4][f3][f2][f1][f0] = \
165 otx2_ssogws_dual_deq_seg_timeout_ ##name,
166 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
170 const event_dequeue_burst_t
171 ssogws_dual_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
172 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
173 [f6][f5][f4][f3][f2][f1][f0] = \
174 otx2_ssogws_dual_deq_seg_timeout_burst_ ##name,
175 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
180 const event_tx_adapter_enqueue
181 ssogws_tx_adptr_enq[2][2][2][2][2][2][2] = {
182 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
183 [f6][f5][f4][f3][f2][f1][f0] = \
184 otx2_ssogws_tx_adptr_enq_ ## name,
185 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
189 const event_tx_adapter_enqueue
190 ssogws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
191 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
192 [f6][f5][f4][f3][f2][f1][f0] = \
193 otx2_ssogws_tx_adptr_enq_seg_ ## name,
194 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
198 const event_tx_adapter_enqueue
199 ssogws_dual_tx_adptr_enq[2][2][2][2][2][2][2] = {
200 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
201 [f6][f5][f4][f3][f2][f1][f0] = \
202 otx2_ssogws_dual_tx_adptr_enq_ ## name,
203 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
207 const event_tx_adapter_enqueue
208 ssogws_dual_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
209 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
210 [f6][f5][f4][f3][f2][f1][f0] = \
211 otx2_ssogws_dual_tx_adptr_enq_seg_ ## name,
212 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
216 event_dev->enqueue = otx2_ssogws_enq;
217 event_dev->enqueue_burst = otx2_ssogws_enq_burst;
218 event_dev->enqueue_new_burst = otx2_ssogws_enq_new_burst;
219 event_dev->enqueue_forward_burst = otx2_ssogws_enq_fwd_burst;
220 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
221 event_dev->dequeue = ssogws_deq_seg
222 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
223 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
224 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
225 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
226 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
227 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
228 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
229 event_dev->dequeue_burst = ssogws_deq_seg_burst
230 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
231 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
232 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
233 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
234 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
235 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
236 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
237 if (dev->is_timeout_deq) {
238 event_dev->dequeue = ssogws_deq_seg_timeout
239 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
240 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
241 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
242 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
243 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
244 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
245 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
246 event_dev->dequeue_burst =
247 ssogws_deq_seg_timeout_burst
248 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
249 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
250 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
251 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
252 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
253 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
254 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
257 event_dev->dequeue = ssogws_deq
258 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
259 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
260 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
261 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
262 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
263 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
264 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
265 event_dev->dequeue_burst = ssogws_deq_burst
266 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
267 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
268 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
269 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
270 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
271 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
272 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
273 if (dev->is_timeout_deq) {
274 event_dev->dequeue = ssogws_deq_timeout
275 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
276 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
277 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
278 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
279 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
280 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
281 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
282 event_dev->dequeue_burst =
283 ssogws_deq_timeout_burst
284 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
285 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
286 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
287 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
288 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
289 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
290 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
294 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
295 /* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
296 event_dev->txa_enqueue = ssogws_tx_adptr_enq_seg
297 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]
298 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
299 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
300 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
301 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
302 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
303 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
305 event_dev->txa_enqueue = ssogws_tx_adptr_enq
306 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]
307 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
308 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
309 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
310 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
311 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
312 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
316 event_dev->enqueue = otx2_ssogws_dual_enq;
317 event_dev->enqueue_burst = otx2_ssogws_dual_enq_burst;
318 event_dev->enqueue_new_burst =
319 otx2_ssogws_dual_enq_new_burst;
320 event_dev->enqueue_forward_burst =
321 otx2_ssogws_dual_enq_fwd_burst;
323 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
324 event_dev->dequeue = ssogws_dual_deq_seg
325 [!!(dev->rx_offloads &
326 NIX_RX_OFFLOAD_SECURITY_F)]
327 [!!(dev->rx_offloads &
328 NIX_RX_OFFLOAD_TSTAMP_F)]
329 [!!(dev->rx_offloads &
330 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
331 [!!(dev->rx_offloads &
332 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
333 [!!(dev->rx_offloads &
334 NIX_RX_OFFLOAD_CHECKSUM_F)]
335 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
336 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
337 event_dev->dequeue_burst = ssogws_dual_deq_seg_burst
338 [!!(dev->rx_offloads &
339 NIX_RX_OFFLOAD_SECURITY_F)]
340 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
341 [!!(dev->rx_offloads &
342 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
343 [!!(dev->rx_offloads &
344 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
345 [!!(dev->rx_offloads &
346 NIX_RX_OFFLOAD_CHECKSUM_F)]
347 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
348 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
349 if (dev->is_timeout_deq) {
351 ssogws_dual_deq_seg_timeout
352 [!!(dev->rx_offloads &
353 NIX_RX_OFFLOAD_SECURITY_F)]
354 [!!(dev->rx_offloads &
355 NIX_RX_OFFLOAD_TSTAMP_F)]
356 [!!(dev->rx_offloads &
357 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
358 [!!(dev->rx_offloads &
359 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
360 [!!(dev->rx_offloads &
361 NIX_RX_OFFLOAD_CHECKSUM_F)]
362 [!!(dev->rx_offloads &
363 NIX_RX_OFFLOAD_PTYPE_F)]
364 [!!(dev->rx_offloads &
365 NIX_RX_OFFLOAD_RSS_F)];
366 event_dev->dequeue_burst =
367 ssogws_dual_deq_seg_timeout_burst
368 [!!(dev->rx_offloads &
369 NIX_RX_OFFLOAD_SECURITY_F)]
370 [!!(dev->rx_offloads &
371 NIX_RX_OFFLOAD_TSTAMP_F)]
372 [!!(dev->rx_offloads &
373 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
374 [!!(dev->rx_offloads &
375 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
376 [!!(dev->rx_offloads &
377 NIX_RX_OFFLOAD_CHECKSUM_F)]
378 [!!(dev->rx_offloads &
379 NIX_RX_OFFLOAD_PTYPE_F)]
380 [!!(dev->rx_offloads &
381 NIX_RX_OFFLOAD_RSS_F)];
384 event_dev->dequeue = ssogws_dual_deq
385 [!!(dev->rx_offloads &
386 NIX_RX_OFFLOAD_SECURITY_F)]
387 [!!(dev->rx_offloads &
388 NIX_RX_OFFLOAD_TSTAMP_F)]
389 [!!(dev->rx_offloads &
390 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
391 [!!(dev->rx_offloads &
392 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
393 [!!(dev->rx_offloads &
394 NIX_RX_OFFLOAD_CHECKSUM_F)]
395 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
396 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
397 event_dev->dequeue_burst = ssogws_dual_deq_burst
398 [!!(dev->rx_offloads &
399 NIX_RX_OFFLOAD_SECURITY_F)]
400 [!!(dev->rx_offloads &
401 NIX_RX_OFFLOAD_TSTAMP_F)]
402 [!!(dev->rx_offloads &
403 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
404 [!!(dev->rx_offloads &
405 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
406 [!!(dev->rx_offloads &
407 NIX_RX_OFFLOAD_CHECKSUM_F)]
408 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
409 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
410 if (dev->is_timeout_deq) {
412 ssogws_dual_deq_timeout
413 [!!(dev->rx_offloads &
414 NIX_RX_OFFLOAD_SECURITY_F)]
415 [!!(dev->rx_offloads &
416 NIX_RX_OFFLOAD_TSTAMP_F)]
417 [!!(dev->rx_offloads &
418 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
419 [!!(dev->rx_offloads &
420 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
421 [!!(dev->rx_offloads &
422 NIX_RX_OFFLOAD_CHECKSUM_F)]
423 [!!(dev->rx_offloads &
424 NIX_RX_OFFLOAD_PTYPE_F)]
425 [!!(dev->rx_offloads &
426 NIX_RX_OFFLOAD_RSS_F)];
427 event_dev->dequeue_burst =
428 ssogws_dual_deq_timeout_burst
429 [!!(dev->rx_offloads &
430 NIX_RX_OFFLOAD_SECURITY_F)]
431 [!!(dev->rx_offloads &
432 NIX_RX_OFFLOAD_TSTAMP_F)]
433 [!!(dev->rx_offloads &
434 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
435 [!!(dev->rx_offloads &
436 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
437 [!!(dev->rx_offloads &
438 NIX_RX_OFFLOAD_CHECKSUM_F)]
439 [!!(dev->rx_offloads &
440 NIX_RX_OFFLOAD_PTYPE_F)]
441 [!!(dev->rx_offloads &
442 NIX_RX_OFFLOAD_RSS_F)];
446 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
447 /* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
448 event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq_seg
449 [!!(dev->tx_offloads &
450 NIX_TX_OFFLOAD_SECURITY_F)]
451 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
452 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
453 [!!(dev->tx_offloads &
454 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
455 [!!(dev->tx_offloads &
456 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
457 [!!(dev->tx_offloads &
458 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
459 [!!(dev->tx_offloads &
460 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
462 event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq
463 [!!(dev->tx_offloads &
464 NIX_TX_OFFLOAD_SECURITY_F)]
465 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
466 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
467 [!!(dev->tx_offloads &
468 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
469 [!!(dev->tx_offloads &
470 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
471 [!!(dev->tx_offloads &
472 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
473 [!!(dev->tx_offloads &
474 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
478 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
483 otx2_sso_info_get(struct rte_eventdev *event_dev,
484 struct rte_event_dev_info *dev_info)
486 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
488 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
489 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
490 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
491 dev_info->max_event_queues = dev->max_event_queues;
492 dev_info->max_event_queue_flows = (1ULL << 20);
493 dev_info->max_event_queue_priority_levels = 8;
494 dev_info->max_event_priority_levels = 1;
495 dev_info->max_event_ports = dev->max_event_ports;
496 dev_info->max_event_port_dequeue_depth = 1;
497 dev_info->max_event_port_enqueue_depth = 1;
498 dev_info->max_num_events = dev->max_num_events;
499 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
500 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
501 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
502 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
503 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
504 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
508 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
510 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
514 val |= 0ULL << 12; /* SET 0 */
515 val |= 0x8000800080000000; /* Dont modify rest of the masks */
516 val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */
518 otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
522 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
523 const uint8_t queues[], const uint8_t priorities[],
526 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
530 RTE_SET_USED(priorities);
531 for (link = 0; link < nb_links; link++) {
533 struct otx2_ssogws_dual *ws = port;
536 sso_port_link_modify((struct otx2_ssogws *)
537 &ws->ws_state[0], queues[link], true);
538 sso_port_link_modify((struct otx2_ssogws *)
539 &ws->ws_state[1], queues[link], true);
541 struct otx2_ssogws *ws = port;
544 sso_port_link_modify(ws, queues[link], true);
547 sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
549 return (int)nb_links;
553 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
554 uint8_t queues[], uint16_t nb_unlinks)
556 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
560 for (unlink = 0; unlink < nb_unlinks; unlink++) {
562 struct otx2_ssogws_dual *ws = port;
565 sso_port_link_modify((struct otx2_ssogws *)
566 &ws->ws_state[0], queues[unlink],
568 sso_port_link_modify((struct otx2_ssogws *)
569 &ws->ws_state[1], queues[unlink],
572 struct otx2_ssogws *ws = port;
575 sso_port_link_modify(ws, queues[unlink], false);
578 sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
580 return (int)nb_unlinks;
584 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
585 uint16_t nb_lf, uint8_t attach)
588 struct rsrc_attach_req *req;
590 req = otx2_mbox_alloc_msg_attach_resources(mbox);
602 if (otx2_mbox_process(mbox) < 0)
605 struct rsrc_detach_req *req;
607 req = otx2_mbox_alloc_msg_detach_resources(mbox);
619 if (otx2_mbox_process(mbox) < 0)
627 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
628 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
637 struct sso_lf_alloc_req *req_ggrp;
638 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
639 req_ggrp->hwgrps = nb_lf;
644 struct ssow_lf_alloc_req *req_hws;
645 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
646 req_hws->hws = nb_lf;
656 struct sso_lf_free_req *req_ggrp;
657 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
658 req_ggrp->hwgrps = nb_lf;
663 struct ssow_lf_free_req *req_hws;
664 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
665 req_hws->hws = nb_lf;
673 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
677 if (alloc && type == SSO_LF_GGRP) {
678 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
680 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
681 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
682 dev->iue = rsp_ggrp->in_unit_entries;
689 otx2_sso_port_release(void *port)
695 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
697 RTE_SET_USED(event_dev);
698 RTE_SET_USED(queue_id);
702 sso_clr_links(const struct rte_eventdev *event_dev)
704 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
707 for (i = 0; i < dev->nb_event_ports; i++) {
709 struct otx2_ssogws_dual *ws;
711 ws = event_dev->data->ports[i];
712 for (j = 0; j < dev->nb_event_queues; j++) {
713 sso_port_link_modify((struct otx2_ssogws *)
714 &ws->ws_state[0], j, false);
715 sso_port_link_modify((struct otx2_ssogws *)
716 &ws->ws_state[1], j, false);
719 struct otx2_ssogws *ws;
721 ws = event_dev->data->ports[i];
722 for (j = 0; j < dev->nb_event_queues; j++)
723 sso_port_link_modify(ws, j, false);
729 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
731 ws->tag_op = base + SSOW_LF_GWS_TAG;
732 ws->wqp_op = base + SSOW_LF_GWS_WQP;
733 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
734 ws->swtp_op = base + SSOW_LF_GWS_SWTP;
735 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
736 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
740 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
742 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
743 struct otx2_mbox *mbox = dev->mbox;
748 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
750 nb_lf = dev->nb_event_ports * 2;
751 /* Ask AF to attach required LFs. */
752 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
754 otx2_err("Failed to attach SSO GWS LF");
758 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
759 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
760 otx2_err("Failed to init SSO GWS LF");
764 for (i = 0; i < dev->nb_event_ports; i++) {
765 struct otx2_ssogws_dual *ws;
768 /* Free memory prior to re-allocation if needed */
769 if (event_dev->data->ports[i] != NULL) {
770 ws = event_dev->data->ports[i];
775 /* Allocate event port memory */
776 ws = rte_zmalloc_socket("otx2_sso_ws",
777 sizeof(struct otx2_ssogws_dual),
779 event_dev->data->socket_id);
781 otx2_err("Failed to alloc memory for port=%d", i);
787 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
788 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
791 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
792 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
795 event_dev->data->ports[i] = ws;
799 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
800 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
807 sso_configure_ports(const struct rte_eventdev *event_dev)
809 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
810 struct otx2_mbox *mbox = dev->mbox;
814 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
816 nb_lf = dev->nb_event_ports;
817 /* Ask AF to attach required LFs. */
818 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
820 otx2_err("Failed to attach SSO GWS LF");
824 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
825 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
826 otx2_err("Failed to init SSO GWS LF");
830 for (i = 0; i < nb_lf; i++) {
831 struct otx2_ssogws *ws;
834 /* Free memory prior to re-allocation if needed */
835 if (event_dev->data->ports[i] != NULL) {
836 ws = event_dev->data->ports[i];
841 /* Allocate event port memory */
842 ws = rte_zmalloc_socket("otx2_sso_ws",
843 sizeof(struct otx2_ssogws),
845 event_dev->data->socket_id);
847 otx2_err("Failed to alloc memory for port=%d", i);
853 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
854 sso_set_port_ops(ws, base);
856 event_dev->data->ports[i] = ws;
860 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
861 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
868 sso_configure_queues(const struct rte_eventdev *event_dev)
870 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
871 struct otx2_mbox *mbox = dev->mbox;
875 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
877 nb_lf = dev->nb_event_queues;
878 /* Ask AF to attach required LFs. */
879 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
881 otx2_err("Failed to attach SSO GGRP LF");
885 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
886 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
887 otx2_err("Failed to init SSO GGRP LF");
895 sso_xaq_allocate(struct otx2_sso_evdev *dev)
897 const struct rte_memzone *mz;
898 struct npa_aura_s *aura;
899 static int reconfig_cnt;
900 char pool_name[RTE_MEMZONE_NAMESIZE];
905 rte_mempool_free(dev->xaq_pool);
908 * Allocate memory for Add work backpressure.
910 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
912 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
914 sizeof(struct npa_aura_s),
916 RTE_MEMZONE_IOVA_CONTIG,
919 otx2_err("Failed to allocate mem for fcmem");
923 dev->fc_iova = mz->iova;
924 dev->fc_mem = mz->addr;
926 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
927 memset(aura, 0, sizeof(struct npa_aura_s));
930 aura->fc_addr = dev->fc_iova;
931 aura->fc_hyst_bits = 0; /* Store count on all updates */
933 /* Taken from HRM 14.3.3(4) */
934 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
936 xaq_cnt += dev->xae_cnt / dev->xae_waes;
937 else if (dev->adptr_xae_cnt)
938 xaq_cnt += (dev->adptr_xae_cnt / dev->xae_waes) +
939 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
941 xaq_cnt += (dev->iue / dev->xae_waes) +
942 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
944 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
945 /* Setup XAQ based on number of nb queues. */
946 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
947 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
948 xaq_cnt, dev->xaq_buf_size, 0, 0,
951 if (dev->xaq_pool == NULL) {
952 otx2_err("Unable to create empty mempool.");
953 rte_memzone_free(mz);
957 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
958 rte_mbuf_platform_mempool_ops(), aura);
960 otx2_err("Unable to set xaqpool ops.");
964 rc = rte_mempool_populate_default(dev->xaq_pool);
966 otx2_err("Unable to set populate xaqpool.");
970 /* When SW does addwork (enqueue) check if there is space in XAQ by
971 * comparing fc_addr above against the xaq_lmt calculated below.
972 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
973 * to request XAQ to cache them even before enqueue is called.
975 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
976 dev->nb_event_queues);
977 dev->nb_xaq_cfg = xaq_cnt;
981 rte_mempool_free(dev->xaq_pool);
982 rte_memzone_free(mz);
987 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
989 struct otx2_mbox *mbox = dev->mbox;
990 struct sso_hw_setconfig *req;
992 otx2_sso_dbg("Configuring XAQ for GGRPs");
993 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
994 req->npa_pf_func = otx2_npa_pf_func_get();
995 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
996 req->hwgrps = dev->nb_event_queues;
998 return otx2_mbox_process(mbox);
1002 sso_lf_teardown(struct otx2_sso_evdev *dev,
1003 enum otx2_sso_lf_type lf_type)
1009 nb_lf = dev->nb_event_queues;
1012 nb_lf = dev->nb_event_ports;
1013 nb_lf *= dev->dual_ws ? 2 : 1;
1019 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
1020 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
1024 otx2_sso_configure(const struct rte_eventdev *event_dev)
1026 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
1027 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1028 uint32_t deq_tmo_ns;
1032 deq_tmo_ns = conf->dequeue_timeout_ns;
1034 if (deq_tmo_ns == 0)
1035 deq_tmo_ns = dev->min_dequeue_timeout_ns;
1037 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
1038 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
1039 otx2_err("Unsupported dequeue timeout requested");
1043 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
1044 dev->is_timeout_deq = 1;
1046 dev->deq_tmo_ns = deq_tmo_ns;
1048 if (conf->nb_event_ports > dev->max_event_ports ||
1049 conf->nb_event_queues > dev->max_event_queues) {
1050 otx2_err("Unsupported event queues/ports requested");
1054 if (conf->nb_event_port_dequeue_depth > 1) {
1055 otx2_err("Unsupported event port deq depth requested");
1059 if (conf->nb_event_port_enqueue_depth > 1) {
1060 otx2_err("Unsupported event port enq depth requested");
1064 if (dev->configured)
1065 sso_unregister_irqs(event_dev);
1067 if (dev->nb_event_queues) {
1068 /* Finit any previous queues. */
1069 sso_lf_teardown(dev, SSO_LF_GGRP);
1071 if (dev->nb_event_ports) {
1072 /* Finit any previous ports. */
1073 sso_lf_teardown(dev, SSO_LF_GWS);
1076 dev->nb_event_queues = conf->nb_event_queues;
1077 dev->nb_event_ports = conf->nb_event_ports;
1080 rc = sso_configure_dual_ports(event_dev);
1082 rc = sso_configure_ports(event_dev);
1085 otx2_err("Failed to configure event ports");
1089 if (sso_configure_queues(event_dev) < 0) {
1090 otx2_err("Failed to configure event queues");
1095 if (sso_xaq_allocate(dev) < 0) {
1097 goto teardown_hwggrp;
1100 /* Clear any prior port-queue mapping. */
1101 sso_clr_links(event_dev);
1102 rc = sso_ggrp_alloc_xaq(dev);
1104 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1105 goto teardown_hwggrp;
1108 rc = sso_get_msix_offsets(event_dev);
1110 otx2_err("Failed to get msix offsets %d", rc);
1111 goto teardown_hwggrp;
1114 rc = sso_register_irqs(event_dev);
1116 otx2_err("Failed to register irq %d", rc);
1117 goto teardown_hwggrp;
1120 dev->configured = 1;
1125 sso_lf_teardown(dev, SSO_LF_GGRP);
1127 sso_lf_teardown(dev, SSO_LF_GWS);
1128 dev->nb_event_queues = 0;
1129 dev->nb_event_ports = 0;
1130 dev->configured = 0;
1135 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
1136 struct rte_event_queue_conf *queue_conf)
1138 RTE_SET_USED(event_dev);
1139 RTE_SET_USED(queue_id);
1141 queue_conf->nb_atomic_flows = (1ULL << 20);
1142 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
1143 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
1144 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
1148 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
1149 const struct rte_event_queue_conf *queue_conf)
1151 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1152 struct otx2_mbox *mbox = dev->mbox;
1153 struct sso_grp_priority *req;
1156 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
1158 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
1159 req->grp = queue_id;
1161 req->affinity = 0xFF;
1162 /* Normalize <0-255> to <0-7> */
1163 req->priority = queue_conf->priority / 32;
1165 rc = otx2_mbox_process(mbox);
1167 otx2_err("Failed to set priority queue=%d", queue_id);
1175 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
1176 struct rte_event_port_conf *port_conf)
1178 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1180 RTE_SET_USED(port_id);
1181 port_conf->new_event_threshold = dev->max_num_events;
1182 port_conf->dequeue_depth = 1;
1183 port_conf->enqueue_depth = 1;
1187 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
1188 const struct rte_event_port_conf *port_conf)
1190 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1191 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
1195 sso_func_trace("Port=%d", port_id);
1196 RTE_SET_USED(port_conf);
1198 if (event_dev->data->ports[port_id] == NULL) {
1199 otx2_err("Invalid port Id %d", port_id);
1203 for (q = 0; q < dev->nb_event_queues; q++) {
1204 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
1205 if (grps_base[q] == 0) {
1206 otx2_err("Failed to get grp[%d] base addr", q);
1211 /* Set get_work timeout for HWS */
1212 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
1215 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
1217 rte_memcpy(ws->grps_base, grps_base,
1218 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1219 ws->fc_mem = dev->fc_mem;
1220 ws->xaq_lmt = dev->xaq_lmt;
1221 ws->tstamp = dev->tstamp;
1222 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1223 ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1224 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1225 ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1227 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
1228 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1230 rte_memcpy(ws->grps_base, grps_base,
1231 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1232 ws->fc_mem = dev->fc_mem;
1233 ws->xaq_lmt = dev->xaq_lmt;
1234 ws->tstamp = dev->tstamp;
1235 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
1238 otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
1244 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
1245 uint64_t *tmo_ticks)
1247 RTE_SET_USED(event_dev);
1248 *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
1254 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
1256 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1258 fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base);
1259 fprintf(f, "SSOW_LF_GWS_LINKS 0x%" PRIx64 "\n",
1260 otx2_read64(base + SSOW_LF_GWS_LINKS));
1261 fprintf(f, "SSOW_LF_GWS_PENDWQP 0x%" PRIx64 "\n",
1262 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
1263 fprintf(f, "SSOW_LF_GWS_PENDSTATE 0x%" PRIx64 "\n",
1264 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
1265 fprintf(f, "SSOW_LF_GWS_NW_TIM 0x%" PRIx64 "\n",
1266 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
1267 fprintf(f, "SSOW_LF_GWS_TAG 0x%" PRIx64 "\n",
1268 otx2_read64(base + SSOW_LF_GWS_TAG));
1269 fprintf(f, "SSOW_LF_GWS_WQP 0x%" PRIx64 "\n",
1270 otx2_read64(base + SSOW_LF_GWS_TAG));
1271 fprintf(f, "SSOW_LF_GWS_SWTP 0x%" PRIx64 "\n",
1272 otx2_read64(base + SSOW_LF_GWS_SWTP));
1273 fprintf(f, "SSOW_LF_GWS_PENDTAG 0x%" PRIx64 "\n",
1274 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
1278 ssoggrp_dump(uintptr_t base, FILE *f)
1280 fprintf(f, "SSO_LF_GGRP Base addr 0x%" PRIx64 "\n", (uint64_t)base);
1281 fprintf(f, "SSO_LF_GGRP_QCTL 0x%" PRIx64 "\n",
1282 otx2_read64(base + SSO_LF_GGRP_QCTL));
1283 fprintf(f, "SSO_LF_GGRP_XAQ_CNT 0x%" PRIx64 "\n",
1284 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
1285 fprintf(f, "SSO_LF_GGRP_INT_THR 0x%" PRIx64 "\n",
1286 otx2_read64(base + SSO_LF_GGRP_INT_THR));
1287 fprintf(f, "SSO_LF_GGRP_INT_CNT 0x%" PRIX64 "\n",
1288 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
1289 fprintf(f, "SSO_LF_GGRP_AQ_CNT 0x%" PRIX64 "\n",
1290 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
1291 fprintf(f, "SSO_LF_GGRP_AQ_THR 0x%" PRIX64 "\n",
1292 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
1293 fprintf(f, "SSO_LF_GGRP_MISC_CNT 0x%" PRIx64 "\n",
1294 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
1298 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
1300 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1304 fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
1305 "dual_ws" : "single_ws");
1306 /* Dump SSOW registers */
1307 for (port = 0; port < dev->nb_event_ports; port++) {
1309 struct otx2_ssogws_dual *ws =
1310 event_dev->data->ports[port];
1312 fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
1314 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
1315 fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
1317 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
1319 fprintf(f, "[%s]SSO single workslot[%d] dump\n",
1321 ssogws_dump(event_dev->data->ports[port], f);
1325 /* Dump SSO registers */
1326 for (queue = 0; queue < dev->nb_event_queues; queue++) {
1327 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
1329 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1330 ssoggrp_dump(ws->grps_base[queue], f);
1332 struct otx2_ssogws *ws = event_dev->data->ports[0];
1333 ssoggrp_dump(ws->grps_base[queue], f);
1339 otx2_handle_event(void *arg, struct rte_event event)
1341 struct rte_eventdev *event_dev = arg;
1343 if (event_dev->dev_ops->dev_stop_flush != NULL)
1344 event_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,
1345 event, event_dev->data->dev_stop_flush_arg);
1349 sso_qos_cfg(struct rte_eventdev *event_dev)
1351 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1352 struct sso_grp_qos_cfg *req;
1355 for (i = 0; i < dev->qos_queue_cnt; i++) {
1356 uint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
1357 uint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
1358 uint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
1360 if (dev->qos_parse_data[i].queue >= dev->nb_event_queues)
1363 req = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);
1364 req->xaq_limit = (dev->nb_xaq_cfg *
1365 (xaq_prcnt ? xaq_prcnt : 100)) / 100;
1366 req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *
1367 (iaq_prcnt ? iaq_prcnt : 100)) / 100;
1368 req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *
1369 (taq_prcnt ? taq_prcnt : 100)) / 100;
1372 if (dev->qos_queue_cnt)
1373 otx2_mbox_process(dev->mbox);
1377 sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
1379 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1382 for (i = 0; i < dev->nb_event_ports; i++) {
1384 struct otx2_ssogws_dual *ws;
1386 ws = event_dev->data->ports[i];
1387 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);
1388 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
1391 ws->ws_state[0].cur_grp = 0;
1392 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1393 ws->ws_state[1].cur_grp = 0;
1394 ws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;
1396 struct otx2_ssogws *ws;
1398 ws = event_dev->data->ports[i];
1402 ws->cur_tt = SSO_SYNC_EMPTY;
1408 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1409 struct otx2_ssogws temp_ws;
1411 memcpy(&temp_ws, &ws->ws_state[0],
1412 sizeof(struct otx2_ssogws_state));
1413 for (i = 0; i < dev->nb_event_queues; i++) {
1414 /* Consume all the events through HWS0 */
1415 ssogws_flush_events(&temp_ws, i, ws->grps_base[i],
1416 otx2_handle_event, event_dev);
1417 /* Enable/Disable SSO GGRP */
1418 otx2_write64(enable, ws->grps_base[i] +
1421 ws->ws_state[0].cur_grp = 0;
1422 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1424 struct otx2_ssogws *ws = event_dev->data->ports[0];
1426 for (i = 0; i < dev->nb_event_queues; i++) {
1427 /* Consume all the events through HWS0 */
1428 ssogws_flush_events(ws, i, ws->grps_base[i],
1429 otx2_handle_event, event_dev);
1430 /* Enable/Disable SSO GGRP */
1431 otx2_write64(enable, ws->grps_base[i] +
1435 ws->cur_tt = SSO_SYNC_EMPTY;
1438 /* reset SSO GWS cache */
1439 otx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);
1440 otx2_mbox_process(dev->mbox);
1444 sso_xae_reconfigure(struct rte_eventdev *event_dev)
1446 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1447 struct rte_mempool *prev_xaq_pool;
1450 if (event_dev->data->dev_started)
1451 sso_cleanup(event_dev, 0);
1453 prev_xaq_pool = dev->xaq_pool;
1454 dev->xaq_pool = NULL;
1455 rc = sso_xaq_allocate(dev);
1457 otx2_err("Failed to alloc xaq pool %d", rc);
1458 rte_mempool_free(prev_xaq_pool);
1461 rc = sso_ggrp_alloc_xaq(dev);
1463 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1464 rte_mempool_free(prev_xaq_pool);
1468 rte_mempool_free(prev_xaq_pool);
1470 if (event_dev->data->dev_started)
1471 sso_cleanup(event_dev, 1);
1477 otx2_sso_start(struct rte_eventdev *event_dev)
1480 sso_qos_cfg(event_dev);
1481 sso_cleanup(event_dev, 1);
1482 sso_fastpath_fns_set(event_dev);
1488 otx2_sso_stop(struct rte_eventdev *event_dev)
1491 sso_cleanup(event_dev, 0);
1496 otx2_sso_close(struct rte_eventdev *event_dev)
1498 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1499 uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
1502 if (!dev->configured)
1505 sso_unregister_irqs(event_dev);
1507 for (i = 0; i < dev->nb_event_queues; i++)
1510 for (i = 0; i < dev->nb_event_ports; i++)
1511 otx2_sso_port_unlink(event_dev, event_dev->data->ports[i],
1512 all_queues, dev->nb_event_queues);
1514 sso_lf_teardown(dev, SSO_LF_GGRP);
1515 sso_lf_teardown(dev, SSO_LF_GWS);
1516 dev->nb_event_ports = 0;
1517 dev->nb_event_queues = 0;
1518 rte_mempool_free(dev->xaq_pool);
1519 rte_memzone_free(rte_memzone_lookup(OTX2_SSO_FC_NAME));
1524 /* Initialize and register event driver with DPDK Application */
1525 static struct rte_eventdev_ops otx2_sso_ops = {
1526 .dev_infos_get = otx2_sso_info_get,
1527 .dev_configure = otx2_sso_configure,
1528 .queue_def_conf = otx2_sso_queue_def_conf,
1529 .queue_setup = otx2_sso_queue_setup,
1530 .queue_release = otx2_sso_queue_release,
1531 .port_def_conf = otx2_sso_port_def_conf,
1532 .port_setup = otx2_sso_port_setup,
1533 .port_release = otx2_sso_port_release,
1534 .port_link = otx2_sso_port_link,
1535 .port_unlink = otx2_sso_port_unlink,
1536 .timeout_ticks = otx2_sso_timeout_ticks,
1538 .eth_rx_adapter_caps_get = otx2_sso_rx_adapter_caps_get,
1539 .eth_rx_adapter_queue_add = otx2_sso_rx_adapter_queue_add,
1540 .eth_rx_adapter_queue_del = otx2_sso_rx_adapter_queue_del,
1541 .eth_rx_adapter_start = otx2_sso_rx_adapter_start,
1542 .eth_rx_adapter_stop = otx2_sso_rx_adapter_stop,
1544 .eth_tx_adapter_caps_get = otx2_sso_tx_adapter_caps_get,
1545 .eth_tx_adapter_queue_add = otx2_sso_tx_adapter_queue_add,
1546 .eth_tx_adapter_queue_del = otx2_sso_tx_adapter_queue_del,
1548 .timer_adapter_caps_get = otx2_tim_caps_get,
1550 .xstats_get = otx2_sso_xstats_get,
1551 .xstats_reset = otx2_sso_xstats_reset,
1552 .xstats_get_names = otx2_sso_xstats_get_names,
1554 .dump = otx2_sso_dump,
1555 .dev_start = otx2_sso_start,
1556 .dev_stop = otx2_sso_stop,
1557 .dev_close = otx2_sso_close,
1558 .dev_selftest = otx2_sso_selftest,
1561 #define OTX2_SSO_XAE_CNT "xae_cnt"
1562 #define OTX2_SSO_SINGLE_WS "single_ws"
1563 #define OTX2_SSO_GGRP_QOS "qos"
1564 #define OTX2_SSO_SELFTEST "selftest"
1567 parse_queue_param(char *value, void *opaque)
1569 struct otx2_sso_qos queue_qos = {0};
1570 uint8_t *val = (uint8_t *)&queue_qos;
1571 struct otx2_sso_evdev *dev = opaque;
1572 char *tok = strtok(value, "-");
1573 struct otx2_sso_qos *old_ptr;
1578 while (tok != NULL) {
1580 tok = strtok(NULL, "-");
1584 if (val != (&queue_qos.iaq_prcnt + 1)) {
1585 otx2_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
1589 dev->qos_queue_cnt++;
1590 old_ptr = dev->qos_parse_data;
1591 dev->qos_parse_data = rte_realloc(dev->qos_parse_data,
1592 sizeof(struct otx2_sso_qos) *
1593 dev->qos_queue_cnt, 0);
1594 if (dev->qos_parse_data == NULL) {
1595 dev->qos_parse_data = old_ptr;
1596 dev->qos_queue_cnt--;
1599 dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
1603 parse_qos_list(const char *value, void *opaque)
1605 char *s = strdup(value);
1616 if (start && start < end) {
1618 parse_queue_param(start + 1, opaque);
1629 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
1633 /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
1634 * isn't allowed. Everything is expressed in percentages, 0 represents
1637 parse_qos_list(value, opaque);
1643 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
1645 struct rte_kvargs *kvlist;
1646 uint8_t single_ws = 0;
1648 if (devargs == NULL)
1650 kvlist = rte_kvargs_parse(devargs->args, NULL);
1654 rte_kvargs_process(kvlist, OTX2_SSO_SELFTEST, &parse_kvargs_flag,
1656 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
1658 rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
1660 rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
1663 dev->dual_ws = !single_ws;
1664 rte_kvargs_free(kvlist);
1668 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1670 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1671 sizeof(struct otx2_sso_evdev),
1676 otx2_sso_remove(struct rte_pci_device *pci_dev)
1678 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
1681 static const struct rte_pci_id pci_sso_map[] = {
1683 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1684 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
1691 static struct rte_pci_driver pci_sso = {
1692 .id_table = pci_sso_map,
1693 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1694 .probe = otx2_sso_probe,
1695 .remove = otx2_sso_remove,
1699 otx2_sso_init(struct rte_eventdev *event_dev)
1701 struct free_rsrcs_rsp *rsrc_cnt;
1702 struct rte_pci_device *pci_dev;
1703 struct otx2_sso_evdev *dev;
1706 event_dev->dev_ops = &otx2_sso_ops;
1707 /* For secondary processes, the primary has done all the work */
1708 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1709 sso_fastpath_fns_set(event_dev);
1713 dev = sso_pmd_priv(event_dev);
1715 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1717 /* Initialize the base otx2_dev object */
1718 rc = otx2_dev_init(pci_dev, dev);
1720 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1724 /* Get SSO and SSOW MSIX rsrc cnt */
1725 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
1726 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
1728 otx2_err("Unable to get free rsrc count");
1729 goto otx2_dev_uninit;
1731 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
1732 rsrc_cnt->ssow, rsrc_cnt->npa);
1734 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
1735 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
1736 /* Grab the NPA LF if required */
1737 rc = otx2_npa_lf_init(pci_dev, dev);
1739 otx2_err("Unable to init NPA lf. It might not be provisioned");
1740 goto otx2_dev_uninit;
1743 dev->drv_inited = true;
1744 dev->is_timeout_deq = 0;
1745 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1746 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1747 dev->max_num_events = -1;
1748 dev->nb_event_queues = 0;
1749 dev->nb_event_ports = 0;
1751 if (!dev->max_event_ports || !dev->max_event_queues) {
1752 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1753 dev->max_event_queues, dev->max_event_ports);
1755 goto otx2_npa_lf_uninit;
1759 sso_parse_devargs(dev, pci_dev->device.devargs);
1761 otx2_sso_dbg("Using dual workslot mode");
1762 dev->max_event_ports = dev->max_event_ports / 2;
1764 otx2_sso_dbg("Using single workslot mode");
1767 otx2_sso_pf_func_set(dev->pf_func);
1768 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1769 event_dev->data->name, dev->max_event_queues,
1770 dev->max_event_ports);
1771 if (dev->selftest) {
1772 event_dev->dev->driver = &pci_sso.driver;
1773 event_dev->dev_ops->dev_selftest();
1776 otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
1783 otx2_dev_fini(pci_dev, dev);
1789 otx2_sso_fini(struct rte_eventdev *event_dev)
1791 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1792 struct rte_pci_device *pci_dev;
1794 /* For secondary processes, nothing to be done */
1795 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1798 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1800 if (!dev->drv_inited)
1803 dev->drv_inited = false;
1807 if (otx2_npa_lf_active(dev)) {
1808 otx2_info("Common resource in use by other devices");
1813 otx2_dev_fini(pci_dev, dev);
1818 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1819 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1820 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1821 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
1822 OTX2_SSO_SINGLE_WS "=1"
1823 OTX2_SSO_GGRP_QOS "=<string>"
1824 OTX2_SSO_SELFTEST "=1");