1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <rte_eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev_stats.h"
16 #include "otx2_evdev.h"
18 #include "otx2_tim_evdev.h"
21 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
23 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
24 uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
25 struct otx2_mbox *mbox = dev->mbox;
26 struct msix_offset_rsp *msix_rsp;
29 /* Get SSO and SSOW MSIX vector offsets */
30 otx2_mbox_alloc_msg_msix_offset(mbox);
31 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
33 for (i = 0; i < nb_ports; i++)
34 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
36 for (i = 0; i < dev->nb_event_queues; i++)
37 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
43 sso_fastpath_fns_set(struct rte_eventdev *event_dev)
45 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
47 event_dev->enqueue = otx2_ssogws_enq;
48 event_dev->enqueue_burst = otx2_ssogws_enq_burst;
49 event_dev->enqueue_new_burst = otx2_ssogws_enq_new_burst;
50 event_dev->enqueue_forward_burst = otx2_ssogws_enq_fwd_burst;
52 event_dev->dequeue = otx2_ssogws_deq;
53 event_dev->dequeue_burst = otx2_ssogws_deq_burst;
54 if (dev->is_timeout_deq) {
55 event_dev->dequeue = otx2_ssogws_deq_timeout;
56 event_dev->dequeue_burst = otx2_ssogws_deq_timeout_burst;
60 event_dev->enqueue = otx2_ssogws_dual_enq;
61 event_dev->enqueue_burst = otx2_ssogws_dual_enq_burst;
62 event_dev->enqueue_new_burst =
63 otx2_ssogws_dual_enq_new_burst;
64 event_dev->enqueue_forward_burst =
65 otx2_ssogws_dual_enq_fwd_burst;
66 event_dev->dequeue = otx2_ssogws_dual_deq;
67 event_dev->dequeue_burst = otx2_ssogws_dual_deq_burst;
68 if (dev->is_timeout_deq) {
69 event_dev->dequeue = otx2_ssogws_dual_deq_timeout;
70 event_dev->dequeue_burst =
71 otx2_ssogws_dual_deq_timeout_burst;
78 otx2_sso_info_get(struct rte_eventdev *event_dev,
79 struct rte_event_dev_info *dev_info)
81 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
83 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
84 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
85 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
86 dev_info->max_event_queues = dev->max_event_queues;
87 dev_info->max_event_queue_flows = (1ULL << 20);
88 dev_info->max_event_queue_priority_levels = 8;
89 dev_info->max_event_priority_levels = 1;
90 dev_info->max_event_ports = dev->max_event_ports;
91 dev_info->max_event_port_dequeue_depth = 1;
92 dev_info->max_event_port_enqueue_depth = 1;
93 dev_info->max_num_events = dev->max_num_events;
94 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
95 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
96 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
97 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
98 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
99 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
103 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
105 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
109 val |= 0ULL << 12; /* SET 0 */
110 val |= 0x8000800080000000; /* Dont modify rest of the masks */
111 val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */
113 otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
117 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
118 const uint8_t queues[], const uint8_t priorities[],
121 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
125 RTE_SET_USED(priorities);
126 for (link = 0; link < nb_links; link++) {
128 struct otx2_ssogws_dual *ws = port;
131 sso_port_link_modify((struct otx2_ssogws *)
132 &ws->ws_state[0], queues[link], true);
133 sso_port_link_modify((struct otx2_ssogws *)
134 &ws->ws_state[1], queues[link], true);
136 struct otx2_ssogws *ws = port;
139 sso_port_link_modify(ws, queues[link], true);
142 sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
144 return (int)nb_links;
148 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
149 uint8_t queues[], uint16_t nb_unlinks)
151 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
155 for (unlink = 0; unlink < nb_unlinks; unlink++) {
157 struct otx2_ssogws_dual *ws = port;
160 sso_port_link_modify((struct otx2_ssogws *)
161 &ws->ws_state[0], queues[unlink],
163 sso_port_link_modify((struct otx2_ssogws *)
164 &ws->ws_state[1], queues[unlink],
167 struct otx2_ssogws *ws = port;
170 sso_port_link_modify(ws, queues[unlink], false);
173 sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
175 return (int)nb_unlinks;
179 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
180 uint16_t nb_lf, uint8_t attach)
183 struct rsrc_attach_req *req;
185 req = otx2_mbox_alloc_msg_attach_resources(mbox);
197 if (otx2_mbox_process(mbox) < 0)
200 struct rsrc_detach_req *req;
202 req = otx2_mbox_alloc_msg_detach_resources(mbox);
214 if (otx2_mbox_process(mbox) < 0)
222 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
223 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
232 struct sso_lf_alloc_req *req_ggrp;
233 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
234 req_ggrp->hwgrps = nb_lf;
239 struct ssow_lf_alloc_req *req_hws;
240 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
241 req_hws->hws = nb_lf;
251 struct sso_lf_free_req *req_ggrp;
252 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
253 req_ggrp->hwgrps = nb_lf;
258 struct ssow_lf_free_req *req_hws;
259 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
260 req_hws->hws = nb_lf;
268 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
272 if (alloc && type == SSO_LF_GGRP) {
273 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
275 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
276 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
277 dev->iue = rsp_ggrp->in_unit_entries;
284 otx2_sso_port_release(void *port)
290 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
292 RTE_SET_USED(event_dev);
293 RTE_SET_USED(queue_id);
297 sso_clr_links(const struct rte_eventdev *event_dev)
299 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
302 for (i = 0; i < dev->nb_event_ports; i++) {
304 struct otx2_ssogws_dual *ws;
306 ws = event_dev->data->ports[i];
307 for (j = 0; j < dev->nb_event_queues; j++) {
308 sso_port_link_modify((struct otx2_ssogws *)
309 &ws->ws_state[0], j, false);
310 sso_port_link_modify((struct otx2_ssogws *)
311 &ws->ws_state[1], j, false);
314 struct otx2_ssogws *ws;
316 ws = event_dev->data->ports[i];
317 for (j = 0; j < dev->nb_event_queues; j++)
318 sso_port_link_modify(ws, j, false);
324 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
326 ws->tag_op = base + SSOW_LF_GWS_TAG;
327 ws->wqp_op = base + SSOW_LF_GWS_WQP;
328 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
329 ws->swtp_op = base + SSOW_LF_GWS_SWTP;
330 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
331 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
335 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
337 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
338 struct otx2_mbox *mbox = dev->mbox;
343 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
345 nb_lf = dev->nb_event_ports * 2;
346 /* Ask AF to attach required LFs. */
347 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
349 otx2_err("Failed to attach SSO GWS LF");
353 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
354 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
355 otx2_err("Failed to init SSO GWS LF");
359 for (i = 0; i < dev->nb_event_ports; i++) {
360 struct otx2_ssogws_dual *ws;
363 /* Free memory prior to re-allocation if needed */
364 if (event_dev->data->ports[i] != NULL) {
365 ws = event_dev->data->ports[i];
370 /* Allocate event port memory */
371 ws = rte_zmalloc_socket("otx2_sso_ws",
372 sizeof(struct otx2_ssogws_dual),
374 event_dev->data->socket_id);
376 otx2_err("Failed to alloc memory for port=%d", i);
382 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
383 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
386 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
387 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
390 event_dev->data->ports[i] = ws;
394 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
395 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
402 sso_configure_ports(const struct rte_eventdev *event_dev)
404 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
405 struct otx2_mbox *mbox = dev->mbox;
409 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
411 nb_lf = dev->nb_event_ports;
412 /* Ask AF to attach required LFs. */
413 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
415 otx2_err("Failed to attach SSO GWS LF");
419 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
420 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
421 otx2_err("Failed to init SSO GWS LF");
425 for (i = 0; i < nb_lf; i++) {
426 struct otx2_ssogws *ws;
429 /* Free memory prior to re-allocation if needed */
430 if (event_dev->data->ports[i] != NULL) {
431 ws = event_dev->data->ports[i];
436 /* Allocate event port memory */
437 ws = rte_zmalloc_socket("otx2_sso_ws",
438 sizeof(struct otx2_ssogws),
440 event_dev->data->socket_id);
442 otx2_err("Failed to alloc memory for port=%d", i);
448 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
449 sso_set_port_ops(ws, base);
451 event_dev->data->ports[i] = ws;
455 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
456 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
463 sso_configure_queues(const struct rte_eventdev *event_dev)
465 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
466 struct otx2_mbox *mbox = dev->mbox;
470 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
472 nb_lf = dev->nb_event_queues;
473 /* Ask AF to attach required LFs. */
474 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
476 otx2_err("Failed to attach SSO GGRP LF");
480 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
481 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
482 otx2_err("Failed to init SSO GGRP LF");
490 sso_xaq_allocate(struct otx2_sso_evdev *dev)
492 const struct rte_memzone *mz;
493 struct npa_aura_s *aura;
494 static int reconfig_cnt;
495 char pool_name[RTE_MEMZONE_NAMESIZE];
500 rte_mempool_free(dev->xaq_pool);
503 * Allocate memory for Add work backpressure.
505 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
507 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
509 sizeof(struct npa_aura_s),
511 RTE_MEMZONE_IOVA_CONTIG,
514 otx2_err("Failed to allocate mem for fcmem");
518 dev->fc_iova = mz->iova;
519 dev->fc_mem = mz->addr;
521 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
522 memset(aura, 0, sizeof(struct npa_aura_s));
525 aura->fc_addr = dev->fc_iova;
526 aura->fc_hyst_bits = 0; /* Store count on all updates */
528 /* Taken from HRM 14.3.3(4) */
529 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
531 xaq_cnt += dev->xae_cnt / dev->xae_waes;
533 xaq_cnt += (dev->iue / dev->xae_waes) +
534 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
536 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
537 /* Setup XAQ based on number of nb queues. */
538 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
539 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
540 xaq_cnt, dev->xaq_buf_size, 0, 0,
543 if (dev->xaq_pool == NULL) {
544 otx2_err("Unable to create empty mempool.");
545 rte_memzone_free(mz);
549 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
550 rte_mbuf_platform_mempool_ops(), aura);
552 otx2_err("Unable to set xaqpool ops.");
556 rc = rte_mempool_populate_default(dev->xaq_pool);
558 otx2_err("Unable to set populate xaqpool.");
562 /* When SW does addwork (enqueue) check if there is space in XAQ by
563 * comparing fc_addr above against the xaq_lmt calculated below.
564 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
565 * to request XAQ to cache them even before enqueue is called.
567 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
568 dev->nb_event_queues);
569 dev->nb_xaq_cfg = xaq_cnt;
573 rte_mempool_free(dev->xaq_pool);
574 rte_memzone_free(mz);
579 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
581 struct otx2_mbox *mbox = dev->mbox;
582 struct sso_hw_setconfig *req;
584 otx2_sso_dbg("Configuring XAQ for GGRPs");
585 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
586 req->npa_pf_func = otx2_npa_pf_func_get();
587 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
588 req->hwgrps = dev->nb_event_queues;
590 return otx2_mbox_process(mbox);
594 sso_lf_teardown(struct otx2_sso_evdev *dev,
595 enum otx2_sso_lf_type lf_type)
601 nb_lf = dev->nb_event_queues;
604 nb_lf = dev->nb_event_ports;
605 nb_lf *= dev->dual_ws ? 2 : 1;
611 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
612 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
616 otx2_sso_configure(const struct rte_eventdev *event_dev)
618 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
619 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
624 deq_tmo_ns = conf->dequeue_timeout_ns;
627 deq_tmo_ns = dev->min_dequeue_timeout_ns;
629 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
630 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
631 otx2_err("Unsupported dequeue timeout requested");
635 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
636 dev->is_timeout_deq = 1;
638 dev->deq_tmo_ns = deq_tmo_ns;
640 if (conf->nb_event_ports > dev->max_event_ports ||
641 conf->nb_event_queues > dev->max_event_queues) {
642 otx2_err("Unsupported event queues/ports requested");
646 if (conf->nb_event_port_dequeue_depth > 1) {
647 otx2_err("Unsupported event port deq depth requested");
651 if (conf->nb_event_port_enqueue_depth > 1) {
652 otx2_err("Unsupported event port enq depth requested");
657 sso_unregister_irqs(event_dev);
659 if (dev->nb_event_queues) {
660 /* Finit any previous queues. */
661 sso_lf_teardown(dev, SSO_LF_GGRP);
663 if (dev->nb_event_ports) {
664 /* Finit any previous ports. */
665 sso_lf_teardown(dev, SSO_LF_GWS);
668 dev->nb_event_queues = conf->nb_event_queues;
669 dev->nb_event_ports = conf->nb_event_ports;
672 rc = sso_configure_dual_ports(event_dev);
674 rc = sso_configure_ports(event_dev);
677 otx2_err("Failed to configure event ports");
681 if (sso_configure_queues(event_dev) < 0) {
682 otx2_err("Failed to configure event queues");
687 if (sso_xaq_allocate(dev) < 0) {
689 goto teardown_hwggrp;
692 /* Clear any prior port-queue mapping. */
693 sso_clr_links(event_dev);
694 rc = sso_ggrp_alloc_xaq(dev);
696 otx2_err("Failed to alloc xaq to ggrp %d", rc);
697 goto teardown_hwggrp;
700 rc = sso_get_msix_offsets(event_dev);
702 otx2_err("Failed to get msix offsets %d", rc);
703 goto teardown_hwggrp;
706 rc = sso_register_irqs(event_dev);
708 otx2_err("Failed to register irq %d", rc);
709 goto teardown_hwggrp;
717 sso_lf_teardown(dev, SSO_LF_GGRP);
719 sso_lf_teardown(dev, SSO_LF_GWS);
720 dev->nb_event_queues = 0;
721 dev->nb_event_ports = 0;
727 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
728 struct rte_event_queue_conf *queue_conf)
730 RTE_SET_USED(event_dev);
731 RTE_SET_USED(queue_id);
733 queue_conf->nb_atomic_flows = (1ULL << 20);
734 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
735 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
736 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
740 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
741 const struct rte_event_queue_conf *queue_conf)
743 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
744 struct otx2_mbox *mbox = dev->mbox;
745 struct sso_grp_priority *req;
748 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
750 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
753 req->affinity = 0xFF;
754 /* Normalize <0-255> to <0-7> */
755 req->priority = queue_conf->priority / 32;
757 rc = otx2_mbox_process(mbox);
759 otx2_err("Failed to set priority queue=%d", queue_id);
767 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
768 struct rte_event_port_conf *port_conf)
770 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
772 RTE_SET_USED(port_id);
773 port_conf->new_event_threshold = dev->max_num_events;
774 port_conf->dequeue_depth = 1;
775 port_conf->enqueue_depth = 1;
779 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
780 const struct rte_event_port_conf *port_conf)
782 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
783 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
787 sso_func_trace("Port=%d", port_id);
788 RTE_SET_USED(port_conf);
790 if (event_dev->data->ports[port_id] == NULL) {
791 otx2_err("Invalid port Id %d", port_id);
795 for (q = 0; q < dev->nb_event_queues; q++) {
796 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
797 if (grps_base[q] == 0) {
798 otx2_err("Failed to get grp[%d] base addr", q);
803 /* Set get_work timeout for HWS */
804 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
807 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
809 rte_memcpy(ws->grps_base, grps_base,
810 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
811 ws->fc_mem = dev->fc_mem;
812 ws->xaq_lmt = dev->xaq_lmt;
813 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
814 ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
815 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
816 ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
818 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
819 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
821 rte_memcpy(ws->grps_base, grps_base,
822 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
823 ws->fc_mem = dev->fc_mem;
824 ws->xaq_lmt = dev->xaq_lmt;
825 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
828 otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
834 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
837 RTE_SET_USED(event_dev);
838 *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
844 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
846 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
848 fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base);
849 fprintf(f, "SSOW_LF_GWS_LINKS 0x%" PRIx64 "\n",
850 otx2_read64(base + SSOW_LF_GWS_LINKS));
851 fprintf(f, "SSOW_LF_GWS_PENDWQP 0x%" PRIx64 "\n",
852 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
853 fprintf(f, "SSOW_LF_GWS_PENDSTATE 0x%" PRIx64 "\n",
854 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
855 fprintf(f, "SSOW_LF_GWS_NW_TIM 0x%" PRIx64 "\n",
856 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
857 fprintf(f, "SSOW_LF_GWS_TAG 0x%" PRIx64 "\n",
858 otx2_read64(base + SSOW_LF_GWS_TAG));
859 fprintf(f, "SSOW_LF_GWS_WQP 0x%" PRIx64 "\n",
860 otx2_read64(base + SSOW_LF_GWS_TAG));
861 fprintf(f, "SSOW_LF_GWS_SWTP 0x%" PRIx64 "\n",
862 otx2_read64(base + SSOW_LF_GWS_SWTP));
863 fprintf(f, "SSOW_LF_GWS_PENDTAG 0x%" PRIx64 "\n",
864 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
868 ssoggrp_dump(uintptr_t base, FILE *f)
870 fprintf(f, "SSO_LF_GGRP Base addr 0x%" PRIx64 "\n", (uint64_t)base);
871 fprintf(f, "SSO_LF_GGRP_QCTL 0x%" PRIx64 "\n",
872 otx2_read64(base + SSO_LF_GGRP_QCTL));
873 fprintf(f, "SSO_LF_GGRP_XAQ_CNT 0x%" PRIx64 "\n",
874 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
875 fprintf(f, "SSO_LF_GGRP_INT_THR 0x%" PRIx64 "\n",
876 otx2_read64(base + SSO_LF_GGRP_INT_THR));
877 fprintf(f, "SSO_LF_GGRP_INT_CNT 0x%" PRIX64 "\n",
878 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
879 fprintf(f, "SSO_LF_GGRP_AQ_CNT 0x%" PRIX64 "\n",
880 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
881 fprintf(f, "SSO_LF_GGRP_AQ_THR 0x%" PRIX64 "\n",
882 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
883 fprintf(f, "SSO_LF_GGRP_MISC_CNT 0x%" PRIx64 "\n",
884 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
888 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
890 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
894 fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
895 "dual_ws" : "single_ws");
896 /* Dump SSOW registers */
897 for (port = 0; port < dev->nb_event_ports; port++) {
899 struct otx2_ssogws_dual *ws =
900 event_dev->data->ports[port];
902 fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
904 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
905 fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
907 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
909 fprintf(f, "[%s]SSO single workslot[%d] dump\n",
911 ssogws_dump(event_dev->data->ports[port], f);
915 /* Dump SSO registers */
916 for (queue = 0; queue < dev->nb_event_queues; queue++) {
917 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
919 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
920 ssoggrp_dump(ws->grps_base[queue], f);
922 struct otx2_ssogws *ws = event_dev->data->ports[0];
923 ssoggrp_dump(ws->grps_base[queue], f);
929 otx2_handle_event(void *arg, struct rte_event event)
931 struct rte_eventdev *event_dev = arg;
933 if (event_dev->dev_ops->dev_stop_flush != NULL)
934 event_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,
935 event, event_dev->data->dev_stop_flush_arg);
939 sso_qos_cfg(struct rte_eventdev *event_dev)
941 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
942 struct sso_grp_qos_cfg *req;
945 for (i = 0; i < dev->qos_queue_cnt; i++) {
946 uint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
947 uint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
948 uint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
950 if (dev->qos_parse_data[i].queue >= dev->nb_event_queues)
953 req = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);
954 req->xaq_limit = (dev->nb_xaq_cfg *
955 (xaq_prcnt ? xaq_prcnt : 100)) / 100;
956 req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *
957 (iaq_prcnt ? iaq_prcnt : 100)) / 100;
958 req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *
959 (taq_prcnt ? taq_prcnt : 100)) / 100;
962 if (dev->qos_queue_cnt)
963 otx2_mbox_process(dev->mbox);
967 sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
969 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
972 for (i = 0; i < dev->nb_event_ports; i++) {
974 struct otx2_ssogws_dual *ws;
976 ws = event_dev->data->ports[i];
977 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);
978 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
981 ws->ws_state[0].cur_grp = 0;
982 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
983 ws->ws_state[1].cur_grp = 0;
984 ws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;
986 struct otx2_ssogws *ws;
988 ws = event_dev->data->ports[i];
992 ws->cur_tt = SSO_SYNC_EMPTY;
998 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
999 struct otx2_ssogws temp_ws;
1001 memcpy(&temp_ws, &ws->ws_state[0],
1002 sizeof(struct otx2_ssogws_state));
1003 for (i = 0; i < dev->nb_event_queues; i++) {
1004 /* Consume all the events through HWS0 */
1005 ssogws_flush_events(&temp_ws, i, ws->grps_base[i],
1006 otx2_handle_event, event_dev);
1007 /* Enable/Disable SSO GGRP */
1008 otx2_write64(enable, ws->grps_base[i] +
1011 ws->ws_state[0].cur_grp = 0;
1012 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1014 struct otx2_ssogws *ws = event_dev->data->ports[0];
1016 for (i = 0; i < dev->nb_event_queues; i++) {
1017 /* Consume all the events through HWS0 */
1018 ssogws_flush_events(ws, i, ws->grps_base[i],
1019 otx2_handle_event, event_dev);
1020 /* Enable/Disable SSO GGRP */
1021 otx2_write64(enable, ws->grps_base[i] +
1025 ws->cur_tt = SSO_SYNC_EMPTY;
1028 /* reset SSO GWS cache */
1029 otx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);
1030 otx2_mbox_process(dev->mbox);
1034 otx2_sso_start(struct rte_eventdev *event_dev)
1037 sso_qos_cfg(event_dev);
1038 sso_cleanup(event_dev, 1);
1039 sso_fastpath_fns_set(event_dev);
1045 otx2_sso_stop(struct rte_eventdev *event_dev)
1048 sso_cleanup(event_dev, 0);
1053 otx2_sso_close(struct rte_eventdev *event_dev)
1055 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1056 uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
1059 if (!dev->configured)
1062 sso_unregister_irqs(event_dev);
1064 for (i = 0; i < dev->nb_event_queues; i++)
1067 for (i = 0; i < dev->nb_event_ports; i++)
1068 otx2_sso_port_unlink(event_dev, event_dev->data->ports[i],
1069 all_queues, dev->nb_event_queues);
1071 sso_lf_teardown(dev, SSO_LF_GGRP);
1072 sso_lf_teardown(dev, SSO_LF_GWS);
1073 dev->nb_event_ports = 0;
1074 dev->nb_event_queues = 0;
1075 rte_mempool_free(dev->xaq_pool);
1076 rte_memzone_free(rte_memzone_lookup(OTX2_SSO_FC_NAME));
1081 /* Initialize and register event driver with DPDK Application */
1082 static struct rte_eventdev_ops otx2_sso_ops = {
1083 .dev_infos_get = otx2_sso_info_get,
1084 .dev_configure = otx2_sso_configure,
1085 .queue_def_conf = otx2_sso_queue_def_conf,
1086 .queue_setup = otx2_sso_queue_setup,
1087 .queue_release = otx2_sso_queue_release,
1088 .port_def_conf = otx2_sso_port_def_conf,
1089 .port_setup = otx2_sso_port_setup,
1090 .port_release = otx2_sso_port_release,
1091 .port_link = otx2_sso_port_link,
1092 .port_unlink = otx2_sso_port_unlink,
1093 .timeout_ticks = otx2_sso_timeout_ticks,
1095 .timer_adapter_caps_get = otx2_tim_caps_get,
1097 .xstats_get = otx2_sso_xstats_get,
1098 .xstats_reset = otx2_sso_xstats_reset,
1099 .xstats_get_names = otx2_sso_xstats_get_names,
1101 .dump = otx2_sso_dump,
1102 .dev_start = otx2_sso_start,
1103 .dev_stop = otx2_sso_stop,
1104 .dev_close = otx2_sso_close,
1105 .dev_selftest = otx2_sso_selftest,
1108 #define OTX2_SSO_XAE_CNT "xae_cnt"
1109 #define OTX2_SSO_SINGLE_WS "single_ws"
1110 #define OTX2_SSO_GGRP_QOS "qos"
1111 #define OTX2_SSO_SELFTEST "selftest"
1114 parse_queue_param(char *value, void *opaque)
1116 struct otx2_sso_qos queue_qos = {0};
1117 uint8_t *val = (uint8_t *)&queue_qos;
1118 struct otx2_sso_evdev *dev = opaque;
1119 char *tok = strtok(value, "-");
1124 while (tok != NULL) {
1126 tok = strtok(NULL, "-");
1130 if (val != (&queue_qos.iaq_prcnt + 1)) {
1131 otx2_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
1135 dev->qos_queue_cnt++;
1136 dev->qos_parse_data = rte_realloc(dev->qos_parse_data,
1137 sizeof(struct otx2_sso_qos) *
1138 dev->qos_queue_cnt, 0);
1139 dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
1143 parse_qos_list(const char *value, void *opaque)
1145 char *s = strdup(value);
1156 if (start < end && *start) {
1158 parse_queue_param(start + 1, opaque);
1169 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
1173 /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
1174 * isn't allowed. Everything is expressed in percentages, 0 represents
1177 parse_qos_list(value, opaque);
1183 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
1185 struct rte_kvargs *kvlist;
1186 uint8_t single_ws = 0;
1188 if (devargs == NULL)
1190 kvlist = rte_kvargs_parse(devargs->args, NULL);
1194 rte_kvargs_process(kvlist, OTX2_SSO_SELFTEST, &parse_kvargs_flag,
1196 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
1198 rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
1200 rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
1203 dev->dual_ws = !single_ws;
1204 rte_kvargs_free(kvlist);
1208 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1210 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1211 sizeof(struct otx2_sso_evdev),
1216 otx2_sso_remove(struct rte_pci_device *pci_dev)
1218 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
1221 static const struct rte_pci_id pci_sso_map[] = {
1223 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1224 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
1231 static struct rte_pci_driver pci_sso = {
1232 .id_table = pci_sso_map,
1233 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1234 .probe = otx2_sso_probe,
1235 .remove = otx2_sso_remove,
1239 otx2_sso_init(struct rte_eventdev *event_dev)
1241 struct free_rsrcs_rsp *rsrc_cnt;
1242 struct rte_pci_device *pci_dev;
1243 struct otx2_sso_evdev *dev;
1246 event_dev->dev_ops = &otx2_sso_ops;
1247 /* For secondary processes, the primary has done all the work */
1248 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1249 sso_fastpath_fns_set(event_dev);
1253 dev = sso_pmd_priv(event_dev);
1255 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1257 /* Initialize the base otx2_dev object */
1258 rc = otx2_dev_init(pci_dev, dev);
1260 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1264 /* Get SSO and SSOW MSIX rsrc cnt */
1265 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
1266 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
1268 otx2_err("Unable to get free rsrc count");
1269 goto otx2_dev_uninit;
1271 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
1272 rsrc_cnt->ssow, rsrc_cnt->npa);
1274 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
1275 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
1276 /* Grab the NPA LF if required */
1277 rc = otx2_npa_lf_init(pci_dev, dev);
1279 otx2_err("Unable to init NPA lf. It might not be provisioned");
1280 goto otx2_dev_uninit;
1283 dev->drv_inited = true;
1284 dev->is_timeout_deq = 0;
1285 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1286 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1287 dev->max_num_events = -1;
1288 dev->nb_event_queues = 0;
1289 dev->nb_event_ports = 0;
1291 if (!dev->max_event_ports || !dev->max_event_queues) {
1292 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1293 dev->max_event_queues, dev->max_event_ports);
1295 goto otx2_npa_lf_uninit;
1299 sso_parse_devargs(dev, pci_dev->device.devargs);
1301 otx2_sso_dbg("Using dual workslot mode");
1302 dev->max_event_ports = dev->max_event_ports / 2;
1304 otx2_sso_dbg("Using single workslot mode");
1307 otx2_sso_pf_func_set(dev->pf_func);
1308 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1309 event_dev->data->name, dev->max_event_queues,
1310 dev->max_event_ports);
1311 if (dev->selftest) {
1312 event_dev->dev->driver = &pci_sso.driver;
1313 event_dev->dev_ops->dev_selftest();
1316 otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
1323 otx2_dev_fini(pci_dev, dev);
1329 otx2_sso_fini(struct rte_eventdev *event_dev)
1331 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1332 struct rte_pci_device *pci_dev;
1334 /* For secondary processes, nothing to be done */
1335 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1338 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1340 if (!dev->drv_inited)
1343 dev->drv_inited = false;
1347 if (otx2_npa_lf_active(dev)) {
1348 otx2_info("Common resource in use by other devices");
1353 otx2_dev_fini(pci_dev, dev);
1358 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1359 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1360 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1361 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
1362 OTX2_SSO_SINGLE_WS "=1"
1363 OTX2_SSO_GGRP_QOS "=<string>"
1364 OTX2_SSO_SELFTEST "=1");