1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <rte_eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev.h"
18 otx2_sso_info_get(struct rte_eventdev *event_dev,
19 struct rte_event_dev_info *dev_info)
21 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
23 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
24 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
25 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
26 dev_info->max_event_queues = dev->max_event_queues;
27 dev_info->max_event_queue_flows = (1ULL << 20);
28 dev_info->max_event_queue_priority_levels = 8;
29 dev_info->max_event_priority_levels = 1;
30 dev_info->max_event_ports = dev->max_event_ports;
31 dev_info->max_event_port_dequeue_depth = 1;
32 dev_info->max_event_port_enqueue_depth = 1;
33 dev_info->max_num_events = dev->max_num_events;
34 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
35 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
36 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
37 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
38 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
39 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
43 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
44 uint16_t nb_lf, uint8_t attach)
47 struct rsrc_attach_req *req;
49 req = otx2_mbox_alloc_msg_attach_resources(mbox);
61 if (otx2_mbox_process(mbox) < 0)
64 struct rsrc_detach_req *req;
66 req = otx2_mbox_alloc_msg_detach_resources(mbox);
78 if (otx2_mbox_process(mbox) < 0)
86 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
87 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
96 struct sso_lf_alloc_req *req_ggrp;
97 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
98 req_ggrp->hwgrps = nb_lf;
103 struct ssow_lf_alloc_req *req_hws;
104 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
105 req_hws->hws = nb_lf;
115 struct sso_lf_free_req *req_ggrp;
116 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
117 req_ggrp->hwgrps = nb_lf;
122 struct ssow_lf_free_req *req_hws;
123 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
124 req_hws->hws = nb_lf;
132 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
136 if (alloc && type == SSO_LF_GGRP) {
137 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
139 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
140 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
141 dev->iue = rsp_ggrp->in_unit_entries;
148 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
150 RTE_SET_USED(event_dev);
151 RTE_SET_USED(queue_id);
155 sso_configure_ports(const struct rte_eventdev *event_dev)
157 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
158 struct otx2_mbox *mbox = dev->mbox;
162 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
164 nb_lf = dev->nb_event_ports;
165 /* Ask AF to attach required LFs. */
166 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
168 otx2_err("Failed to attach SSO GWS LF");
172 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
173 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
174 otx2_err("Failed to init SSO GWS LF");
182 sso_configure_queues(const struct rte_eventdev *event_dev)
184 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
185 struct otx2_mbox *mbox = dev->mbox;
189 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
191 nb_lf = dev->nb_event_queues;
192 /* Ask AF to attach required LFs. */
193 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
195 otx2_err("Failed to attach SSO GGRP LF");
199 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
200 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
201 otx2_err("Failed to init SSO GGRP LF");
209 sso_xaq_allocate(struct otx2_sso_evdev *dev)
211 const struct rte_memzone *mz;
212 struct npa_aura_s *aura;
213 static int reconfig_cnt;
214 char pool_name[RTE_MEMZONE_NAMESIZE];
219 rte_mempool_free(dev->xaq_pool);
222 * Allocate memory for Add work backpressure.
224 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
226 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
228 sizeof(struct npa_aura_s),
230 RTE_MEMZONE_IOVA_CONTIG,
233 otx2_err("Failed to allocate mem for fcmem");
237 dev->fc_iova = mz->iova;
238 dev->fc_mem = mz->addr;
240 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
241 memset(aura, 0, sizeof(struct npa_aura_s));
244 aura->fc_addr = dev->fc_iova;
245 aura->fc_hyst_bits = 0; /* Store count on all updates */
247 /* Taken from HRM 14.3.3(4) */
248 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
250 xaq_cnt += dev->xae_cnt / dev->xae_waes;
252 xaq_cnt += (dev->iue / dev->xae_waes) +
253 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
255 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
256 /* Setup XAQ based on number of nb queues. */
257 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
258 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
259 xaq_cnt, dev->xaq_buf_size, 0, 0,
262 if (dev->xaq_pool == NULL) {
263 otx2_err("Unable to create empty mempool.");
264 rte_memzone_free(mz);
268 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
269 rte_mbuf_platform_mempool_ops(), aura);
271 otx2_err("Unable to set xaqpool ops.");
275 rc = rte_mempool_populate_default(dev->xaq_pool);
277 otx2_err("Unable to set populate xaqpool.");
281 /* When SW does addwork (enqueue) check if there is space in XAQ by
282 * comparing fc_addr above against the xaq_lmt calculated below.
283 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
284 * to request XAQ to cache them even before enqueue is called.
286 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
287 dev->nb_event_queues);
288 dev->nb_xaq_cfg = xaq_cnt;
292 rte_mempool_free(dev->xaq_pool);
293 rte_memzone_free(mz);
298 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
300 struct otx2_mbox *mbox = dev->mbox;
301 struct sso_hw_setconfig *req;
303 otx2_sso_dbg("Configuring XAQ for GGRPs");
304 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
305 req->npa_pf_func = otx2_npa_pf_func_get();
306 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
307 req->hwgrps = dev->nb_event_queues;
309 return otx2_mbox_process(mbox);
313 sso_lf_teardown(struct otx2_sso_evdev *dev,
314 enum otx2_sso_lf_type lf_type)
320 nb_lf = dev->nb_event_queues;
323 nb_lf = dev->nb_event_ports;
329 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
330 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
334 otx2_sso_configure(const struct rte_eventdev *event_dev)
336 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
337 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
342 deq_tmo_ns = conf->dequeue_timeout_ns;
345 deq_tmo_ns = dev->min_dequeue_timeout_ns;
347 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
348 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
349 otx2_err("Unsupported dequeue timeout requested");
353 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
354 dev->is_timeout_deq = 1;
356 dev->deq_tmo_ns = deq_tmo_ns;
358 if (conf->nb_event_ports > dev->max_event_ports ||
359 conf->nb_event_queues > dev->max_event_queues) {
360 otx2_err("Unsupported event queues/ports requested");
364 if (conf->nb_event_port_dequeue_depth > 1) {
365 otx2_err("Unsupported event port deq depth requested");
369 if (conf->nb_event_port_enqueue_depth > 1) {
370 otx2_err("Unsupported event port enq depth requested");
374 if (dev->nb_event_queues) {
375 /* Finit any previous queues. */
376 sso_lf_teardown(dev, SSO_LF_GGRP);
378 if (dev->nb_event_ports) {
379 /* Finit any previous ports. */
380 sso_lf_teardown(dev, SSO_LF_GWS);
383 dev->nb_event_queues = conf->nb_event_queues;
384 dev->nb_event_ports = conf->nb_event_ports;
386 if (sso_configure_ports(event_dev)) {
387 otx2_err("Failed to configure event ports");
391 if (sso_configure_queues(event_dev) < 0) {
392 otx2_err("Failed to configure event queues");
397 if (sso_xaq_allocate(dev) < 0) {
399 goto teardown_hwggrp;
402 rc = sso_ggrp_alloc_xaq(dev);
404 otx2_err("Failed to alloc xaq to ggrp %d", rc);
405 goto teardown_hwggrp;
413 sso_lf_teardown(dev, SSO_LF_GGRP);
415 sso_lf_teardown(dev, SSO_LF_GWS);
416 dev->nb_event_queues = 0;
417 dev->nb_event_ports = 0;
423 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
424 struct rte_event_queue_conf *queue_conf)
426 RTE_SET_USED(event_dev);
427 RTE_SET_USED(queue_id);
429 queue_conf->nb_atomic_flows = (1ULL << 20);
430 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
431 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
432 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
436 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
437 const struct rte_event_queue_conf *queue_conf)
439 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
440 struct otx2_mbox *mbox = dev->mbox;
441 struct sso_grp_priority *req;
444 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
446 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
449 req->affinity = 0xFF;
450 /* Normalize <0-255> to <0-7> */
451 req->priority = queue_conf->priority / 32;
453 rc = otx2_mbox_process(mbox);
455 otx2_err("Failed to set priority queue=%d", queue_id);
462 /* Initialize and register event driver with DPDK Application */
463 static struct rte_eventdev_ops otx2_sso_ops = {
464 .dev_infos_get = otx2_sso_info_get,
465 .dev_configure = otx2_sso_configure,
466 .queue_def_conf = otx2_sso_queue_def_conf,
467 .queue_setup = otx2_sso_queue_setup,
468 .queue_release = otx2_sso_queue_release,
471 #define OTX2_SSO_XAE_CNT "xae_cnt"
474 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
476 struct rte_kvargs *kvlist;
480 kvlist = rte_kvargs_parse(devargs->args, NULL);
484 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
487 rte_kvargs_free(kvlist);
491 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
493 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
494 sizeof(struct otx2_sso_evdev),
499 otx2_sso_remove(struct rte_pci_device *pci_dev)
501 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
504 static const struct rte_pci_id pci_sso_map[] = {
506 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
507 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
514 static struct rte_pci_driver pci_sso = {
515 .id_table = pci_sso_map,
516 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
517 .probe = otx2_sso_probe,
518 .remove = otx2_sso_remove,
522 otx2_sso_init(struct rte_eventdev *event_dev)
524 struct free_rsrcs_rsp *rsrc_cnt;
525 struct rte_pci_device *pci_dev;
526 struct otx2_sso_evdev *dev;
529 event_dev->dev_ops = &otx2_sso_ops;
530 /* For secondary processes, the primary has done all the work */
531 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
534 dev = sso_pmd_priv(event_dev);
536 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
538 /* Initialize the base otx2_dev object */
539 rc = otx2_dev_init(pci_dev, dev);
541 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
545 /* Get SSO and SSOW MSIX rsrc cnt */
546 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
547 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
549 otx2_err("Unable to get free rsrc count");
550 goto otx2_dev_uninit;
552 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
553 rsrc_cnt->ssow, rsrc_cnt->npa);
555 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
556 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
557 /* Grab the NPA LF if required */
558 rc = otx2_npa_lf_init(pci_dev, dev);
560 otx2_err("Unable to init NPA lf. It might not be provisioned");
561 goto otx2_dev_uninit;
564 dev->drv_inited = true;
565 dev->is_timeout_deq = 0;
566 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
567 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
568 dev->max_num_events = -1;
569 dev->nb_event_queues = 0;
570 dev->nb_event_ports = 0;
572 if (!dev->max_event_ports || !dev->max_event_queues) {
573 otx2_err("Not enough eventdev resource queues=%d ports=%d",
574 dev->max_event_queues, dev->max_event_ports);
576 goto otx2_npa_lf_uninit;
579 sso_parse_devargs(dev, pci_dev->device.devargs);
581 otx2_sso_pf_func_set(dev->pf_func);
582 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
583 event_dev->data->name, dev->max_event_queues,
584 dev->max_event_ports);
592 otx2_dev_fini(pci_dev, dev);
598 otx2_sso_fini(struct rte_eventdev *event_dev)
600 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
601 struct rte_pci_device *pci_dev;
603 /* For secondary processes, nothing to be done */
604 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
607 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
609 if (!dev->drv_inited)
612 dev->drv_inited = false;
616 if (otx2_npa_lf_active(dev)) {
617 otx2_info("Common resource in use by other devices");
621 otx2_dev_fini(pci_dev, dev);
626 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
627 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
628 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
629 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>");