1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <rte_eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev_stats.h"
16 #include "otx2_evdev.h"
20 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
22 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
23 uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
24 struct otx2_mbox *mbox = dev->mbox;
25 struct msix_offset_rsp *msix_rsp;
28 /* Get SSO and SSOW MSIX vector offsets */
29 otx2_mbox_alloc_msg_msix_offset(mbox);
30 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
32 for (i = 0; i < nb_ports; i++)
33 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
35 for (i = 0; i < dev->nb_event_queues; i++)
36 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
42 sso_fastpath_fns_set(struct rte_eventdev *event_dev)
44 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
46 event_dev->enqueue = otx2_ssogws_enq;
47 event_dev->enqueue_burst = otx2_ssogws_enq_burst;
48 event_dev->enqueue_new_burst = otx2_ssogws_enq_new_burst;
49 event_dev->enqueue_forward_burst = otx2_ssogws_enq_fwd_burst;
51 event_dev->dequeue = otx2_ssogws_deq;
52 event_dev->dequeue_burst = otx2_ssogws_deq_burst;
53 if (dev->is_timeout_deq) {
54 event_dev->dequeue = otx2_ssogws_deq_timeout;
55 event_dev->dequeue_burst = otx2_ssogws_deq_timeout_burst;
59 event_dev->enqueue = otx2_ssogws_dual_enq;
60 event_dev->enqueue_burst = otx2_ssogws_dual_enq_burst;
61 event_dev->enqueue_new_burst =
62 otx2_ssogws_dual_enq_new_burst;
63 event_dev->enqueue_forward_burst =
64 otx2_ssogws_dual_enq_fwd_burst;
65 event_dev->dequeue = otx2_ssogws_dual_deq;
66 event_dev->dequeue_burst = otx2_ssogws_dual_deq_burst;
67 if (dev->is_timeout_deq) {
68 event_dev->dequeue = otx2_ssogws_dual_deq_timeout;
69 event_dev->dequeue_burst =
70 otx2_ssogws_dual_deq_timeout_burst;
77 otx2_sso_info_get(struct rte_eventdev *event_dev,
78 struct rte_event_dev_info *dev_info)
80 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
82 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
83 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
84 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
85 dev_info->max_event_queues = dev->max_event_queues;
86 dev_info->max_event_queue_flows = (1ULL << 20);
87 dev_info->max_event_queue_priority_levels = 8;
88 dev_info->max_event_priority_levels = 1;
89 dev_info->max_event_ports = dev->max_event_ports;
90 dev_info->max_event_port_dequeue_depth = 1;
91 dev_info->max_event_port_enqueue_depth = 1;
92 dev_info->max_num_events = dev->max_num_events;
93 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
94 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
95 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
96 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
97 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
98 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
102 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
104 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
108 val |= 0ULL << 12; /* SET 0 */
109 val |= 0x8000800080000000; /* Dont modify rest of the masks */
110 val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */
112 otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
116 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
117 const uint8_t queues[], const uint8_t priorities[],
120 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
124 RTE_SET_USED(priorities);
125 for (link = 0; link < nb_links; link++) {
127 struct otx2_ssogws_dual *ws = port;
130 sso_port_link_modify((struct otx2_ssogws *)
131 &ws->ws_state[0], queues[link], true);
132 sso_port_link_modify((struct otx2_ssogws *)
133 &ws->ws_state[1], queues[link], true);
135 struct otx2_ssogws *ws = port;
138 sso_port_link_modify(ws, queues[link], true);
141 sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
143 return (int)nb_links;
147 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
148 uint8_t queues[], uint16_t nb_unlinks)
150 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
154 for (unlink = 0; unlink < nb_unlinks; unlink++) {
156 struct otx2_ssogws_dual *ws = port;
159 sso_port_link_modify((struct otx2_ssogws *)
160 &ws->ws_state[0], queues[unlink],
162 sso_port_link_modify((struct otx2_ssogws *)
163 &ws->ws_state[1], queues[unlink],
166 struct otx2_ssogws *ws = port;
169 sso_port_link_modify(ws, queues[unlink], false);
172 sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
174 return (int)nb_unlinks;
178 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
179 uint16_t nb_lf, uint8_t attach)
182 struct rsrc_attach_req *req;
184 req = otx2_mbox_alloc_msg_attach_resources(mbox);
196 if (otx2_mbox_process(mbox) < 0)
199 struct rsrc_detach_req *req;
201 req = otx2_mbox_alloc_msg_detach_resources(mbox);
213 if (otx2_mbox_process(mbox) < 0)
221 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
222 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
231 struct sso_lf_alloc_req *req_ggrp;
232 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
233 req_ggrp->hwgrps = nb_lf;
238 struct ssow_lf_alloc_req *req_hws;
239 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
240 req_hws->hws = nb_lf;
250 struct sso_lf_free_req *req_ggrp;
251 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
252 req_ggrp->hwgrps = nb_lf;
257 struct ssow_lf_free_req *req_hws;
258 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
259 req_hws->hws = nb_lf;
267 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
271 if (alloc && type == SSO_LF_GGRP) {
272 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
274 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
275 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
276 dev->iue = rsp_ggrp->in_unit_entries;
283 otx2_sso_port_release(void *port)
289 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
291 RTE_SET_USED(event_dev);
292 RTE_SET_USED(queue_id);
296 sso_clr_links(const struct rte_eventdev *event_dev)
298 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
301 for (i = 0; i < dev->nb_event_ports; i++) {
303 struct otx2_ssogws_dual *ws;
305 ws = event_dev->data->ports[i];
306 for (j = 0; j < dev->nb_event_queues; j++) {
307 sso_port_link_modify((struct otx2_ssogws *)
308 &ws->ws_state[0], j, false);
309 sso_port_link_modify((struct otx2_ssogws *)
310 &ws->ws_state[1], j, false);
313 struct otx2_ssogws *ws;
315 ws = event_dev->data->ports[i];
316 for (j = 0; j < dev->nb_event_queues; j++)
317 sso_port_link_modify(ws, j, false);
323 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
325 ws->tag_op = base + SSOW_LF_GWS_TAG;
326 ws->wqp_op = base + SSOW_LF_GWS_WQP;
327 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
328 ws->swtp_op = base + SSOW_LF_GWS_SWTP;
329 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
330 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
334 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
336 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
337 struct otx2_mbox *mbox = dev->mbox;
342 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
344 nb_lf = dev->nb_event_ports * 2;
345 /* Ask AF to attach required LFs. */
346 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
348 otx2_err("Failed to attach SSO GWS LF");
352 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
353 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
354 otx2_err("Failed to init SSO GWS LF");
358 for (i = 0; i < dev->nb_event_ports; i++) {
359 struct otx2_ssogws_dual *ws;
362 /* Free memory prior to re-allocation if needed */
363 if (event_dev->data->ports[i] != NULL) {
364 ws = event_dev->data->ports[i];
369 /* Allocate event port memory */
370 ws = rte_zmalloc_socket("otx2_sso_ws",
371 sizeof(struct otx2_ssogws_dual),
373 event_dev->data->socket_id);
375 otx2_err("Failed to alloc memory for port=%d", i);
381 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
382 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
385 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
386 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
389 event_dev->data->ports[i] = ws;
393 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
394 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
401 sso_configure_ports(const struct rte_eventdev *event_dev)
403 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
404 struct otx2_mbox *mbox = dev->mbox;
408 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
410 nb_lf = dev->nb_event_ports;
411 /* Ask AF to attach required LFs. */
412 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
414 otx2_err("Failed to attach SSO GWS LF");
418 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
419 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
420 otx2_err("Failed to init SSO GWS LF");
424 for (i = 0; i < nb_lf; i++) {
425 struct otx2_ssogws *ws;
428 /* Free memory prior to re-allocation if needed */
429 if (event_dev->data->ports[i] != NULL) {
430 ws = event_dev->data->ports[i];
435 /* Allocate event port memory */
436 ws = rte_zmalloc_socket("otx2_sso_ws",
437 sizeof(struct otx2_ssogws),
439 event_dev->data->socket_id);
441 otx2_err("Failed to alloc memory for port=%d", i);
447 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
448 sso_set_port_ops(ws, base);
450 event_dev->data->ports[i] = ws;
454 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
455 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
462 sso_configure_queues(const struct rte_eventdev *event_dev)
464 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
465 struct otx2_mbox *mbox = dev->mbox;
469 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
471 nb_lf = dev->nb_event_queues;
472 /* Ask AF to attach required LFs. */
473 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
475 otx2_err("Failed to attach SSO GGRP LF");
479 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
480 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
481 otx2_err("Failed to init SSO GGRP LF");
489 sso_xaq_allocate(struct otx2_sso_evdev *dev)
491 const struct rte_memzone *mz;
492 struct npa_aura_s *aura;
493 static int reconfig_cnt;
494 char pool_name[RTE_MEMZONE_NAMESIZE];
499 rte_mempool_free(dev->xaq_pool);
502 * Allocate memory for Add work backpressure.
504 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
506 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
508 sizeof(struct npa_aura_s),
510 RTE_MEMZONE_IOVA_CONTIG,
513 otx2_err("Failed to allocate mem for fcmem");
517 dev->fc_iova = mz->iova;
518 dev->fc_mem = mz->addr;
520 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
521 memset(aura, 0, sizeof(struct npa_aura_s));
524 aura->fc_addr = dev->fc_iova;
525 aura->fc_hyst_bits = 0; /* Store count on all updates */
527 /* Taken from HRM 14.3.3(4) */
528 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
530 xaq_cnt += dev->xae_cnt / dev->xae_waes;
532 xaq_cnt += (dev->iue / dev->xae_waes) +
533 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
535 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
536 /* Setup XAQ based on number of nb queues. */
537 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
538 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
539 xaq_cnt, dev->xaq_buf_size, 0, 0,
542 if (dev->xaq_pool == NULL) {
543 otx2_err("Unable to create empty mempool.");
544 rte_memzone_free(mz);
548 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
549 rte_mbuf_platform_mempool_ops(), aura);
551 otx2_err("Unable to set xaqpool ops.");
555 rc = rte_mempool_populate_default(dev->xaq_pool);
557 otx2_err("Unable to set populate xaqpool.");
561 /* When SW does addwork (enqueue) check if there is space in XAQ by
562 * comparing fc_addr above against the xaq_lmt calculated below.
563 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
564 * to request XAQ to cache them even before enqueue is called.
566 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
567 dev->nb_event_queues);
568 dev->nb_xaq_cfg = xaq_cnt;
572 rte_mempool_free(dev->xaq_pool);
573 rte_memzone_free(mz);
578 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
580 struct otx2_mbox *mbox = dev->mbox;
581 struct sso_hw_setconfig *req;
583 otx2_sso_dbg("Configuring XAQ for GGRPs");
584 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
585 req->npa_pf_func = otx2_npa_pf_func_get();
586 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
587 req->hwgrps = dev->nb_event_queues;
589 return otx2_mbox_process(mbox);
593 sso_lf_teardown(struct otx2_sso_evdev *dev,
594 enum otx2_sso_lf_type lf_type)
600 nb_lf = dev->nb_event_queues;
603 nb_lf = dev->nb_event_ports;
604 nb_lf *= dev->dual_ws ? 2 : 1;
610 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
611 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
615 otx2_sso_configure(const struct rte_eventdev *event_dev)
617 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
618 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
623 deq_tmo_ns = conf->dequeue_timeout_ns;
626 deq_tmo_ns = dev->min_dequeue_timeout_ns;
628 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
629 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
630 otx2_err("Unsupported dequeue timeout requested");
634 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
635 dev->is_timeout_deq = 1;
637 dev->deq_tmo_ns = deq_tmo_ns;
639 if (conf->nb_event_ports > dev->max_event_ports ||
640 conf->nb_event_queues > dev->max_event_queues) {
641 otx2_err("Unsupported event queues/ports requested");
645 if (conf->nb_event_port_dequeue_depth > 1) {
646 otx2_err("Unsupported event port deq depth requested");
650 if (conf->nb_event_port_enqueue_depth > 1) {
651 otx2_err("Unsupported event port enq depth requested");
656 sso_unregister_irqs(event_dev);
658 if (dev->nb_event_queues) {
659 /* Finit any previous queues. */
660 sso_lf_teardown(dev, SSO_LF_GGRP);
662 if (dev->nb_event_ports) {
663 /* Finit any previous ports. */
664 sso_lf_teardown(dev, SSO_LF_GWS);
667 dev->nb_event_queues = conf->nb_event_queues;
668 dev->nb_event_ports = conf->nb_event_ports;
671 rc = sso_configure_dual_ports(event_dev);
673 rc = sso_configure_ports(event_dev);
676 otx2_err("Failed to configure event ports");
680 if (sso_configure_queues(event_dev) < 0) {
681 otx2_err("Failed to configure event queues");
686 if (sso_xaq_allocate(dev) < 0) {
688 goto teardown_hwggrp;
691 /* Clear any prior port-queue mapping. */
692 sso_clr_links(event_dev);
693 rc = sso_ggrp_alloc_xaq(dev);
695 otx2_err("Failed to alloc xaq to ggrp %d", rc);
696 goto teardown_hwggrp;
699 rc = sso_get_msix_offsets(event_dev);
701 otx2_err("Failed to get msix offsets %d", rc);
702 goto teardown_hwggrp;
705 rc = sso_register_irqs(event_dev);
707 otx2_err("Failed to register irq %d", rc);
708 goto teardown_hwggrp;
716 sso_lf_teardown(dev, SSO_LF_GGRP);
718 sso_lf_teardown(dev, SSO_LF_GWS);
719 dev->nb_event_queues = 0;
720 dev->nb_event_ports = 0;
726 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
727 struct rte_event_queue_conf *queue_conf)
729 RTE_SET_USED(event_dev);
730 RTE_SET_USED(queue_id);
732 queue_conf->nb_atomic_flows = (1ULL << 20);
733 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
734 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
735 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
739 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
740 const struct rte_event_queue_conf *queue_conf)
742 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
743 struct otx2_mbox *mbox = dev->mbox;
744 struct sso_grp_priority *req;
747 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
749 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
752 req->affinity = 0xFF;
753 /* Normalize <0-255> to <0-7> */
754 req->priority = queue_conf->priority / 32;
756 rc = otx2_mbox_process(mbox);
758 otx2_err("Failed to set priority queue=%d", queue_id);
766 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
767 struct rte_event_port_conf *port_conf)
769 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
771 RTE_SET_USED(port_id);
772 port_conf->new_event_threshold = dev->max_num_events;
773 port_conf->dequeue_depth = 1;
774 port_conf->enqueue_depth = 1;
778 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
779 const struct rte_event_port_conf *port_conf)
781 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
782 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
786 sso_func_trace("Port=%d", port_id);
787 RTE_SET_USED(port_conf);
789 if (event_dev->data->ports[port_id] == NULL) {
790 otx2_err("Invalid port Id %d", port_id);
794 for (q = 0; q < dev->nb_event_queues; q++) {
795 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
796 if (grps_base[q] == 0) {
797 otx2_err("Failed to get grp[%d] base addr", q);
802 /* Set get_work timeout for HWS */
803 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
806 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
808 rte_memcpy(ws->grps_base, grps_base,
809 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
810 ws->fc_mem = dev->fc_mem;
811 ws->xaq_lmt = dev->xaq_lmt;
812 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
813 ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
814 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
815 ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
817 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
818 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
820 rte_memcpy(ws->grps_base, grps_base,
821 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
822 ws->fc_mem = dev->fc_mem;
823 ws->xaq_lmt = dev->xaq_lmt;
824 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
827 otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
833 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
836 RTE_SET_USED(event_dev);
837 *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
843 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
845 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
847 fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base);
848 fprintf(f, "SSOW_LF_GWS_LINKS 0x%" PRIx64 "\n",
849 otx2_read64(base + SSOW_LF_GWS_LINKS));
850 fprintf(f, "SSOW_LF_GWS_PENDWQP 0x%" PRIx64 "\n",
851 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
852 fprintf(f, "SSOW_LF_GWS_PENDSTATE 0x%" PRIx64 "\n",
853 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
854 fprintf(f, "SSOW_LF_GWS_NW_TIM 0x%" PRIx64 "\n",
855 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
856 fprintf(f, "SSOW_LF_GWS_TAG 0x%" PRIx64 "\n",
857 otx2_read64(base + SSOW_LF_GWS_TAG));
858 fprintf(f, "SSOW_LF_GWS_WQP 0x%" PRIx64 "\n",
859 otx2_read64(base + SSOW_LF_GWS_TAG));
860 fprintf(f, "SSOW_LF_GWS_SWTP 0x%" PRIx64 "\n",
861 otx2_read64(base + SSOW_LF_GWS_SWTP));
862 fprintf(f, "SSOW_LF_GWS_PENDTAG 0x%" PRIx64 "\n",
863 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
867 ssoggrp_dump(uintptr_t base, FILE *f)
869 fprintf(f, "SSO_LF_GGRP Base addr 0x%" PRIx64 "\n", (uint64_t)base);
870 fprintf(f, "SSO_LF_GGRP_QCTL 0x%" PRIx64 "\n",
871 otx2_read64(base + SSO_LF_GGRP_QCTL));
872 fprintf(f, "SSO_LF_GGRP_XAQ_CNT 0x%" PRIx64 "\n",
873 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
874 fprintf(f, "SSO_LF_GGRP_INT_THR 0x%" PRIx64 "\n",
875 otx2_read64(base + SSO_LF_GGRP_INT_THR));
876 fprintf(f, "SSO_LF_GGRP_INT_CNT 0x%" PRIX64 "\n",
877 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
878 fprintf(f, "SSO_LF_GGRP_AQ_CNT 0x%" PRIX64 "\n",
879 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
880 fprintf(f, "SSO_LF_GGRP_AQ_THR 0x%" PRIX64 "\n",
881 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
882 fprintf(f, "SSO_LF_GGRP_MISC_CNT 0x%" PRIx64 "\n",
883 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
887 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
889 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
893 fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
894 "dual_ws" : "single_ws");
895 /* Dump SSOW registers */
896 for (port = 0; port < dev->nb_event_ports; port++) {
898 struct otx2_ssogws_dual *ws =
899 event_dev->data->ports[port];
901 fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
903 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
904 fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
906 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
908 fprintf(f, "[%s]SSO single workslot[%d] dump\n",
910 ssogws_dump(event_dev->data->ports[port], f);
914 /* Dump SSO registers */
915 for (queue = 0; queue < dev->nb_event_queues; queue++) {
916 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
918 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
919 ssoggrp_dump(ws->grps_base[queue], f);
921 struct otx2_ssogws *ws = event_dev->data->ports[0];
922 ssoggrp_dump(ws->grps_base[queue], f);
928 otx2_handle_event(void *arg, struct rte_event event)
930 struct rte_eventdev *event_dev = arg;
932 if (event_dev->dev_ops->dev_stop_flush != NULL)
933 event_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,
934 event, event_dev->data->dev_stop_flush_arg);
938 sso_qos_cfg(struct rte_eventdev *event_dev)
940 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
941 struct sso_grp_qos_cfg *req;
944 for (i = 0; i < dev->qos_queue_cnt; i++) {
945 uint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
946 uint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
947 uint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
949 if (dev->qos_parse_data[i].queue >= dev->nb_event_queues)
952 req = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);
953 req->xaq_limit = (dev->nb_xaq_cfg *
954 (xaq_prcnt ? xaq_prcnt : 100)) / 100;
955 req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *
956 (iaq_prcnt ? iaq_prcnt : 100)) / 100;
957 req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *
958 (taq_prcnt ? taq_prcnt : 100)) / 100;
961 if (dev->qos_queue_cnt)
962 otx2_mbox_process(dev->mbox);
966 sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
968 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
971 for (i = 0; i < dev->nb_event_ports; i++) {
973 struct otx2_ssogws_dual *ws;
975 ws = event_dev->data->ports[i];
976 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);
977 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
980 ws->ws_state[0].cur_grp = 0;
981 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
982 ws->ws_state[1].cur_grp = 0;
983 ws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;
985 struct otx2_ssogws *ws;
987 ws = event_dev->data->ports[i];
991 ws->cur_tt = SSO_SYNC_EMPTY;
997 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
998 struct otx2_ssogws temp_ws;
1000 memcpy(&temp_ws, &ws->ws_state[0],
1001 sizeof(struct otx2_ssogws_state));
1002 for (i = 0; i < dev->nb_event_queues; i++) {
1003 /* Consume all the events through HWS0 */
1004 ssogws_flush_events(&temp_ws, i, ws->grps_base[i],
1005 otx2_handle_event, event_dev);
1006 /* Enable/Disable SSO GGRP */
1007 otx2_write64(enable, ws->grps_base[i] +
1010 ws->ws_state[0].cur_grp = 0;
1011 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1013 struct otx2_ssogws *ws = event_dev->data->ports[0];
1015 for (i = 0; i < dev->nb_event_queues; i++) {
1016 /* Consume all the events through HWS0 */
1017 ssogws_flush_events(ws, i, ws->grps_base[i],
1018 otx2_handle_event, event_dev);
1019 /* Enable/Disable SSO GGRP */
1020 otx2_write64(enable, ws->grps_base[i] +
1024 ws->cur_tt = SSO_SYNC_EMPTY;
1027 /* reset SSO GWS cache */
1028 otx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);
1029 otx2_mbox_process(dev->mbox);
1033 otx2_sso_start(struct rte_eventdev *event_dev)
1036 sso_qos_cfg(event_dev);
1037 sso_cleanup(event_dev, 1);
1038 sso_fastpath_fns_set(event_dev);
1043 /* Initialize and register event driver with DPDK Application */
1044 static struct rte_eventdev_ops otx2_sso_ops = {
1045 .dev_infos_get = otx2_sso_info_get,
1046 .dev_configure = otx2_sso_configure,
1047 .queue_def_conf = otx2_sso_queue_def_conf,
1048 .queue_setup = otx2_sso_queue_setup,
1049 .queue_release = otx2_sso_queue_release,
1050 .port_def_conf = otx2_sso_port_def_conf,
1051 .port_setup = otx2_sso_port_setup,
1052 .port_release = otx2_sso_port_release,
1053 .port_link = otx2_sso_port_link,
1054 .port_unlink = otx2_sso_port_unlink,
1055 .timeout_ticks = otx2_sso_timeout_ticks,
1057 .xstats_get = otx2_sso_xstats_get,
1058 .xstats_reset = otx2_sso_xstats_reset,
1059 .xstats_get_names = otx2_sso_xstats_get_names,
1061 .dump = otx2_sso_dump,
1062 .dev_start = otx2_sso_start,
1065 #define OTX2_SSO_XAE_CNT "xae_cnt"
1066 #define OTX2_SSO_SINGLE_WS "single_ws"
1067 #define OTX2_SSO_GGRP_QOS "qos"
1070 parse_queue_param(char *value, void *opaque)
1072 struct otx2_sso_qos queue_qos = {0};
1073 uint8_t *val = (uint8_t *)&queue_qos;
1074 struct otx2_sso_evdev *dev = opaque;
1075 char *tok = strtok(value, "-");
1080 while (tok != NULL) {
1082 tok = strtok(NULL, "-");
1086 if (val != (&queue_qos.iaq_prcnt + 1)) {
1087 otx2_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
1091 dev->qos_queue_cnt++;
1092 dev->qos_parse_data = rte_realloc(dev->qos_parse_data,
1093 sizeof(struct otx2_sso_qos) *
1094 dev->qos_queue_cnt, 0);
1095 dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
1099 parse_qos_list(const char *value, void *opaque)
1101 char *s = strdup(value);
1112 if (start < end && *start) {
1114 parse_queue_param(start + 1, opaque);
1125 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
1129 /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
1130 * isn't allowed. Everything is expressed in percentages, 0 represents
1133 parse_qos_list(value, opaque);
1139 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
1141 struct rte_kvargs *kvlist;
1142 uint8_t single_ws = 0;
1144 if (devargs == NULL)
1146 kvlist = rte_kvargs_parse(devargs->args, NULL);
1150 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
1152 rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
1154 rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
1157 dev->dual_ws = !single_ws;
1158 rte_kvargs_free(kvlist);
1162 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1164 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1165 sizeof(struct otx2_sso_evdev),
1170 otx2_sso_remove(struct rte_pci_device *pci_dev)
1172 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
1175 static const struct rte_pci_id pci_sso_map[] = {
1177 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1178 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
1185 static struct rte_pci_driver pci_sso = {
1186 .id_table = pci_sso_map,
1187 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1188 .probe = otx2_sso_probe,
1189 .remove = otx2_sso_remove,
1193 otx2_sso_init(struct rte_eventdev *event_dev)
1195 struct free_rsrcs_rsp *rsrc_cnt;
1196 struct rte_pci_device *pci_dev;
1197 struct otx2_sso_evdev *dev;
1200 event_dev->dev_ops = &otx2_sso_ops;
1201 /* For secondary processes, the primary has done all the work */
1202 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1203 sso_fastpath_fns_set(event_dev);
1207 dev = sso_pmd_priv(event_dev);
1209 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1211 /* Initialize the base otx2_dev object */
1212 rc = otx2_dev_init(pci_dev, dev);
1214 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1218 /* Get SSO and SSOW MSIX rsrc cnt */
1219 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
1220 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
1222 otx2_err("Unable to get free rsrc count");
1223 goto otx2_dev_uninit;
1225 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
1226 rsrc_cnt->ssow, rsrc_cnt->npa);
1228 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
1229 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
1230 /* Grab the NPA LF if required */
1231 rc = otx2_npa_lf_init(pci_dev, dev);
1233 otx2_err("Unable to init NPA lf. It might not be provisioned");
1234 goto otx2_dev_uninit;
1237 dev->drv_inited = true;
1238 dev->is_timeout_deq = 0;
1239 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1240 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1241 dev->max_num_events = -1;
1242 dev->nb_event_queues = 0;
1243 dev->nb_event_ports = 0;
1245 if (!dev->max_event_ports || !dev->max_event_queues) {
1246 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1247 dev->max_event_queues, dev->max_event_ports);
1249 goto otx2_npa_lf_uninit;
1253 sso_parse_devargs(dev, pci_dev->device.devargs);
1255 otx2_sso_dbg("Using dual workslot mode");
1256 dev->max_event_ports = dev->max_event_ports / 2;
1258 otx2_sso_dbg("Using single workslot mode");
1261 otx2_sso_pf_func_set(dev->pf_func);
1262 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1263 event_dev->data->name, dev->max_event_queues,
1264 dev->max_event_ports);
1272 otx2_dev_fini(pci_dev, dev);
1278 otx2_sso_fini(struct rte_eventdev *event_dev)
1280 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1281 struct rte_pci_device *pci_dev;
1283 /* For secondary processes, nothing to be done */
1284 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1287 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1289 if (!dev->drv_inited)
1292 dev->drv_inited = false;
1296 if (otx2_npa_lf_active(dev)) {
1297 otx2_info("Common resource in use by other devices");
1301 otx2_dev_fini(pci_dev, dev);
1306 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1307 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1308 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1309 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
1310 OTX2_SSO_SINGLE_WS "=1"
1311 OTX2_SSO_GGRP_QOS "=<string>");