1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
8 #include <rte_common.h>
10 #include <rte_eventdev_pmd_pci.h>
11 #include <rte_kvargs.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_evdev_stats.h"
16 #include "otx2_evdev.h"
18 #include "otx2_tim_evdev.h"
21 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
23 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
24 uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
25 struct otx2_mbox *mbox = dev->mbox;
26 struct msix_offset_rsp *msix_rsp;
29 /* Get SSO and SSOW MSIX vector offsets */
30 otx2_mbox_alloc_msg_msix_offset(mbox);
31 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
33 for (i = 0; i < nb_ports; i++)
34 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
36 for (i = 0; i < dev->nb_event_queues; i++)
37 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
43 sso_fastpath_fns_set(struct rte_eventdev *event_dev)
45 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
47 const event_dequeue_t ssogws_deq[2][2][2][2][2][2] = {
48 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
49 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_ ##name,
50 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
54 const event_dequeue_burst_t ssogws_deq_burst[2][2][2][2][2][2] = {
55 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
56 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_burst_ ##name,
57 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
61 const event_dequeue_t ssogws_deq_timeout[2][2][2][2][2][2] = {
62 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
63 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_timeout_ ##name,
64 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
68 const event_dequeue_burst_t
69 ssogws_deq_timeout_burst[2][2][2][2][2][2] = {
70 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
71 [f5][f4][f3][f2][f1][f0] = \
72 otx2_ssogws_deq_timeout_burst_ ##name,
73 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
77 const event_dequeue_t ssogws_deq_seg[2][2][2][2][2][2] = {
78 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
79 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_ ##name,
80 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
84 const event_dequeue_burst_t ssogws_deq_seg_burst[2][2][2][2][2][2] = {
85 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
86 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_burst_ ##name,
87 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
91 const event_dequeue_t ssogws_deq_seg_timeout[2][2][2][2][2][2] = {
92 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
93 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_timeout_ ##name,
94 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
98 const event_dequeue_burst_t
99 ssogws_deq_seg_timeout_burst[2][2][2][2][2][2] = {
100 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
101 [f5][f4][f3][f2][f1][f0] = \
102 otx2_ssogws_deq_seg_timeout_burst_ ##name,
103 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
109 const event_dequeue_t ssogws_dual_deq[2][2][2][2][2][2] = {
110 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
111 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_ ##name,
112 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
116 const event_dequeue_burst_t ssogws_dual_deq_burst[2][2][2][2][2][2] = {
117 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
118 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_burst_ ##name,
119 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
123 const event_dequeue_t ssogws_dual_deq_timeout[2][2][2][2][2][2] = {
124 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
125 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_timeout_ ##name,
126 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
130 const event_dequeue_burst_t
131 ssogws_dual_deq_timeout_burst[2][2][2][2][2][2] = {
132 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
133 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_timeout_burst_ ##name,
134 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
138 const event_dequeue_t ssogws_dual_deq_seg[2][2][2][2][2][2] = {
139 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
140 [f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_seg_ ##name,
141 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
145 const event_dequeue_burst_t
146 ssogws_dual_deq_seg_burst[2][2][2][2][2][2] = {
147 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
148 [f5][f4][f3][f2][f1][f0] = \
149 otx2_ssogws_dual_deq_seg_burst_ ##name,
150 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
154 const event_dequeue_t ssogws_dual_deq_seg_timeout[2][2][2][2][2][2] = {
155 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
156 [f5][f4][f3][f2][f1][f0] = \
157 otx2_ssogws_dual_deq_seg_timeout_ ##name,
158 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
162 const event_dequeue_burst_t
163 ssogws_dual_deq_seg_timeout_burst[2][2][2][2][2][2] = {
164 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
165 [f5][f4][f3][f2][f1][f0] = \
166 otx2_ssogws_dual_deq_seg_timeout_burst_ ##name,
167 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
172 const event_tx_adapter_enqueue ssogws_tx_adptr_enq[2][2][2][2][2] = {
173 #define T(name, f4, f3, f2, f1, f0, sz, flags) \
174 [f4][f3][f2][f1][f0] = otx2_ssogws_tx_adptr_enq_ ## name,
175 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
179 const event_tx_adapter_enqueue
180 ssogws_tx_adptr_enq_seg[2][2][2][2][2] = {
181 #define T(name, f4, f3, f2, f1, f0, sz, flags) \
182 [f4][f3][f2][f1][f0] = otx2_ssogws_tx_adptr_enq_seg_ ## name,
183 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
187 const event_tx_adapter_enqueue
188 ssogws_dual_tx_adptr_enq[2][2][2][2][2] = {
189 #define T(name, f4, f3, f2, f1, f0, sz, flags) \
190 [f4][f3][f2][f1][f0] = otx2_ssogws_dual_tx_adptr_enq_ ## name,
191 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
195 const event_tx_adapter_enqueue
196 ssogws_dual_tx_adptr_enq_seg[2][2][2][2][2] = {
197 #define T(name, f4, f3, f2, f1, f0, sz, flags) \
198 [f4][f3][f2][f1][f0] = \
199 otx2_ssogws_dual_tx_adptr_enq_seg_ ## name,
200 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
204 event_dev->enqueue = otx2_ssogws_enq;
205 event_dev->enqueue_burst = otx2_ssogws_enq_burst;
206 event_dev->enqueue_new_burst = otx2_ssogws_enq_new_burst;
207 event_dev->enqueue_forward_burst = otx2_ssogws_enq_fwd_burst;
208 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
209 event_dev->dequeue = ssogws_deq_seg
210 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
211 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
212 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
213 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
214 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
215 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
216 event_dev->dequeue_burst = ssogws_deq_seg_burst
217 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
218 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
219 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
220 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
221 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
222 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
223 if (dev->is_timeout_deq) {
224 event_dev->dequeue = ssogws_deq_seg_timeout
225 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
226 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
227 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
228 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
229 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
230 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
231 event_dev->dequeue_burst =
232 ssogws_deq_seg_timeout_burst
233 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
234 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
235 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
236 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
237 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
238 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
241 event_dev->dequeue = ssogws_deq
242 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
243 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
244 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
245 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
246 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
247 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
248 event_dev->dequeue_burst = ssogws_deq_burst
249 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
250 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
251 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
252 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
253 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
254 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
255 if (dev->is_timeout_deq) {
256 event_dev->dequeue = ssogws_deq_timeout
257 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
258 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
259 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
260 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
261 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
262 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
263 event_dev->dequeue_burst =
264 ssogws_deq_timeout_burst
265 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
266 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
267 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
268 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
269 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
270 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
274 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
275 /* [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
276 event_dev->txa_enqueue = ssogws_tx_adptr_enq_seg
277 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
278 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
279 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
280 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
281 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
283 event_dev->txa_enqueue = ssogws_tx_adptr_enq
284 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
285 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
286 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
287 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
288 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
292 event_dev->enqueue = otx2_ssogws_dual_enq;
293 event_dev->enqueue_burst = otx2_ssogws_dual_enq_burst;
294 event_dev->enqueue_new_burst =
295 otx2_ssogws_dual_enq_new_burst;
296 event_dev->enqueue_forward_burst =
297 otx2_ssogws_dual_enq_fwd_burst;
299 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
300 event_dev->dequeue = ssogws_dual_deq_seg
301 [!!(dev->rx_offloads &
302 NIX_RX_OFFLOAD_TSTAMP_F)]
303 [!!(dev->rx_offloads &
304 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
305 [!!(dev->rx_offloads &
306 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
307 [!!(dev->rx_offloads &
308 NIX_RX_OFFLOAD_CHECKSUM_F)]
309 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
310 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
311 event_dev->dequeue_burst = ssogws_dual_deq_seg_burst
312 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
313 [!!(dev->rx_offloads &
314 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
315 [!!(dev->rx_offloads &
316 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
317 [!!(dev->rx_offloads &
318 NIX_RX_OFFLOAD_CHECKSUM_F)]
319 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
320 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
321 if (dev->is_timeout_deq) {
323 ssogws_dual_deq_seg_timeout
324 [!!(dev->rx_offloads &
325 NIX_RX_OFFLOAD_TSTAMP_F)]
326 [!!(dev->rx_offloads &
327 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
328 [!!(dev->rx_offloads &
329 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
330 [!!(dev->rx_offloads &
331 NIX_RX_OFFLOAD_CHECKSUM_F)]
332 [!!(dev->rx_offloads &
333 NIX_RX_OFFLOAD_PTYPE_F)]
334 [!!(dev->rx_offloads &
335 NIX_RX_OFFLOAD_RSS_F)];
336 event_dev->dequeue_burst =
337 ssogws_dual_deq_seg_timeout_burst
338 [!!(dev->rx_offloads &
339 NIX_RX_OFFLOAD_TSTAMP_F)]
340 [!!(dev->rx_offloads &
341 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
342 [!!(dev->rx_offloads &
343 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
344 [!!(dev->rx_offloads &
345 NIX_RX_OFFLOAD_CHECKSUM_F)]
346 [!!(dev->rx_offloads &
347 NIX_RX_OFFLOAD_PTYPE_F)]
348 [!!(dev->rx_offloads &
349 NIX_RX_OFFLOAD_RSS_F)];
352 event_dev->dequeue = ssogws_dual_deq
353 [!!(dev->rx_offloads &
354 NIX_RX_OFFLOAD_TSTAMP_F)]
355 [!!(dev->rx_offloads &
356 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
357 [!!(dev->rx_offloads &
358 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
359 [!!(dev->rx_offloads &
360 NIX_RX_OFFLOAD_CHECKSUM_F)]
361 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
362 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
363 event_dev->dequeue_burst = ssogws_dual_deq_burst
364 [!!(dev->rx_offloads &
365 NIX_RX_OFFLOAD_TSTAMP_F)]
366 [!!(dev->rx_offloads &
367 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
368 [!!(dev->rx_offloads &
369 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
370 [!!(dev->rx_offloads &
371 NIX_RX_OFFLOAD_CHECKSUM_F)]
372 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
373 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
374 if (dev->is_timeout_deq) {
376 ssogws_dual_deq_timeout
377 [!!(dev->rx_offloads &
378 NIX_RX_OFFLOAD_TSTAMP_F)]
379 [!!(dev->rx_offloads &
380 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
381 [!!(dev->rx_offloads &
382 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
383 [!!(dev->rx_offloads &
384 NIX_RX_OFFLOAD_CHECKSUM_F)]
385 [!!(dev->rx_offloads &
386 NIX_RX_OFFLOAD_PTYPE_F)]
387 [!!(dev->rx_offloads &
388 NIX_RX_OFFLOAD_RSS_F)];
389 event_dev->dequeue_burst =
390 ssogws_dual_deq_timeout_burst
391 [!!(dev->rx_offloads &
392 NIX_RX_OFFLOAD_TSTAMP_F)]
393 [!!(dev->rx_offloads &
394 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
395 [!!(dev->rx_offloads &
396 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
397 [!!(dev->rx_offloads &
398 NIX_RX_OFFLOAD_CHECKSUM_F)]
399 [!!(dev->rx_offloads &
400 NIX_RX_OFFLOAD_PTYPE_F)]
401 [!!(dev->rx_offloads &
402 NIX_RX_OFFLOAD_RSS_F)];
406 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
407 /* [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
408 event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq_seg
409 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
410 [!!(dev->tx_offloads &
411 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
412 [!!(dev->tx_offloads &
413 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
414 [!!(dev->tx_offloads &
415 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
416 [!!(dev->tx_offloads &
417 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
419 event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq
420 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
421 [!!(dev->tx_offloads &
422 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
423 [!!(dev->tx_offloads &
424 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
425 [!!(dev->tx_offloads &
426 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
427 [!!(dev->tx_offloads &
428 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
435 otx2_sso_info_get(struct rte_eventdev *event_dev,
436 struct rte_event_dev_info *dev_info)
438 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
440 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
441 dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
442 dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
443 dev_info->max_event_queues = dev->max_event_queues;
444 dev_info->max_event_queue_flows = (1ULL << 20);
445 dev_info->max_event_queue_priority_levels = 8;
446 dev_info->max_event_priority_levels = 1;
447 dev_info->max_event_ports = dev->max_event_ports;
448 dev_info->max_event_port_dequeue_depth = 1;
449 dev_info->max_event_port_enqueue_depth = 1;
450 dev_info->max_num_events = dev->max_num_events;
451 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
452 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
453 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
454 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
455 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
456 RTE_EVENT_DEV_CAP_NONSEQ_MODE;
460 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
462 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
466 val |= 0ULL << 12; /* SET 0 */
467 val |= 0x8000800080000000; /* Dont modify rest of the masks */
468 val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */
470 otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
474 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
475 const uint8_t queues[], const uint8_t priorities[],
478 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
482 RTE_SET_USED(priorities);
483 for (link = 0; link < nb_links; link++) {
485 struct otx2_ssogws_dual *ws = port;
488 sso_port_link_modify((struct otx2_ssogws *)
489 &ws->ws_state[0], queues[link], true);
490 sso_port_link_modify((struct otx2_ssogws *)
491 &ws->ws_state[1], queues[link], true);
493 struct otx2_ssogws *ws = port;
496 sso_port_link_modify(ws, queues[link], true);
499 sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
501 return (int)nb_links;
505 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
506 uint8_t queues[], uint16_t nb_unlinks)
508 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
512 for (unlink = 0; unlink < nb_unlinks; unlink++) {
514 struct otx2_ssogws_dual *ws = port;
517 sso_port_link_modify((struct otx2_ssogws *)
518 &ws->ws_state[0], queues[unlink],
520 sso_port_link_modify((struct otx2_ssogws *)
521 &ws->ws_state[1], queues[unlink],
524 struct otx2_ssogws *ws = port;
527 sso_port_link_modify(ws, queues[unlink], false);
530 sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
532 return (int)nb_unlinks;
536 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
537 uint16_t nb_lf, uint8_t attach)
540 struct rsrc_attach_req *req;
542 req = otx2_mbox_alloc_msg_attach_resources(mbox);
554 if (otx2_mbox_process(mbox) < 0)
557 struct rsrc_detach_req *req;
559 req = otx2_mbox_alloc_msg_detach_resources(mbox);
571 if (otx2_mbox_process(mbox) < 0)
579 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
580 enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
589 struct sso_lf_alloc_req *req_ggrp;
590 req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
591 req_ggrp->hwgrps = nb_lf;
596 struct ssow_lf_alloc_req *req_hws;
597 req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
598 req_hws->hws = nb_lf;
608 struct sso_lf_free_req *req_ggrp;
609 req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
610 req_ggrp->hwgrps = nb_lf;
615 struct ssow_lf_free_req *req_hws;
616 req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
617 req_hws->hws = nb_lf;
625 rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
629 if (alloc && type == SSO_LF_GGRP) {
630 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
632 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
633 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
634 dev->iue = rsp_ggrp->in_unit_entries;
641 otx2_sso_port_release(void *port)
647 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
649 RTE_SET_USED(event_dev);
650 RTE_SET_USED(queue_id);
654 sso_clr_links(const struct rte_eventdev *event_dev)
656 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
659 for (i = 0; i < dev->nb_event_ports; i++) {
661 struct otx2_ssogws_dual *ws;
663 ws = event_dev->data->ports[i];
664 for (j = 0; j < dev->nb_event_queues; j++) {
665 sso_port_link_modify((struct otx2_ssogws *)
666 &ws->ws_state[0], j, false);
667 sso_port_link_modify((struct otx2_ssogws *)
668 &ws->ws_state[1], j, false);
671 struct otx2_ssogws *ws;
673 ws = event_dev->data->ports[i];
674 for (j = 0; j < dev->nb_event_queues; j++)
675 sso_port_link_modify(ws, j, false);
681 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
683 ws->tag_op = base + SSOW_LF_GWS_TAG;
684 ws->wqp_op = base + SSOW_LF_GWS_WQP;
685 ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK;
686 ws->swtp_op = base + SSOW_LF_GWS_SWTP;
687 ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;
688 ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
692 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
694 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
695 struct otx2_mbox *mbox = dev->mbox;
700 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
702 nb_lf = dev->nb_event_ports * 2;
703 /* Ask AF to attach required LFs. */
704 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
706 otx2_err("Failed to attach SSO GWS LF");
710 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
711 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
712 otx2_err("Failed to init SSO GWS LF");
716 for (i = 0; i < dev->nb_event_ports; i++) {
717 struct otx2_ssogws_dual *ws;
720 /* Free memory prior to re-allocation if needed */
721 if (event_dev->data->ports[i] != NULL) {
722 ws = event_dev->data->ports[i];
727 /* Allocate event port memory */
728 ws = rte_zmalloc_socket("otx2_sso_ws",
729 sizeof(struct otx2_ssogws_dual),
731 event_dev->data->socket_id);
733 otx2_err("Failed to alloc memory for port=%d", i);
739 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
740 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
743 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
744 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
747 event_dev->data->ports[i] = ws;
751 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
752 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
759 sso_configure_ports(const struct rte_eventdev *event_dev)
761 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
762 struct otx2_mbox *mbox = dev->mbox;
766 otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
768 nb_lf = dev->nb_event_ports;
769 /* Ask AF to attach required LFs. */
770 rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
772 otx2_err("Failed to attach SSO GWS LF");
776 if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
777 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
778 otx2_err("Failed to init SSO GWS LF");
782 for (i = 0; i < nb_lf; i++) {
783 struct otx2_ssogws *ws;
786 /* Free memory prior to re-allocation if needed */
787 if (event_dev->data->ports[i] != NULL) {
788 ws = event_dev->data->ports[i];
793 /* Allocate event port memory */
794 ws = rte_zmalloc_socket("otx2_sso_ws",
795 sizeof(struct otx2_ssogws),
797 event_dev->data->socket_id);
799 otx2_err("Failed to alloc memory for port=%d", i);
805 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
806 sso_set_port_ops(ws, base);
808 event_dev->data->ports[i] = ws;
812 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
813 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
820 sso_configure_queues(const struct rte_eventdev *event_dev)
822 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
823 struct otx2_mbox *mbox = dev->mbox;
827 otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
829 nb_lf = dev->nb_event_queues;
830 /* Ask AF to attach required LFs. */
831 rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
833 otx2_err("Failed to attach SSO GGRP LF");
837 if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
838 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
839 otx2_err("Failed to init SSO GGRP LF");
847 sso_xaq_allocate(struct otx2_sso_evdev *dev)
849 const struct rte_memzone *mz;
850 struct npa_aura_s *aura;
851 static int reconfig_cnt;
852 char pool_name[RTE_MEMZONE_NAMESIZE];
857 rte_mempool_free(dev->xaq_pool);
860 * Allocate memory for Add work backpressure.
862 mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
864 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
866 sizeof(struct npa_aura_s),
868 RTE_MEMZONE_IOVA_CONTIG,
871 otx2_err("Failed to allocate mem for fcmem");
875 dev->fc_iova = mz->iova;
876 dev->fc_mem = mz->addr;
878 aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
879 memset(aura, 0, sizeof(struct npa_aura_s));
882 aura->fc_addr = dev->fc_iova;
883 aura->fc_hyst_bits = 0; /* Store count on all updates */
885 /* Taken from HRM 14.3.3(4) */
886 xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
888 xaq_cnt += dev->xae_cnt / dev->xae_waes;
889 else if (dev->adptr_xae_cnt)
890 xaq_cnt += (dev->adptr_xae_cnt / dev->xae_waes) +
891 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
893 xaq_cnt += (dev->iue / dev->xae_waes) +
894 (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
896 otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
897 /* Setup XAQ based on number of nb queues. */
898 snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
899 dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
900 xaq_cnt, dev->xaq_buf_size, 0, 0,
903 if (dev->xaq_pool == NULL) {
904 otx2_err("Unable to create empty mempool.");
905 rte_memzone_free(mz);
909 rc = rte_mempool_set_ops_byname(dev->xaq_pool,
910 rte_mbuf_platform_mempool_ops(), aura);
912 otx2_err("Unable to set xaqpool ops.");
916 rc = rte_mempool_populate_default(dev->xaq_pool);
918 otx2_err("Unable to set populate xaqpool.");
922 /* When SW does addwork (enqueue) check if there is space in XAQ by
923 * comparing fc_addr above against the xaq_lmt calculated below.
924 * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
925 * to request XAQ to cache them even before enqueue is called.
927 dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
928 dev->nb_event_queues);
929 dev->nb_xaq_cfg = xaq_cnt;
933 rte_mempool_free(dev->xaq_pool);
934 rte_memzone_free(mz);
939 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
941 struct otx2_mbox *mbox = dev->mbox;
942 struct sso_hw_setconfig *req;
944 otx2_sso_dbg("Configuring XAQ for GGRPs");
945 req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
946 req->npa_pf_func = otx2_npa_pf_func_get();
947 req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
948 req->hwgrps = dev->nb_event_queues;
950 return otx2_mbox_process(mbox);
954 sso_lf_teardown(struct otx2_sso_evdev *dev,
955 enum otx2_sso_lf_type lf_type)
961 nb_lf = dev->nb_event_queues;
964 nb_lf = dev->nb_event_ports;
965 nb_lf *= dev->dual_ws ? 2 : 1;
971 sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
972 sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
976 otx2_sso_configure(const struct rte_eventdev *event_dev)
978 struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
979 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
984 deq_tmo_ns = conf->dequeue_timeout_ns;
987 deq_tmo_ns = dev->min_dequeue_timeout_ns;
989 if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
990 deq_tmo_ns > dev->max_dequeue_timeout_ns) {
991 otx2_err("Unsupported dequeue timeout requested");
995 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
996 dev->is_timeout_deq = 1;
998 dev->deq_tmo_ns = deq_tmo_ns;
1000 if (conf->nb_event_ports > dev->max_event_ports ||
1001 conf->nb_event_queues > dev->max_event_queues) {
1002 otx2_err("Unsupported event queues/ports requested");
1006 if (conf->nb_event_port_dequeue_depth > 1) {
1007 otx2_err("Unsupported event port deq depth requested");
1011 if (conf->nb_event_port_enqueue_depth > 1) {
1012 otx2_err("Unsupported event port enq depth requested");
1016 if (dev->configured)
1017 sso_unregister_irqs(event_dev);
1019 if (dev->nb_event_queues) {
1020 /* Finit any previous queues. */
1021 sso_lf_teardown(dev, SSO_LF_GGRP);
1023 if (dev->nb_event_ports) {
1024 /* Finit any previous ports. */
1025 sso_lf_teardown(dev, SSO_LF_GWS);
1028 dev->nb_event_queues = conf->nb_event_queues;
1029 dev->nb_event_ports = conf->nb_event_ports;
1032 rc = sso_configure_dual_ports(event_dev);
1034 rc = sso_configure_ports(event_dev);
1037 otx2_err("Failed to configure event ports");
1041 if (sso_configure_queues(event_dev) < 0) {
1042 otx2_err("Failed to configure event queues");
1047 if (sso_xaq_allocate(dev) < 0) {
1049 goto teardown_hwggrp;
1052 /* Clear any prior port-queue mapping. */
1053 sso_clr_links(event_dev);
1054 rc = sso_ggrp_alloc_xaq(dev);
1056 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1057 goto teardown_hwggrp;
1060 rc = sso_get_msix_offsets(event_dev);
1062 otx2_err("Failed to get msix offsets %d", rc);
1063 goto teardown_hwggrp;
1066 rc = sso_register_irqs(event_dev);
1068 otx2_err("Failed to register irq %d", rc);
1069 goto teardown_hwggrp;
1072 dev->configured = 1;
1077 sso_lf_teardown(dev, SSO_LF_GGRP);
1079 sso_lf_teardown(dev, SSO_LF_GWS);
1080 dev->nb_event_queues = 0;
1081 dev->nb_event_ports = 0;
1082 dev->configured = 0;
1087 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
1088 struct rte_event_queue_conf *queue_conf)
1090 RTE_SET_USED(event_dev);
1091 RTE_SET_USED(queue_id);
1093 queue_conf->nb_atomic_flows = (1ULL << 20);
1094 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
1095 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
1096 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
1100 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
1101 const struct rte_event_queue_conf *queue_conf)
1103 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1104 struct otx2_mbox *mbox = dev->mbox;
1105 struct sso_grp_priority *req;
1108 sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
1110 req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
1111 req->grp = queue_id;
1113 req->affinity = 0xFF;
1114 /* Normalize <0-255> to <0-7> */
1115 req->priority = queue_conf->priority / 32;
1117 rc = otx2_mbox_process(mbox);
1119 otx2_err("Failed to set priority queue=%d", queue_id);
1127 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
1128 struct rte_event_port_conf *port_conf)
1130 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1132 RTE_SET_USED(port_id);
1133 port_conf->new_event_threshold = dev->max_num_events;
1134 port_conf->dequeue_depth = 1;
1135 port_conf->enqueue_depth = 1;
1139 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
1140 const struct rte_event_port_conf *port_conf)
1142 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1143 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
1147 sso_func_trace("Port=%d", port_id);
1148 RTE_SET_USED(port_conf);
1150 if (event_dev->data->ports[port_id] == NULL) {
1151 otx2_err("Invalid port Id %d", port_id);
1155 for (q = 0; q < dev->nb_event_queues; q++) {
1156 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
1157 if (grps_base[q] == 0) {
1158 otx2_err("Failed to get grp[%d] base addr", q);
1163 /* Set get_work timeout for HWS */
1164 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
1167 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
1169 rte_memcpy(ws->grps_base, grps_base,
1170 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1171 ws->fc_mem = dev->fc_mem;
1172 ws->xaq_lmt = dev->xaq_lmt;
1173 ws->tstamp = dev->tstamp;
1174 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1175 ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1176 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1177 ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1179 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
1180 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1182 rte_memcpy(ws->grps_base, grps_base,
1183 sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1184 ws->fc_mem = dev->fc_mem;
1185 ws->xaq_lmt = dev->xaq_lmt;
1186 ws->tstamp = dev->tstamp;
1187 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
1190 otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
1196 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
1197 uint64_t *tmo_ticks)
1199 RTE_SET_USED(event_dev);
1200 *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
1206 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
1208 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1210 fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base);
1211 fprintf(f, "SSOW_LF_GWS_LINKS 0x%" PRIx64 "\n",
1212 otx2_read64(base + SSOW_LF_GWS_LINKS));
1213 fprintf(f, "SSOW_LF_GWS_PENDWQP 0x%" PRIx64 "\n",
1214 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
1215 fprintf(f, "SSOW_LF_GWS_PENDSTATE 0x%" PRIx64 "\n",
1216 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
1217 fprintf(f, "SSOW_LF_GWS_NW_TIM 0x%" PRIx64 "\n",
1218 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
1219 fprintf(f, "SSOW_LF_GWS_TAG 0x%" PRIx64 "\n",
1220 otx2_read64(base + SSOW_LF_GWS_TAG));
1221 fprintf(f, "SSOW_LF_GWS_WQP 0x%" PRIx64 "\n",
1222 otx2_read64(base + SSOW_LF_GWS_TAG));
1223 fprintf(f, "SSOW_LF_GWS_SWTP 0x%" PRIx64 "\n",
1224 otx2_read64(base + SSOW_LF_GWS_SWTP));
1225 fprintf(f, "SSOW_LF_GWS_PENDTAG 0x%" PRIx64 "\n",
1226 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
1230 ssoggrp_dump(uintptr_t base, FILE *f)
1232 fprintf(f, "SSO_LF_GGRP Base addr 0x%" PRIx64 "\n", (uint64_t)base);
1233 fprintf(f, "SSO_LF_GGRP_QCTL 0x%" PRIx64 "\n",
1234 otx2_read64(base + SSO_LF_GGRP_QCTL));
1235 fprintf(f, "SSO_LF_GGRP_XAQ_CNT 0x%" PRIx64 "\n",
1236 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
1237 fprintf(f, "SSO_LF_GGRP_INT_THR 0x%" PRIx64 "\n",
1238 otx2_read64(base + SSO_LF_GGRP_INT_THR));
1239 fprintf(f, "SSO_LF_GGRP_INT_CNT 0x%" PRIX64 "\n",
1240 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
1241 fprintf(f, "SSO_LF_GGRP_AQ_CNT 0x%" PRIX64 "\n",
1242 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
1243 fprintf(f, "SSO_LF_GGRP_AQ_THR 0x%" PRIX64 "\n",
1244 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
1245 fprintf(f, "SSO_LF_GGRP_MISC_CNT 0x%" PRIx64 "\n",
1246 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
1250 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
1252 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1256 fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
1257 "dual_ws" : "single_ws");
1258 /* Dump SSOW registers */
1259 for (port = 0; port < dev->nb_event_ports; port++) {
1261 struct otx2_ssogws_dual *ws =
1262 event_dev->data->ports[port];
1264 fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
1266 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
1267 fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
1269 ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
1271 fprintf(f, "[%s]SSO single workslot[%d] dump\n",
1273 ssogws_dump(event_dev->data->ports[port], f);
1277 /* Dump SSO registers */
1278 for (queue = 0; queue < dev->nb_event_queues; queue++) {
1279 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
1281 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1282 ssoggrp_dump(ws->grps_base[queue], f);
1284 struct otx2_ssogws *ws = event_dev->data->ports[0];
1285 ssoggrp_dump(ws->grps_base[queue], f);
1291 otx2_handle_event(void *arg, struct rte_event event)
1293 struct rte_eventdev *event_dev = arg;
1295 if (event_dev->dev_ops->dev_stop_flush != NULL)
1296 event_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,
1297 event, event_dev->data->dev_stop_flush_arg);
1301 sso_qos_cfg(struct rte_eventdev *event_dev)
1303 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1304 struct sso_grp_qos_cfg *req;
1307 for (i = 0; i < dev->qos_queue_cnt; i++) {
1308 uint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
1309 uint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
1310 uint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
1312 if (dev->qos_parse_data[i].queue >= dev->nb_event_queues)
1315 req = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);
1316 req->xaq_limit = (dev->nb_xaq_cfg *
1317 (xaq_prcnt ? xaq_prcnt : 100)) / 100;
1318 req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *
1319 (iaq_prcnt ? iaq_prcnt : 100)) / 100;
1320 req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *
1321 (taq_prcnt ? taq_prcnt : 100)) / 100;
1324 if (dev->qos_queue_cnt)
1325 otx2_mbox_process(dev->mbox);
1329 sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
1331 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1334 for (i = 0; i < dev->nb_event_ports; i++) {
1336 struct otx2_ssogws_dual *ws;
1338 ws = event_dev->data->ports[i];
1339 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);
1340 ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
1343 ws->ws_state[0].cur_grp = 0;
1344 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1345 ws->ws_state[1].cur_grp = 0;
1346 ws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;
1348 struct otx2_ssogws *ws;
1350 ws = event_dev->data->ports[i];
1354 ws->cur_tt = SSO_SYNC_EMPTY;
1360 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1361 struct otx2_ssogws temp_ws;
1363 memcpy(&temp_ws, &ws->ws_state[0],
1364 sizeof(struct otx2_ssogws_state));
1365 for (i = 0; i < dev->nb_event_queues; i++) {
1366 /* Consume all the events through HWS0 */
1367 ssogws_flush_events(&temp_ws, i, ws->grps_base[i],
1368 otx2_handle_event, event_dev);
1369 /* Enable/Disable SSO GGRP */
1370 otx2_write64(enable, ws->grps_base[i] +
1373 ws->ws_state[0].cur_grp = 0;
1374 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1376 struct otx2_ssogws *ws = event_dev->data->ports[0];
1378 for (i = 0; i < dev->nb_event_queues; i++) {
1379 /* Consume all the events through HWS0 */
1380 ssogws_flush_events(ws, i, ws->grps_base[i],
1381 otx2_handle_event, event_dev);
1382 /* Enable/Disable SSO GGRP */
1383 otx2_write64(enable, ws->grps_base[i] +
1387 ws->cur_tt = SSO_SYNC_EMPTY;
1390 /* reset SSO GWS cache */
1391 otx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);
1392 otx2_mbox_process(dev->mbox);
1396 sso_xae_reconfigure(struct rte_eventdev *event_dev)
1398 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1399 struct rte_mempool *prev_xaq_pool;
1402 if (event_dev->data->dev_started)
1403 sso_cleanup(event_dev, 0);
1405 prev_xaq_pool = dev->xaq_pool;
1406 dev->xaq_pool = NULL;
1407 rc = sso_xaq_allocate(dev);
1409 otx2_err("Failed to alloc xaq pool %d", rc);
1410 rte_mempool_free(prev_xaq_pool);
1413 rc = sso_ggrp_alloc_xaq(dev);
1415 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1416 rte_mempool_free(prev_xaq_pool);
1420 rte_mempool_free(prev_xaq_pool);
1422 if (event_dev->data->dev_started)
1423 sso_cleanup(event_dev, 1);
1429 otx2_sso_start(struct rte_eventdev *event_dev)
1432 sso_qos_cfg(event_dev);
1433 sso_cleanup(event_dev, 1);
1434 sso_fastpath_fns_set(event_dev);
1440 otx2_sso_stop(struct rte_eventdev *event_dev)
1443 sso_cleanup(event_dev, 0);
1448 otx2_sso_close(struct rte_eventdev *event_dev)
1450 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1451 uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
1454 if (!dev->configured)
1457 sso_unregister_irqs(event_dev);
1459 for (i = 0; i < dev->nb_event_queues; i++)
1462 for (i = 0; i < dev->nb_event_ports; i++)
1463 otx2_sso_port_unlink(event_dev, event_dev->data->ports[i],
1464 all_queues, dev->nb_event_queues);
1466 sso_lf_teardown(dev, SSO_LF_GGRP);
1467 sso_lf_teardown(dev, SSO_LF_GWS);
1468 dev->nb_event_ports = 0;
1469 dev->nb_event_queues = 0;
1470 rte_mempool_free(dev->xaq_pool);
1471 rte_memzone_free(rte_memzone_lookup(OTX2_SSO_FC_NAME));
1476 /* Initialize and register event driver with DPDK Application */
1477 static struct rte_eventdev_ops otx2_sso_ops = {
1478 .dev_infos_get = otx2_sso_info_get,
1479 .dev_configure = otx2_sso_configure,
1480 .queue_def_conf = otx2_sso_queue_def_conf,
1481 .queue_setup = otx2_sso_queue_setup,
1482 .queue_release = otx2_sso_queue_release,
1483 .port_def_conf = otx2_sso_port_def_conf,
1484 .port_setup = otx2_sso_port_setup,
1485 .port_release = otx2_sso_port_release,
1486 .port_link = otx2_sso_port_link,
1487 .port_unlink = otx2_sso_port_unlink,
1488 .timeout_ticks = otx2_sso_timeout_ticks,
1490 .eth_rx_adapter_caps_get = otx2_sso_rx_adapter_caps_get,
1491 .eth_rx_adapter_queue_add = otx2_sso_rx_adapter_queue_add,
1492 .eth_rx_adapter_queue_del = otx2_sso_rx_adapter_queue_del,
1493 .eth_rx_adapter_start = otx2_sso_rx_adapter_start,
1494 .eth_rx_adapter_stop = otx2_sso_rx_adapter_stop,
1496 .eth_tx_adapter_caps_get = otx2_sso_tx_adapter_caps_get,
1497 .eth_tx_adapter_queue_add = otx2_sso_tx_adapter_queue_add,
1498 .eth_tx_adapter_queue_del = otx2_sso_tx_adapter_queue_del,
1500 .timer_adapter_caps_get = otx2_tim_caps_get,
1502 .xstats_get = otx2_sso_xstats_get,
1503 .xstats_reset = otx2_sso_xstats_reset,
1504 .xstats_get_names = otx2_sso_xstats_get_names,
1506 .dump = otx2_sso_dump,
1507 .dev_start = otx2_sso_start,
1508 .dev_stop = otx2_sso_stop,
1509 .dev_close = otx2_sso_close,
1510 .dev_selftest = otx2_sso_selftest,
1513 #define OTX2_SSO_XAE_CNT "xae_cnt"
1514 #define OTX2_SSO_SINGLE_WS "single_ws"
1515 #define OTX2_SSO_GGRP_QOS "qos"
1516 #define OTX2_SSO_SELFTEST "selftest"
1519 parse_queue_param(char *value, void *opaque)
1521 struct otx2_sso_qos queue_qos = {0};
1522 uint8_t *val = (uint8_t *)&queue_qos;
1523 struct otx2_sso_evdev *dev = opaque;
1524 char *tok = strtok(value, "-");
1525 struct otx2_sso_qos *old_ptr;
1530 while (tok != NULL) {
1532 tok = strtok(NULL, "-");
1536 if (val != (&queue_qos.iaq_prcnt + 1)) {
1537 otx2_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
1541 dev->qos_queue_cnt++;
1542 old_ptr = dev->qos_parse_data;
1543 dev->qos_parse_data = rte_realloc(dev->qos_parse_data,
1544 sizeof(struct otx2_sso_qos) *
1545 dev->qos_queue_cnt, 0);
1546 if (dev->qos_parse_data == NULL) {
1547 dev->qos_parse_data = old_ptr;
1548 dev->qos_queue_cnt--;
1551 dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
1555 parse_qos_list(const char *value, void *opaque)
1557 char *s = strdup(value);
1568 if (start && start < end) {
1570 parse_queue_param(start + 1, opaque);
1581 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
1585 /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
1586 * isn't allowed. Everything is expressed in percentages, 0 represents
1589 parse_qos_list(value, opaque);
1595 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
1597 struct rte_kvargs *kvlist;
1598 uint8_t single_ws = 0;
1600 if (devargs == NULL)
1602 kvlist = rte_kvargs_parse(devargs->args, NULL);
1606 rte_kvargs_process(kvlist, OTX2_SSO_SELFTEST, &parse_kvargs_flag,
1608 rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
1610 rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
1612 rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
1615 dev->dual_ws = !single_ws;
1616 rte_kvargs_free(kvlist);
1620 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1622 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1623 sizeof(struct otx2_sso_evdev),
1628 otx2_sso_remove(struct rte_pci_device *pci_dev)
1630 return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
1633 static const struct rte_pci_id pci_sso_map[] = {
1635 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1636 PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
1643 static struct rte_pci_driver pci_sso = {
1644 .id_table = pci_sso_map,
1645 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1646 .probe = otx2_sso_probe,
1647 .remove = otx2_sso_remove,
1651 otx2_sso_init(struct rte_eventdev *event_dev)
1653 struct free_rsrcs_rsp *rsrc_cnt;
1654 struct rte_pci_device *pci_dev;
1655 struct otx2_sso_evdev *dev;
1658 event_dev->dev_ops = &otx2_sso_ops;
1659 /* For secondary processes, the primary has done all the work */
1660 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1661 sso_fastpath_fns_set(event_dev);
1665 dev = sso_pmd_priv(event_dev);
1667 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1669 /* Initialize the base otx2_dev object */
1670 rc = otx2_dev_init(pci_dev, dev);
1672 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1676 /* Get SSO and SSOW MSIX rsrc cnt */
1677 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
1678 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
1680 otx2_err("Unable to get free rsrc count");
1681 goto otx2_dev_uninit;
1683 otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
1684 rsrc_cnt->ssow, rsrc_cnt->npa);
1686 dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
1687 dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
1688 /* Grab the NPA LF if required */
1689 rc = otx2_npa_lf_init(pci_dev, dev);
1691 otx2_err("Unable to init NPA lf. It might not be provisioned");
1692 goto otx2_dev_uninit;
1695 dev->drv_inited = true;
1696 dev->is_timeout_deq = 0;
1697 dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1698 dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1699 dev->max_num_events = -1;
1700 dev->nb_event_queues = 0;
1701 dev->nb_event_ports = 0;
1703 if (!dev->max_event_ports || !dev->max_event_queues) {
1704 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1705 dev->max_event_queues, dev->max_event_ports);
1707 goto otx2_npa_lf_uninit;
1711 sso_parse_devargs(dev, pci_dev->device.devargs);
1713 otx2_sso_dbg("Using dual workslot mode");
1714 dev->max_event_ports = dev->max_event_ports / 2;
1716 otx2_sso_dbg("Using single workslot mode");
1719 otx2_sso_pf_func_set(dev->pf_func);
1720 otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1721 event_dev->data->name, dev->max_event_queues,
1722 dev->max_event_ports);
1723 if (dev->selftest) {
1724 event_dev->dev->driver = &pci_sso.driver;
1725 event_dev->dev_ops->dev_selftest();
1728 otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
1735 otx2_dev_fini(pci_dev, dev);
1741 otx2_sso_fini(struct rte_eventdev *event_dev)
1743 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1744 struct rte_pci_device *pci_dev;
1746 /* For secondary processes, nothing to be done */
1747 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1750 pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1752 if (!dev->drv_inited)
1755 dev->drv_inited = false;
1759 if (otx2_npa_lf_active(dev)) {
1760 otx2_info("Common resource in use by other devices");
1765 otx2_dev_fini(pci_dev, dev);
1770 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1771 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1772 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1773 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
1774 OTX2_SSO_SINGLE_WS "=1"
1775 OTX2_SSO_GGRP_QOS "=<string>"
1776 OTX2_SSO_SELFTEST "=1");