1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_EVDEV_H__
6 #define __OTX2_EVDEV_H__
8 #include <rte_eventdev.h>
10 #include "otx2_common.h"
12 #include "otx2_mempool.h"
14 #define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev
16 #define sso_func_trace otx2_sso_dbg
18 #define OTX2_SSO_MAX_VHGRP RTE_EVENT_MAX_QUEUES_PER_DEV
19 #define OTX2_SSO_MAX_VHWS (UINT8_MAX)
20 #define OTX2_SSO_FC_NAME "otx2_evdev_xaq_fc"
21 #define OTX2_SSO_XAQ_SLACK (8)
22 #define OTX2_SSO_XAQ_CACHE_CNT (0x7)
24 /* SSO LF register offsets (BAR2) */
25 #define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull)
26 #define SSO_LF_GGRP_OP_ADD_WORK1 (0x8ull)
28 #define SSO_LF_GGRP_QCTL (0x20ull)
29 #define SSO_LF_GGRP_EXE_DIS (0x80ull)
30 #define SSO_LF_GGRP_INT (0x100ull)
31 #define SSO_LF_GGRP_INT_W1S (0x108ull)
32 #define SSO_LF_GGRP_INT_ENA_W1S (0x110ull)
33 #define SSO_LF_GGRP_INT_ENA_W1C (0x118ull)
34 #define SSO_LF_GGRP_INT_THR (0x140ull)
35 #define SSO_LF_GGRP_INT_CNT (0x180ull)
36 #define SSO_LF_GGRP_XAQ_CNT (0x1b0ull)
37 #define SSO_LF_GGRP_AQ_CNT (0x1c0ull)
38 #define SSO_LF_GGRP_AQ_THR (0x1e0ull)
39 #define SSO_LF_GGRP_MISC_CNT (0x200ull)
41 /* SSOW LF register offsets (BAR2) */
42 #define SSOW_LF_GWS_LINKS (0x10ull)
43 #define SSOW_LF_GWS_PENDWQP (0x40ull)
44 #define SSOW_LF_GWS_PENDSTATE (0x50ull)
45 #define SSOW_LF_GWS_NW_TIM (0x70ull)
46 #define SSOW_LF_GWS_GRPMSK_CHG (0x80ull)
47 #define SSOW_LF_GWS_INT (0x100ull)
48 #define SSOW_LF_GWS_INT_W1S (0x108ull)
49 #define SSOW_LF_GWS_INT_ENA_W1S (0x110ull)
50 #define SSOW_LF_GWS_INT_ENA_W1C (0x118ull)
51 #define SSOW_LF_GWS_TAG (0x200ull)
52 #define SSOW_LF_GWS_WQP (0x210ull)
53 #define SSOW_LF_GWS_SWTP (0x220ull)
54 #define SSOW_LF_GWS_PENDTAG (0x230ull)
55 #define SSOW_LF_GWS_OP_ALLOC_WE (0x400ull)
56 #define SSOW_LF_GWS_OP_GET_WORK (0x600ull)
57 #define SSOW_LF_GWS_OP_SWTAG_FLUSH (0x800ull)
58 #define SSOW_LF_GWS_OP_SWTAG_UNTAG (0x810ull)
59 #define SSOW_LF_GWS_OP_SWTP_CLR (0x820ull)
60 #define SSOW_LF_GWS_OP_UPD_WQP_GRP0 (0x830ull)
61 #define SSOW_LF_GWS_OP_UPD_WQP_GRP1 (0x838ull)
62 #define SSOW_LF_GWS_OP_DESCHED (0x880ull)
63 #define SSOW_LF_GWS_OP_DESCHED_NOSCH (0x8c0ull)
64 #define SSOW_LF_GWS_OP_SWTAG_DESCHED (0x980ull)
65 #define SSOW_LF_GWS_OP_SWTAG_NOSCHED (0x9c0ull)
66 #define SSOW_LF_GWS_OP_CLR_NSCHED0 (0xa00ull)
67 #define SSOW_LF_GWS_OP_CLR_NSCHED1 (0xa08ull)
68 #define SSOW_LF_GWS_OP_SWTP_SET (0xc00ull)
69 #define SSOW_LF_GWS_OP_SWTAG_NORM (0xc10ull)
70 #define SSOW_LF_GWS_OP_SWTAG_FULL0 (0xc20ull)
71 #define SSOW_LF_GWS_OP_SWTAG_FULL1 (0xc28ull)
72 #define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull)
74 #define OTX2_SSOW_GET_BASE_ADDR(_GW) ((_GW) - SSOW_LF_GWS_OP_GET_WORK)
76 #define NSEC2USEC(__ns) ((__ns) / 1E3)
77 #define USEC2NSEC(__us) ((__us) * 1E3)
78 #define NSEC2TICK(__ns, __freq) (((__ns) * (__freq)) / 1E9)
80 enum otx2_sso_lf_type {
85 struct otx2_sso_evdev {
86 OTX2_DEV; /* Base class */
87 uint8_t max_event_queues;
88 uint8_t max_event_ports;
89 uint8_t is_timeout_deq;
90 uint8_t nb_event_queues;
91 uint8_t nb_event_ports;
94 uint32_t min_dequeue_timeout_ns;
95 uint32_t max_dequeue_timeout_ns;
96 int32_t max_num_events;
101 struct rte_mempool *xaq_pool;
106 uint32_t xaq_buf_size;
108 } __rte_cache_aligned;
110 #define OTX2_SSOGWS_OPS \
112 uintptr_t getwrk_op; \
116 uintptr_t swtag_norm_op; \
117 uintptr_t swtag_desched_op; \
121 /* Event port aka GWS */
123 /* Get Work Fastpath data */
127 /* Add Work Fastpath data */
128 uint64_t xaq_lmt __rte_cache_aligned;
130 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP];
131 } __rte_cache_aligned;
133 static inline struct otx2_sso_evdev *
134 sso_pmd_priv(const struct rte_eventdev *event_dev)
136 return event_dev->data->dev_private;
140 parse_kvargs_value(const char *key, const char *value, void *opaque)
144 *(uint32_t *)opaque = (uint32_t)atoi(value);
148 /* Init and Fini API's */
149 int otx2_sso_init(struct rte_eventdev *event_dev);
150 int otx2_sso_fini(struct rte_eventdev *event_dev);
152 #endif /* __OTX2_EVDEV_H__ */