1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_EVDEV_H__
6 #define __OTX2_EVDEV_H__
8 #include <rte_eventdev.h>
9 #include <rte_eventdev_pmd.h>
10 #include <rte_event_eth_rx_adapter.h>
11 #include <rte_event_eth_tx_adapter.h>
13 #include "otx2_common.h"
15 #include "otx2_ethdev.h"
16 #include "otx2_mempool.h"
17 #include "otx2_tim_evdev.h"
19 #define EVENTDEV_NAME_OCTEONTX2_PMD event_octeontx2
21 #define sso_func_trace otx2_sso_dbg
23 #define OTX2_SSO_MAX_VHGRP RTE_EVENT_MAX_QUEUES_PER_DEV
24 #define OTX2_SSO_MAX_VHWS (UINT8_MAX)
25 #define OTX2_SSO_FC_NAME "otx2_evdev_xaq_fc"
26 #define OTX2_SSO_SQB_LIMIT (0x180)
27 #define OTX2_SSO_XAQ_SLACK (8)
28 #define OTX2_SSO_XAQ_CACHE_CNT (0x7)
29 #define OTX2_SSO_WQE_SG_PTR (9)
31 /* SSO LF register offsets (BAR2) */
32 #define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull)
33 #define SSO_LF_GGRP_OP_ADD_WORK1 (0x8ull)
35 #define SSO_LF_GGRP_QCTL (0x20ull)
36 #define SSO_LF_GGRP_EXE_DIS (0x80ull)
37 #define SSO_LF_GGRP_INT (0x100ull)
38 #define SSO_LF_GGRP_INT_W1S (0x108ull)
39 #define SSO_LF_GGRP_INT_ENA_W1S (0x110ull)
40 #define SSO_LF_GGRP_INT_ENA_W1C (0x118ull)
41 #define SSO_LF_GGRP_INT_THR (0x140ull)
42 #define SSO_LF_GGRP_INT_CNT (0x180ull)
43 #define SSO_LF_GGRP_XAQ_CNT (0x1b0ull)
44 #define SSO_LF_GGRP_AQ_CNT (0x1c0ull)
45 #define SSO_LF_GGRP_AQ_THR (0x1e0ull)
46 #define SSO_LF_GGRP_MISC_CNT (0x200ull)
48 /* SSOW LF register offsets (BAR2) */
49 #define SSOW_LF_GWS_LINKS (0x10ull)
50 #define SSOW_LF_GWS_PENDWQP (0x40ull)
51 #define SSOW_LF_GWS_PENDSTATE (0x50ull)
52 #define SSOW_LF_GWS_NW_TIM (0x70ull)
53 #define SSOW_LF_GWS_GRPMSK_CHG (0x80ull)
54 #define SSOW_LF_GWS_INT (0x100ull)
55 #define SSOW_LF_GWS_INT_W1S (0x108ull)
56 #define SSOW_LF_GWS_INT_ENA_W1S (0x110ull)
57 #define SSOW_LF_GWS_INT_ENA_W1C (0x118ull)
58 #define SSOW_LF_GWS_TAG (0x200ull)
59 #define SSOW_LF_GWS_WQP (0x210ull)
60 #define SSOW_LF_GWS_SWTP (0x220ull)
61 #define SSOW_LF_GWS_PENDTAG (0x230ull)
62 #define SSOW_LF_GWS_OP_ALLOC_WE (0x400ull)
63 #define SSOW_LF_GWS_OP_GET_WORK (0x600ull)
64 #define SSOW_LF_GWS_OP_SWTAG_FLUSH (0x800ull)
65 #define SSOW_LF_GWS_OP_SWTAG_UNTAG (0x810ull)
66 #define SSOW_LF_GWS_OP_SWTP_CLR (0x820ull)
67 #define SSOW_LF_GWS_OP_UPD_WQP_GRP0 (0x830ull)
68 #define SSOW_LF_GWS_OP_UPD_WQP_GRP1 (0x838ull)
69 #define SSOW_LF_GWS_OP_DESCHED (0x880ull)
70 #define SSOW_LF_GWS_OP_DESCHED_NOSCH (0x8c0ull)
71 #define SSOW_LF_GWS_OP_SWTAG_DESCHED (0x980ull)
72 #define SSOW_LF_GWS_OP_SWTAG_NOSCHED (0x9c0ull)
73 #define SSOW_LF_GWS_OP_CLR_NSCHED0 (0xa00ull)
74 #define SSOW_LF_GWS_OP_CLR_NSCHED1 (0xa08ull)
75 #define SSOW_LF_GWS_OP_SWTP_SET (0xc00ull)
76 #define SSOW_LF_GWS_OP_SWTAG_NORM (0xc10ull)
77 #define SSOW_LF_GWS_OP_SWTAG_FULL0 (0xc20ull)
78 #define SSOW_LF_GWS_OP_SWTAG_FULL1 (0xc28ull)
79 #define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull)
81 #define OTX2_SSOW_GET_BASE_ADDR(_GW) ((_GW) - SSOW_LF_GWS_OP_GET_WORK)
83 #define NSEC2USEC(__ns) ((__ns) / 1E3)
84 #define USEC2NSEC(__us) ((__us) * 1E3)
85 #define NSEC2TICK(__ns, __freq) (((__ns) * (__freq)) / 1E9)
86 #define TICK2NSEC(__tck, __freq) (((__tck) * 1E9) / (__freq))
88 enum otx2_sso_lf_type {
93 union otx2_sso_event {
97 uint32_t sub_event_type:8;
98 uint32_t event_type:4;
101 uint8_t sched_type:2;
115 struct otx2_sso_qos {
122 struct otx2_sso_evdev {
123 OTX2_DEV; /* Base class */
124 uint8_t max_event_queues;
125 uint8_t max_event_ports;
126 uint8_t is_timeout_deq;
127 uint8_t nb_event_queues;
128 uint8_t nb_event_ports;
131 uint32_t min_dequeue_timeout_ns;
132 uint32_t max_dequeue_timeout_ns;
133 int32_t max_num_events;
138 struct rte_mempool *xaq_pool;
139 uint64_t rx_offloads;
140 uint64_t tx_offloads;
141 uint64_t adptr_xae_cnt;
142 uint16_t rx_adptr_pool_cnt;
143 uint64_t *rx_adptr_pools;
144 uint16_t max_port_id;
145 uint16_t tim_adptr_ring_cnt;
146 uint16_t *timer_adptr_rings;
147 uint64_t *timer_adptr_sz;
151 uint8_t qos_queue_cnt;
152 struct otx2_sso_qos *qos_parse_data;
155 uint32_t xaq_buf_size;
158 uint16_t sso_msixoff[OTX2_SSO_MAX_VHGRP];
159 uint16_t ssow_msixoff[OTX2_SSO_MAX_VHWS];
161 struct otx2_timesync_info *tstamp;
162 } __rte_cache_aligned;
164 #define OTX2_SSOGWS_OPS \
166 uintptr_t getwrk_op; \
169 uintptr_t swtag_flush_op; \
170 uintptr_t swtag_norm_op; \
171 uintptr_t swtag_desched_op; \
175 /* Event port aka GWS */
177 /* Get Work Fastpath data */
182 /* Add Work Fastpath data */
183 uint64_t xaq_lmt __rte_cache_aligned;
185 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP];
187 struct otx2_timesync_info *tstamp;
188 /* Tx Fastpath data */
189 uint8_t tx_adptr_data[] __rte_cache_aligned;
190 } __rte_cache_aligned;
192 struct otx2_ssogws_state {
196 struct otx2_ssogws_dual {
197 /* Get Work Fastpath data */
198 struct otx2_ssogws_state ws_state[2]; /* Ping and Pong */
200 uint8_t vws; /* Ping pong bit */
203 /* Add Work Fastpath data */
204 uint64_t xaq_lmt __rte_cache_aligned;
206 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP];
208 struct otx2_timesync_info *tstamp;
209 /* Tx Fastpath data */
210 uint8_t tx_adptr_data[] __rte_cache_aligned;
211 } __rte_cache_aligned;
213 static inline struct otx2_sso_evdev *
214 sso_pmd_priv(const struct rte_eventdev *event_dev)
216 return event_dev->data->dev_private;
219 static const union mbuf_initializer mbuf_init = {
221 .data_off = RTE_PKTMBUF_HEADROOM,
228 static __rte_always_inline void
229 otx2_wqe_to_mbuf(uint64_t get_work1, const uint64_t mbuf, uint8_t port_id,
230 const uint32_t tag, const uint32_t flags,
231 const void * const lookup_mem)
233 struct nix_wqe_hdr_s *wqe = (struct nix_wqe_hdr_s *)get_work1;
234 uint64_t val = mbuf_init.value | (uint64_t)port_id << 48;
236 if (flags & NIX_RX_OFFLOAD_TSTAMP_F)
237 val |= NIX_TIMESYNC_RX_OFFSET;
239 otx2_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
240 (struct rte_mbuf *)mbuf, lookup_mem,
246 parse_kvargs_flag(const char *key, const char *value, void *opaque)
250 *(uint8_t *)opaque = !!atoi(value);
255 parse_kvargs_value(const char *key, const char *value, void *opaque)
259 *(uint32_t *)opaque = (uint32_t)atoi(value);
263 #define SSO_RX_ADPTR_ENQ_FASTPATH_FUNC NIX_RX_FASTPATH_MODES
264 #define SSO_TX_ADPTR_ENQ_FASTPATH_FUNC NIX_TX_FASTPATH_MODES
266 /* Single WS API's */
267 uint16_t otx2_ssogws_enq(void *port, const struct rte_event *ev);
268 uint16_t otx2_ssogws_enq_burst(void *port, const struct rte_event ev[],
270 uint16_t otx2_ssogws_enq_new_burst(void *port, const struct rte_event ev[],
272 uint16_t otx2_ssogws_enq_fwd_burst(void *port, const struct rte_event ev[],
276 uint16_t otx2_ssogws_dual_enq(void *port, const struct rte_event *ev);
277 uint16_t otx2_ssogws_dual_enq_burst(void *port, const struct rte_event ev[],
279 uint16_t otx2_ssogws_dual_enq_new_burst(void *port, const struct rte_event ev[],
281 uint16_t otx2_ssogws_dual_enq_fwd_burst(void *port, const struct rte_event ev[],
284 /* Auto generated API's */
285 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
286 uint16_t otx2_ssogws_deq_ ##name(void *port, struct rte_event *ev, \
287 uint64_t timeout_ticks); \
288 uint16_t otx2_ssogws_deq_burst_ ##name(void *port, struct rte_event ev[], \
289 uint16_t nb_events, \
290 uint64_t timeout_ticks); \
291 uint16_t otx2_ssogws_deq_timeout_ ##name(void *port, \
292 struct rte_event *ev, \
293 uint64_t timeout_ticks); \
294 uint16_t otx2_ssogws_deq_timeout_burst_ ##name(void *port, \
295 struct rte_event ev[], \
296 uint16_t nb_events, \
297 uint64_t timeout_ticks); \
298 uint16_t otx2_ssogws_deq_seg_ ##name(void *port, struct rte_event *ev, \
299 uint64_t timeout_ticks); \
300 uint16_t otx2_ssogws_deq_seg_burst_ ##name(void *port, \
301 struct rte_event ev[], \
302 uint16_t nb_events, \
303 uint64_t timeout_ticks); \
304 uint16_t otx2_ssogws_deq_seg_timeout_ ##name(void *port, \
305 struct rte_event *ev, \
306 uint64_t timeout_ticks); \
307 uint16_t otx2_ssogws_deq_seg_timeout_burst_ ##name(void *port, \
308 struct rte_event ev[], \
309 uint16_t nb_events, \
310 uint64_t timeout_ticks); \
312 uint16_t otx2_ssogws_dual_deq_ ##name(void *port, struct rte_event *ev, \
313 uint64_t timeout_ticks); \
314 uint16_t otx2_ssogws_dual_deq_burst_ ##name(void *port, \
315 struct rte_event ev[], \
316 uint16_t nb_events, \
317 uint64_t timeout_ticks); \
318 uint16_t otx2_ssogws_dual_deq_timeout_ ##name(void *port, \
319 struct rte_event *ev, \
320 uint64_t timeout_ticks); \
321 uint16_t otx2_ssogws_dual_deq_timeout_burst_ ##name(void *port, \
322 struct rte_event ev[], \
323 uint16_t nb_events, \
324 uint64_t timeout_ticks); \
325 uint16_t otx2_ssogws_dual_deq_seg_ ##name(void *port, struct rte_event *ev, \
326 uint64_t timeout_ticks); \
327 uint16_t otx2_ssogws_dual_deq_seg_burst_ ##name(void *port, \
328 struct rte_event ev[], \
329 uint16_t nb_events, \
330 uint64_t timeout_ticks); \
331 uint16_t otx2_ssogws_dual_deq_seg_timeout_ ##name(void *port, \
332 struct rte_event *ev, \
333 uint64_t timeout_ticks); \
334 uint16_t otx2_ssogws_dual_deq_seg_timeout_burst_ ##name(void *port, \
335 struct rte_event ev[], \
336 uint16_t nb_events, \
337 uint64_t timeout_ticks);\
339 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
342 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
343 uint16_t otx2_ssogws_tx_adptr_enq_ ## name(void *port, struct rte_event ev[],\
344 uint16_t nb_events); \
345 uint16_t otx2_ssogws_tx_adptr_enq_seg_ ## name(void *port, \
346 struct rte_event ev[], \
347 uint16_t nb_events); \
348 uint16_t otx2_ssogws_dual_tx_adptr_enq_ ## name(void *port, \
349 struct rte_event ev[], \
350 uint16_t nb_events); \
351 uint16_t otx2_ssogws_dual_tx_adptr_enq_seg_ ## name(void *port, \
352 struct rte_event ev[], \
353 uint16_t nb_events); \
355 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
358 void sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data,
359 uint32_t event_type);
360 int sso_xae_reconfigure(struct rte_eventdev *event_dev);
361 void sso_fastpath_fns_set(struct rte_eventdev *event_dev);
363 int otx2_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
364 const struct rte_eth_dev *eth_dev,
366 int otx2_sso_rx_adapter_queue_add(const struct rte_eventdev *event_dev,
367 const struct rte_eth_dev *eth_dev,
369 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
370 int otx2_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
371 const struct rte_eth_dev *eth_dev,
372 int32_t rx_queue_id);
373 int otx2_sso_rx_adapter_start(const struct rte_eventdev *event_dev,
374 const struct rte_eth_dev *eth_dev);
375 int otx2_sso_rx_adapter_stop(const struct rte_eventdev *event_dev,
376 const struct rte_eth_dev *eth_dev);
377 int otx2_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
378 const struct rte_eth_dev *eth_dev,
380 int otx2_sso_tx_adapter_queue_add(uint8_t id,
381 const struct rte_eventdev *event_dev,
382 const struct rte_eth_dev *eth_dev,
383 int32_t tx_queue_id);
385 int otx2_sso_tx_adapter_queue_del(uint8_t id,
386 const struct rte_eventdev *event_dev,
387 const struct rte_eth_dev *eth_dev,
388 int32_t tx_queue_id);
390 /* Event crypto adapter API's */
391 int otx2_ca_caps_get(const struct rte_eventdev *dev,
392 const struct rte_cryptodev *cdev, uint32_t *caps);
394 int otx2_ca_qp_add(const struct rte_eventdev *dev,
395 const struct rte_cryptodev *cdev, int32_t queue_pair_id,
396 const struct rte_event *event);
398 int otx2_ca_qp_del(const struct rte_eventdev *dev,
399 const struct rte_cryptodev *cdev, int32_t queue_pair_id);
402 typedef void (*otx2_handle_event_t)(void *arg, struct rte_event ev);
403 void ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id,
404 uintptr_t base, otx2_handle_event_t fn, void *arg);
405 void ssogws_reset(struct otx2_ssogws *ws);
407 int otx2_sso_selftest(void);
408 /* Init and Fini API's */
409 int otx2_sso_init(struct rte_eventdev *event_dev);
410 int otx2_sso_fini(struct rte_eventdev *event_dev);
412 int sso_register_irqs(const struct rte_eventdev *event_dev);
413 void sso_unregister_irqs(const struct rte_eventdev *event_dev);
415 #endif /* __OTX2_EVDEV_H__ */