1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include "otx2_evdev.h"
8 sso_lf_irq(void *param)
10 uintptr_t base = (uintptr_t)param;
14 ggrp = (base >> 12) & 0xFF;
16 intr = otx2_read64(base + SSO_LF_GGRP_INT);
20 otx2_err("GGRP %d GGRP_INT=0x%" PRIx64 "", ggrp, intr);
23 otx2_write64(intr, base + SSO_LF_GGRP_INT);
27 sso_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t ggrp_msixoff,
30 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
31 struct rte_intr_handle *handle = &pci_dev->intr_handle;
34 vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;
36 /* Clear err interrupt */
37 otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C);
38 /* Set used interrupt vectors */
39 rc = otx2_register_irq(handle, sso_lf_irq, (void *)base, vec);
40 /* Enable hw interrupt */
41 otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1S);
47 ssow_lf_irq(void *param)
49 uintptr_t base = (uintptr_t)param;
50 uint8_t gws = (base >> 12) & 0xFF;
53 intr = otx2_read64(base + SSOW_LF_GWS_INT);
57 otx2_err("GWS %d GWS_INT=0x%" PRIx64 "", gws, intr);
60 otx2_write64(intr, base + SSOW_LF_GWS_INT);
64 ssow_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t gws_msixoff,
67 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
68 struct rte_intr_handle *handle = &pci_dev->intr_handle;
71 vec = gws_msixoff + SSOW_LF_INT_VEC_IOP;
73 /* Clear err interrupt */
74 otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C);
75 /* Set used interrupt vectors */
76 rc = otx2_register_irq(handle, ssow_lf_irq, (void *)base, vec);
77 /* Enable hw interrupt */
78 otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1S);
84 sso_lf_unregister_irq(const struct rte_eventdev *event_dev,
85 uint16_t ggrp_msixoff, uintptr_t base)
87 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
88 struct rte_intr_handle *handle = &pci_dev->intr_handle;
91 vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;
93 /* Clear err interrupt */
94 otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C);
95 otx2_unregister_irq(handle, sso_lf_irq, (void *)base, vec);
99 ssow_lf_unregister_irq(const struct rte_eventdev *event_dev,
100 uint16_t gws_msixoff, uintptr_t base)
102 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
103 struct rte_intr_handle *handle = &pci_dev->intr_handle;
106 vec = gws_msixoff + SSOW_LF_INT_VEC_IOP;
108 /* Clear err interrupt */
109 otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C);
110 otx2_unregister_irq(handle, ssow_lf_irq, (void *)base, vec);
114 sso_register_irqs(const struct rte_eventdev *event_dev)
116 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
120 nb_ports = dev->nb_event_ports;
122 for (i = 0; i < dev->nb_event_queues; i++) {
123 if (dev->sso_msixoff[i] == MSIX_VECTOR_INVALID) {
124 otx2_err("Invalid SSOLF MSIX offset[%d] vector: 0x%x",
125 i, dev->sso_msixoff[i]);
130 for (i = 0; i < nb_ports; i++) {
131 if (dev->ssow_msixoff[i] == MSIX_VECTOR_INVALID) {
132 otx2_err("Invalid SSOWLF MSIX offset[%d] vector: 0x%x",
133 i, dev->ssow_msixoff[i]);
138 for (i = 0; i < dev->nb_event_queues; i++) {
139 uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |
141 rc = sso_lf_register_irq(event_dev, dev->sso_msixoff[i], base);
144 for (i = 0; i < nb_ports; i++) {
145 uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 |
147 rc = ssow_lf_register_irq(event_dev, dev->ssow_msixoff[i],
156 sso_unregister_irqs(const struct rte_eventdev *event_dev)
158 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
162 nb_ports = dev->nb_event_ports;
164 for (i = 0; i < dev->nb_event_queues; i++) {
165 uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |
167 sso_lf_unregister_irq(event_dev, dev->sso_msixoff[i], base);
170 for (i = 0; i < nb_ports; i++) {
171 uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 |
173 ssow_lf_unregister_irq(event_dev, dev->ssow_msixoff[i], base);