1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include "otx2_evdev.h"
6 #include "otx2_tim_evdev.h"
9 sso_lf_irq(void *param)
11 uintptr_t base = (uintptr_t)param;
15 ggrp = (base >> 12) & 0xFF;
17 intr = otx2_read64(base + SSO_LF_GGRP_INT);
21 otx2_err("GGRP %d GGRP_INT=0x%" PRIx64 "", ggrp, intr);
24 otx2_write64(intr, base + SSO_LF_GGRP_INT);
28 sso_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t ggrp_msixoff,
31 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
32 struct rte_intr_handle *handle = &pci_dev->intr_handle;
35 vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;
37 /* Clear err interrupt */
38 otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C);
39 /* Set used interrupt vectors */
40 rc = otx2_register_irq(handle, sso_lf_irq, (void *)base, vec);
41 /* Enable hw interrupt */
42 otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1S);
48 ssow_lf_irq(void *param)
50 uintptr_t base = (uintptr_t)param;
51 uint8_t gws = (base >> 12) & 0xFF;
54 intr = otx2_read64(base + SSOW_LF_GWS_INT);
58 otx2_err("GWS %d GWS_INT=0x%" PRIx64 "", gws, intr);
61 otx2_write64(intr, base + SSOW_LF_GWS_INT);
65 ssow_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t gws_msixoff,
68 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
69 struct rte_intr_handle *handle = &pci_dev->intr_handle;
72 vec = gws_msixoff + SSOW_LF_INT_VEC_IOP;
74 /* Clear err interrupt */
75 otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C);
76 /* Set used interrupt vectors */
77 rc = otx2_register_irq(handle, ssow_lf_irq, (void *)base, vec);
78 /* Enable hw interrupt */
79 otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1S);
85 sso_lf_unregister_irq(const struct rte_eventdev *event_dev,
86 uint16_t ggrp_msixoff, uintptr_t base)
88 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
89 struct rte_intr_handle *handle = &pci_dev->intr_handle;
92 vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;
94 /* Clear err interrupt */
95 otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C);
96 otx2_unregister_irq(handle, sso_lf_irq, (void *)base, vec);
100 ssow_lf_unregister_irq(const struct rte_eventdev *event_dev,
101 uint16_t gws_msixoff, uintptr_t base)
103 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);
104 struct rte_intr_handle *handle = &pci_dev->intr_handle;
107 vec = gws_msixoff + SSOW_LF_INT_VEC_IOP;
109 /* Clear err interrupt */
110 otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C);
111 otx2_unregister_irq(handle, ssow_lf_irq, (void *)base, vec);
115 sso_register_irqs(const struct rte_eventdev *event_dev)
117 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
121 nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
123 for (i = 0; i < dev->nb_event_queues; i++) {
124 if (dev->sso_msixoff[i] == MSIX_VECTOR_INVALID) {
125 otx2_err("Invalid SSOLF MSIX offset[%d] vector: 0x%x",
126 i, dev->sso_msixoff[i]);
131 for (i = 0; i < nb_ports; i++) {
132 if (dev->ssow_msixoff[i] == MSIX_VECTOR_INVALID) {
133 otx2_err("Invalid SSOWLF MSIX offset[%d] vector: 0x%x",
134 i, dev->ssow_msixoff[i]);
139 for (i = 0; i < dev->nb_event_queues; i++) {
140 uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |
142 rc = sso_lf_register_irq(event_dev, dev->sso_msixoff[i], base);
145 for (i = 0; i < nb_ports; i++) {
146 uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 |
148 rc = ssow_lf_register_irq(event_dev, dev->ssow_msixoff[i],
157 sso_unregister_irqs(const struct rte_eventdev *event_dev)
159 struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
163 nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
165 for (i = 0; i < dev->nb_event_queues; i++) {
166 uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |
168 sso_lf_unregister_irq(event_dev, dev->sso_msixoff[i], base);
171 for (i = 0; i < nb_ports; i++) {
172 uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 |
174 ssow_lf_unregister_irq(event_dev, dev->ssow_msixoff[i], base);
179 tim_lf_irq(void *param)
181 uintptr_t base = (uintptr_t)param;
185 ring = (base >> 12) & 0xFF;
187 intr = otx2_read64(base + TIM_LF_NRSPERR_INT);
188 otx2_err("TIM RING %d TIM_LF_NRSPERR_INT=0x%" PRIx64 "", ring, intr);
189 intr = otx2_read64(base + TIM_LF_RAS_INT);
190 otx2_err("TIM RING %d TIM_LF_RAS_INT=0x%" PRIx64 "", ring, intr);
192 /* Clear interrupt */
193 otx2_write64(intr, base + TIM_LF_NRSPERR_INT);
194 otx2_write64(intr, base + TIM_LF_RAS_INT);
198 tim_lf_register_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,
201 struct rte_intr_handle *handle = &pci_dev->intr_handle;
204 vec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;
206 /* Clear err interrupt */
207 otx2_write64(~0ull, base + TIM_LF_NRSPERR_INT);
208 /* Set used interrupt vectors */
209 rc = otx2_register_irq(handle, tim_lf_irq, (void *)base, vec);
210 /* Enable hw interrupt */
211 otx2_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1S);
213 vec = tim_msixoff + TIM_LF_INT_VEC_RAS_INT;
215 /* Clear err interrupt */
216 otx2_write64(~0ull, base + TIM_LF_RAS_INT);
217 /* Set used interrupt vectors */
218 rc = otx2_register_irq(handle, tim_lf_irq, (void *)base, vec);
219 /* Enable hw interrupt */
220 otx2_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1S);
226 tim_lf_unregister_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,
229 struct rte_intr_handle *handle = &pci_dev->intr_handle;
232 vec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;
234 /* Clear err interrupt */
235 otx2_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1C);
236 otx2_unregister_irq(handle, tim_lf_irq, (void *)base, vec);
238 vec = tim_msixoff + TIM_LF_INT_VEC_RAS_INT;
240 /* Clear err interrupt */
241 otx2_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1C);
242 otx2_unregister_irq(handle, tim_lf_irq, (void *)base, vec);
246 tim_register_irq(uint16_t ring_id)
248 struct otx2_tim_evdev *dev = tim_priv_get();
252 if (dev->tim_msixoff[ring_id] == MSIX_VECTOR_INVALID) {
253 otx2_err("Invalid TIMLF MSIX offset[%d] vector: 0x%x",
254 ring_id, dev->tim_msixoff[ring_id]);
258 base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
259 rc = tim_lf_register_irq(dev->pci_dev, dev->tim_msixoff[ring_id], base);
265 tim_unregister_irq(uint16_t ring_id)
267 struct otx2_tim_evdev *dev = tim_priv_get();
270 base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
271 tim_lf_unregister_irq(dev->pci_dev, dev->tim_msixoff[ring_id], base);