1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_malloc.h>
6 #include <rte_mbuf_pool_ops.h>
8 #include "otx2_evdev.h"
9 #include "otx2_tim_evdev.h"
11 static struct rte_event_timer_adapter_ops otx2_tim_ops;
14 tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,
15 struct rte_event_timer_adapter_conf *rcfg)
17 unsigned int cache_sz = (tim_ring->nb_chunks / 1.5);
18 unsigned int mp_flags = 0;
22 /* Create chunk pool. */
23 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
24 mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
25 otx2_tim_dbg("Using single producer mode");
26 tim_ring->prod_type_sp = true;
29 snprintf(pool_name, sizeof(pool_name), "otx2_tim_chunk_pool%d",
32 if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)
33 cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;
35 /* NPA need not have cache as free is not visible to SW */
36 tim_ring->chunk_pool = rte_mempool_create_empty(pool_name,
39 0, 0, rte_socket_id(),
42 if (tim_ring->chunk_pool == NULL) {
43 otx2_err("Unable to create chunkpool.");
47 rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
48 rte_mbuf_platform_mempool_ops(), NULL);
50 otx2_err("Unable to set chunkpool ops");
54 rc = rte_mempool_populate_default(tim_ring->chunk_pool);
56 otx2_err("Unable to set populate chunkpool.");
59 tim_ring->aura = npa_lf_aura_handle_to_aura(
60 tim_ring->chunk_pool->pool_id);
61 tim_ring->ena_dfb = 0;
66 rte_mempool_free(tim_ring->chunk_pool);
74 case TIM_AF_NO_RINGS_LEFT:
75 otx2_err("Unable to allocat new TIM ring.");
77 case TIM_AF_INVALID_NPA_PF_FUNC:
78 otx2_err("Invalid NPA pf func.");
80 case TIM_AF_INVALID_SSO_PF_FUNC:
81 otx2_err("Invalid SSO pf func.");
83 case TIM_AF_RING_STILL_RUNNING:
84 otx2_tim_dbg("Ring busy.");
86 case TIM_AF_LF_INVALID:
87 otx2_err("Invalid Ring id.");
89 case TIM_AF_CSIZE_NOT_ALIGNED:
90 otx2_err("Chunk size specified needs to be multiple of 16.");
92 case TIM_AF_CSIZE_TOO_SMALL:
93 otx2_err("Chunk size too small.");
95 case TIM_AF_CSIZE_TOO_BIG:
96 otx2_err("Chunk size too big.");
98 case TIM_AF_INTERVAL_TOO_SMALL:
99 otx2_err("Bucket traversal interval too small.");
101 case TIM_AF_INVALID_BIG_ENDIAN_VALUE:
102 otx2_err("Invalid Big endian value.");
104 case TIM_AF_INVALID_CLOCK_SOURCE:
105 otx2_err("Invalid Clock source specified.");
107 case TIM_AF_GPIO_CLK_SRC_NOT_ENABLED:
108 otx2_err("GPIO clock source not enabled.");
110 case TIM_AF_INVALID_BSIZE:
111 otx2_err("Invalid bucket size.");
113 case TIM_AF_INVALID_ENABLE_PERIODIC:
114 otx2_err("Invalid bucket size.");
116 case TIM_AF_INVALID_ENABLE_DONTFREE:
117 otx2_err("Invalid Don't free value.");
119 case TIM_AF_ENA_DONTFRE_NSET_PERIODIC:
120 otx2_err("Don't free bit not set when periodic is enabled.");
122 case TIM_AF_RING_ALREADY_DISABLED:
123 otx2_err("Ring already stopped");
126 otx2_err("Unknown Error.");
131 otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)
133 struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
134 struct otx2_tim_evdev *dev = tim_priv_get();
135 struct otx2_tim_ring *tim_ring;
136 struct tim_config_req *cfg_req;
137 struct tim_ring_req *free_req;
138 struct tim_lf_alloc_req *req;
139 struct tim_lf_alloc_rsp *rsp;
146 if (adptr->data->id >= dev->nb_rings)
149 req = otx2_mbox_alloc_msg_tim_lf_alloc(dev->mbox);
150 req->npa_pf_func = otx2_npa_pf_func_get();
151 req->sso_pf_func = otx2_sso_pf_func_get();
152 req->ring = adptr->data->id;
154 rc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);
160 if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10),
161 rsp->tenns_clk) < OTX2_TIM_MIN_TMO_TKS) {
166 tim_ring = rte_zmalloc("otx2_tim_prv", sizeof(struct otx2_tim_ring), 0);
167 if (tim_ring == NULL) {
172 adptr->data->adapter_priv = tim_ring;
174 tim_ring->tenns_clk_freq = rsp->tenns_clk;
175 tim_ring->clk_src = (int)rcfg->clk_src;
176 tim_ring->ring_id = adptr->data->id;
177 tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);
178 tim_ring->max_tout = rcfg->max_tmo_ns;
179 tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
180 tim_ring->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ;
181 nb_timers = rcfg->nb_timers;
182 tim_ring->nb_chunks = nb_timers / OTX2_TIM_NB_CHUNK_SLOTS(
184 tim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
186 /* Create buckets. */
187 tim_ring->bkt = rte_zmalloc("otx2_tim_bucket", (tim_ring->nb_bkts) *
188 sizeof(struct otx2_tim_bkt),
189 RTE_CACHE_LINE_SIZE);
190 if (tim_ring->bkt == NULL)
193 rc = tim_chnk_pool_create(tim_ring, rcfg);
197 cfg_req = otx2_mbox_alloc_msg_tim_config_ring(dev->mbox);
199 cfg_req->ring = tim_ring->ring_id;
200 cfg_req->bigendian = false;
201 cfg_req->clocksource = tim_ring->clk_src;
202 cfg_req->enableperiodic = false;
203 cfg_req->enabledontfreebuffer = tim_ring->ena_dfb;
204 cfg_req->bucketsize = tim_ring->nb_bkts;
205 cfg_req->chunksize = tim_ring->chunk_sz;
206 cfg_req->interval = NSEC2TICK(tim_ring->tck_nsec,
207 tim_ring->tenns_clk_freq);
209 rc = otx2_mbox_process(dev->mbox);
215 tim_ring->base = dev->bar2 +
216 (RVU_BLOCK_ADDR_TIM << 20 | tim_ring->ring_id << 12);
218 otx2_write64((uint64_t)tim_ring->bkt,
219 tim_ring->base + TIM_LF_RING_BASE);
220 otx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
225 rte_free(tim_ring->bkt);
229 free_req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
230 free_req->ring = adptr->data->id;
231 otx2_mbox_process(dev->mbox);
236 otx2_tim_ring_free(struct rte_event_timer_adapter *adptr)
238 struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
239 struct otx2_tim_evdev *dev = tim_priv_get();
240 struct tim_ring_req *req;
246 req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
247 req->ring = tim_ring->ring_id;
249 rc = otx2_mbox_process(dev->mbox);
255 rte_free(tim_ring->bkt);
256 rte_mempool_free(tim_ring->chunk_pool);
257 rte_free(adptr->data->adapter_priv);
263 otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
265 const struct rte_event_timer_adapter_ops **ops)
267 struct otx2_tim_evdev *dev = tim_priv_get();
273 otx2_tim_ops.init = otx2_tim_ring_create;
274 otx2_tim_ops.uninit = otx2_tim_ring_free;
276 /* Store evdev pointer for later use. */
277 dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
278 *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
279 *ops = &otx2_tim_ops;
285 otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)
287 struct rsrc_attach_req *atch_req;
288 struct free_rsrcs_rsp *rsrc_cnt;
289 const struct rte_memzone *mz;
290 struct otx2_tim_evdev *dev;
293 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
296 mz = rte_memzone_reserve(RTE_STR(OTX2_TIM_EVDEV_NAME),
297 sizeof(struct otx2_tim_evdev),
300 otx2_tim_dbg("Unable to allocate memory for TIM Event device");
305 dev->pci_dev = pci_dev;
306 dev->mbox = cmn_dev->mbox;
307 dev->bar2 = cmn_dev->bar2;
309 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
310 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
312 otx2_err("Unable to get free rsrc count.");
316 dev->nb_rings = rsrc_cnt->tim;
318 if (!dev->nb_rings) {
319 otx2_tim_dbg("No TIM Logical functions provisioned.");
323 atch_req = otx2_mbox_alloc_msg_attach_resources(dev->mbox);
324 atch_req->modify = true;
325 atch_req->timlfs = dev->nb_rings;
327 rc = otx2_mbox_process(dev->mbox);
329 otx2_err("Unable to attach TIM rings.");
336 rte_memzone_free(mz);
342 struct otx2_tim_evdev *dev = tim_priv_get();
343 struct rsrc_detach_req *dtch_req;
345 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
348 dtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);
349 dtch_req->partial = true;
350 dtch_req->timlfs = true;
352 otx2_mbox_process(dev->mbox);
353 rte_memzone_free(rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME)));