1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_kvargs.h>
6 #include <rte_malloc.h>
7 #include <rte_mbuf_pool_ops.h>
9 #include "otx2_evdev.h"
10 #include "otx2_tim_evdev.h"
12 static struct rte_event_timer_adapter_ops otx2_tim_ops;
15 tim_get_msix_offsets(void)
17 struct otx2_tim_evdev *dev = tim_priv_get();
18 struct otx2_mbox *mbox = dev->mbox;
19 struct msix_offset_rsp *msix_rsp;
22 /* Get TIM MSIX vector offsets */
23 otx2_mbox_alloc_msg_msix_offset(mbox);
24 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
26 for (i = 0; i < dev->nb_rings; i++)
27 dev->tim_msixoff[i] = msix_rsp->timlf_msixoff[i];
33 tim_set_fp_ops(struct otx2_tim_ring *tim_ring)
35 uint8_t prod_flag = !tim_ring->prod_type_sp;
37 /* [MOD/AND] [DFB/FB] [SP][MP]*/
38 const rte_event_timer_arm_burst_t arm_burst[2][2][2][2] = {
39 #define FP(_name, _f4, _f3, _f2, _f1, flags) \
40 [_f4][_f3][_f2][_f1] = otx2_tim_arm_burst_ ## _name,
41 TIM_ARM_FASTPATH_MODES
45 const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2][2][2] = {
46 #define FP(_name, _f3, _f2, _f1, flags) \
47 [_f3][_f2][_f1] = otx2_tim_arm_tmo_tick_burst_ ## _name,
48 TIM_ARM_TMO_FASTPATH_MODES
52 otx2_tim_ops.arm_burst =
53 arm_burst[tim_ring->enable_stats][tim_ring->optimized]
54 [tim_ring->ena_dfb][prod_flag];
55 otx2_tim_ops.arm_tmo_tick_burst =
56 arm_tmo_burst[tim_ring->enable_stats][tim_ring->optimized]
58 otx2_tim_ops.cancel_burst = otx2_tim_timer_cancel_burst;
62 otx2_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,
63 struct rte_event_timer_adapter_info *adptr_info)
65 struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
67 adptr_info->max_tmo_ns = tim_ring->max_tout;
68 adptr_info->min_resolution_ns = tim_ring->ena_periodic ?
69 tim_ring->max_tout : tim_ring->tck_nsec;
70 rte_memcpy(&adptr_info->conf, &adptr->data->conf,
71 sizeof(struct rte_event_timer_adapter_conf));
75 tim_optimze_bkt_param(struct otx2_tim_ring *tim_ring)
81 hbkts = rte_align32pow2(tim_ring->nb_bkts);
82 tck_nsec = RTE_ALIGN_MUL_CEIL(tim_ring->max_tout / (hbkts - 1), 10);
84 if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
85 tim_ring->tenns_clk_freq) ||
86 hbkts > OTX2_TIM_MAX_BUCKETS))
89 lbkts = rte_align32prevpow2(tim_ring->nb_bkts);
90 tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout / (lbkts - 1)), 10);
92 if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
93 tim_ring->tenns_clk_freq) ||
94 lbkts > OTX2_TIM_MAX_BUCKETS))
101 tim_ring->nb_bkts = lbkts;
104 tim_ring->nb_bkts = hbkts;
108 tim_ring->nb_bkts = (hbkts - tim_ring->nb_bkts) <
109 (tim_ring->nb_bkts - lbkts) ? hbkts : lbkts;
111 tim_ring->optimized = true;
112 tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout /
113 (tim_ring->nb_bkts - 1)), 10);
114 otx2_tim_dbg("Optimized configured values");
115 otx2_tim_dbg("Nb_bkts : %" PRIu32 "", tim_ring->nb_bkts);
116 otx2_tim_dbg("Tck_nsec : %" PRIu64 "", tim_ring->tck_nsec);
120 tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,
121 struct rte_event_timer_adapter_conf *rcfg)
123 unsigned int cache_sz = (tim_ring->nb_chunks / 1.5);
124 unsigned int mp_flags = 0;
128 cache_sz /= rte_lcore_count();
129 /* Create chunk pool. */
130 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
131 mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
132 otx2_tim_dbg("Using single producer mode");
133 tim_ring->prod_type_sp = true;
136 snprintf(pool_name, sizeof(pool_name), "otx2_tim_chunk_pool%d",
139 if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)
140 cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;
142 if (!tim_ring->disable_npa) {
143 tim_ring->chunk_pool = rte_mempool_create_empty(pool_name,
144 tim_ring->nb_chunks, tim_ring->chunk_sz,
145 cache_sz, 0, rte_socket_id(), mp_flags);
147 if (tim_ring->chunk_pool == NULL) {
148 otx2_err("Unable to create chunkpool.");
152 rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
153 rte_mbuf_platform_mempool_ops(),
156 otx2_err("Unable to set chunkpool ops");
160 rc = rte_mempool_populate_default(tim_ring->chunk_pool);
162 otx2_err("Unable to set populate chunkpool.");
165 tim_ring->aura = npa_lf_aura_handle_to_aura(
166 tim_ring->chunk_pool->pool_id);
167 tim_ring->ena_dfb = tim_ring->ena_periodic ? 1 : 0;
169 tim_ring->chunk_pool = rte_mempool_create(pool_name,
170 tim_ring->nb_chunks, tim_ring->chunk_sz,
171 cache_sz, 0, NULL, NULL, NULL, NULL,
174 if (tim_ring->chunk_pool == NULL) {
175 otx2_err("Unable to create chunkpool.");
178 tim_ring->ena_dfb = 1;
184 rte_mempool_free(tim_ring->chunk_pool);
192 case TIM_AF_NO_RINGS_LEFT:
193 otx2_err("Unable to allocat new TIM ring.");
195 case TIM_AF_INVALID_NPA_PF_FUNC:
196 otx2_err("Invalid NPA pf func.");
198 case TIM_AF_INVALID_SSO_PF_FUNC:
199 otx2_err("Invalid SSO pf func.");
201 case TIM_AF_RING_STILL_RUNNING:
202 otx2_tim_dbg("Ring busy.");
204 case TIM_AF_LF_INVALID:
205 otx2_err("Invalid Ring id.");
207 case TIM_AF_CSIZE_NOT_ALIGNED:
208 otx2_err("Chunk size specified needs to be multiple of 16.");
210 case TIM_AF_CSIZE_TOO_SMALL:
211 otx2_err("Chunk size too small.");
213 case TIM_AF_CSIZE_TOO_BIG:
214 otx2_err("Chunk size too big.");
216 case TIM_AF_INTERVAL_TOO_SMALL:
217 otx2_err("Bucket traversal interval too small.");
219 case TIM_AF_INVALID_BIG_ENDIAN_VALUE:
220 otx2_err("Invalid Big endian value.");
222 case TIM_AF_INVALID_CLOCK_SOURCE:
223 otx2_err("Invalid Clock source specified.");
225 case TIM_AF_GPIO_CLK_SRC_NOT_ENABLED:
226 otx2_err("GPIO clock source not enabled.");
228 case TIM_AF_INVALID_BSIZE:
229 otx2_err("Invalid bucket size.");
231 case TIM_AF_INVALID_ENABLE_PERIODIC:
232 otx2_err("Invalid bucket size.");
234 case TIM_AF_INVALID_ENABLE_DONTFREE:
235 otx2_err("Invalid Don't free value.");
237 case TIM_AF_ENA_DONTFRE_NSET_PERIODIC:
238 otx2_err("Don't free bit not set when periodic is enabled.");
240 case TIM_AF_RING_ALREADY_DISABLED:
241 otx2_err("Ring already stopped");
244 otx2_err("Unknown Error.");
249 otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)
251 struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
252 struct otx2_tim_evdev *dev = tim_priv_get();
253 struct otx2_tim_ring *tim_ring;
254 struct tim_config_req *cfg_req;
255 struct tim_ring_req *free_req;
256 struct tim_lf_alloc_req *req;
257 struct tim_lf_alloc_rsp *rsp;
264 if (adptr->data->id >= dev->nb_rings)
267 req = otx2_mbox_alloc_msg_tim_lf_alloc(dev->mbox);
268 req->npa_pf_func = otx2_npa_pf_func_get();
269 req->sso_pf_func = otx2_sso_pf_func_get();
270 req->ring = adptr->data->id;
272 rc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);
278 if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10),
279 rsp->tenns_clk) < OTX2_TIM_MIN_TMO_TKS) {
280 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)
281 rcfg->timer_tick_ns = TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
290 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_PERIODIC) {
291 if (rcfg->max_tmo_ns &&
292 rcfg->max_tmo_ns != rcfg->timer_tick_ns) {
297 /* Use 2 buckets to avoid contention */
298 rcfg->max_tmo_ns = rcfg->timer_tick_ns;
299 rcfg->timer_tick_ns /= 2;
303 tim_ring = rte_zmalloc("otx2_tim_prv", sizeof(struct otx2_tim_ring), 0);
304 if (tim_ring == NULL) {
309 adptr->data->adapter_priv = tim_ring;
311 tim_ring->tenns_clk_freq = rsp->tenns_clk;
312 tim_ring->clk_src = (int)rcfg->clk_src;
313 tim_ring->ring_id = adptr->data->id;
314 tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);
315 tim_ring->max_tout = is_periodic ?
316 rcfg->timer_tick_ns * 2 : rcfg->max_tmo_ns;
317 tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
318 tim_ring->chunk_sz = dev->chunk_sz;
319 tim_ring->nb_timers = rcfg->nb_timers;
320 tim_ring->disable_npa = dev->disable_npa;
321 tim_ring->ena_periodic = is_periodic;
322 tim_ring->enable_stats = dev->enable_stats;
324 for (i = 0; i < dev->ring_ctl_cnt ; i++) {
325 struct otx2_tim_ctl *ring_ctl = &dev->ring_ctl_data[i];
327 if (ring_ctl->ring == tim_ring->ring_id) {
328 tim_ring->chunk_sz = ring_ctl->chunk_slots ?
329 ((uint32_t)(ring_ctl->chunk_slots + 1) *
330 OTX2_TIM_CHUNK_ALIGNMENT) : tim_ring->chunk_sz;
331 tim_ring->enable_stats = ring_ctl->enable_stats;
332 tim_ring->disable_npa = ring_ctl->disable_npa;
336 tim_ring->nb_chunks = tim_ring->nb_timers / OTX2_TIM_NB_CHUNK_SLOTS(
338 tim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
340 /* Try to optimize the bucket parameters. */
341 if ((rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)) {
342 if (rte_is_power_of_2(tim_ring->nb_bkts))
343 tim_ring->optimized = true;
345 tim_optimze_bkt_param(tim_ring);
348 if (tim_ring->disable_npa)
349 tim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts;
351 tim_ring->nb_chunks = tim_ring->nb_chunks + tim_ring->nb_bkts;
353 /* Create buckets. */
354 tim_ring->bkt = rte_zmalloc("otx2_tim_bucket", (tim_ring->nb_bkts) *
355 sizeof(struct otx2_tim_bkt),
356 RTE_CACHE_LINE_SIZE);
357 if (tim_ring->bkt == NULL)
360 rc = tim_chnk_pool_create(tim_ring, rcfg);
364 cfg_req = otx2_mbox_alloc_msg_tim_config_ring(dev->mbox);
366 cfg_req->ring = tim_ring->ring_id;
367 cfg_req->bigendian = false;
368 cfg_req->clocksource = tim_ring->clk_src;
369 cfg_req->enableperiodic = tim_ring->ena_periodic;
370 cfg_req->enabledontfreebuffer = tim_ring->ena_dfb;
371 cfg_req->bucketsize = tim_ring->nb_bkts;
372 cfg_req->chunksize = tim_ring->chunk_sz;
373 cfg_req->interval = NSEC2TICK(tim_ring->tck_nsec,
374 tim_ring->tenns_clk_freq);
376 rc = otx2_mbox_process(dev->mbox);
382 tim_ring->base = dev->bar2 +
383 (RVU_BLOCK_ADDR_TIM << 20 | tim_ring->ring_id << 12);
385 rc = tim_register_irq(tim_ring->ring_id);
389 otx2_write64((uint64_t)tim_ring->bkt,
390 tim_ring->base + TIM_LF_RING_BASE);
391 otx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
393 /* Set fastpath ops. */
394 tim_set_fp_ops(tim_ring);
396 /* Update SSO xae count. */
397 sso_updt_xae_cnt(sso_pmd_priv(dev->event_dev), (void *)tim_ring,
398 RTE_EVENT_TYPE_TIMER);
399 sso_xae_reconfigure(dev->event_dev);
401 otx2_tim_dbg("Total memory used %"PRIu64"MB\n",
402 (uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz)
403 + (tim_ring->nb_bkts * sizeof(struct otx2_tim_bkt))) /
409 rte_free(tim_ring->bkt);
413 free_req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
414 free_req->ring = adptr->data->id;
415 otx2_mbox_process(dev->mbox);
420 otx2_tim_calibrate_start_tsc(struct otx2_tim_ring *tim_ring)
422 #define OTX2_TIM_CALIB_ITER 1E6
423 uint32_t real_bkt, bucket;
424 int icount, ecount = 0;
427 for (icount = 0; icount < OTX2_TIM_CALIB_ITER; icount++) {
428 real_bkt = otx2_read64(tim_ring->base + TIM_LF_RING_REL) >> 44;
429 bkt_cyc = rte_rdtsc();
430 bucket = (bkt_cyc - tim_ring->ring_start_cyc) /
432 bucket = bucket % (tim_ring->nb_bkts);
433 tim_ring->ring_start_cyc = bkt_cyc - (real_bkt *
435 if (bucket != real_bkt)
438 tim_ring->last_updt_cyc = bkt_cyc;
439 otx2_tim_dbg("Bucket mispredict %3.2f distance %d\n",
440 100 - (((double)(icount - ecount) / (double)icount) * 100),
445 otx2_tim_ring_start(const struct rte_event_timer_adapter *adptr)
447 struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
448 struct otx2_tim_evdev *dev = tim_priv_get();
449 struct tim_enable_rsp *rsp;
450 struct tim_ring_req *req;
456 req = otx2_mbox_alloc_msg_tim_enable_ring(dev->mbox);
457 req->ring = tim_ring->ring_id;
459 rc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);
464 #ifdef RTE_ARM_EAL_RDTSC_USE_PMU
465 uint64_t tenns_stmp, tenns_diff;
468 pmu_stmp = rte_rdtsc();
469 asm volatile("mrs %0, cntvct_el0" : "=r" (tenns_stmp));
471 tenns_diff = tenns_stmp - rsp->timestarted;
472 pmu_stmp = pmu_stmp - (NSEC2TICK(tenns_diff * 10, rte_get_timer_hz()));
473 tim_ring->ring_start_cyc = pmu_stmp;
475 tim_ring->ring_start_cyc = rsp->timestarted;
477 tim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, rte_get_timer_hz());
478 tim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts;
479 tim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int);
481 otx2_tim_calibrate_start_tsc(tim_ring);
488 otx2_tim_ring_stop(const struct rte_event_timer_adapter *adptr)
490 struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
491 struct otx2_tim_evdev *dev = tim_priv_get();
492 struct tim_ring_req *req;
498 req = otx2_mbox_alloc_msg_tim_disable_ring(dev->mbox);
499 req->ring = tim_ring->ring_id;
501 rc = otx2_mbox_process(dev->mbox);
511 otx2_tim_ring_free(struct rte_event_timer_adapter *adptr)
513 struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
514 struct otx2_tim_evdev *dev = tim_priv_get();
515 struct tim_ring_req *req;
521 tim_unregister_irq(tim_ring->ring_id);
523 req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
524 req->ring = tim_ring->ring_id;
526 rc = otx2_mbox_process(dev->mbox);
532 rte_free(tim_ring->bkt);
533 rte_mempool_free(tim_ring->chunk_pool);
534 rte_free(adptr->data->adapter_priv);
540 otx2_tim_stats_get(const struct rte_event_timer_adapter *adapter,
541 struct rte_event_timer_adapter_stats *stats)
543 struct otx2_tim_ring *tim_ring = adapter->data->adapter_priv;
544 uint64_t bkt_cyc = rte_rdtsc() - tim_ring->ring_start_cyc;
547 stats->evtim_exp_count = __atomic_load_n(&tim_ring->arm_cnt,
549 stats->ev_enq_count = stats->evtim_exp_count;
550 stats->adapter_tick_count = rte_reciprocal_divide_u64(bkt_cyc,
551 &tim_ring->fast_div);
556 otx2_tim_stats_reset(const struct rte_event_timer_adapter *adapter)
558 struct otx2_tim_ring *tim_ring = adapter->data->adapter_priv;
560 __atomic_store_n(&tim_ring->arm_cnt, 0, __ATOMIC_RELAXED);
565 otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
567 const struct rte_event_timer_adapter_ops **ops)
569 struct otx2_tim_evdev *dev = tim_priv_get();
576 otx2_tim_ops.init = otx2_tim_ring_create;
577 otx2_tim_ops.uninit = otx2_tim_ring_free;
578 otx2_tim_ops.start = otx2_tim_ring_start;
579 otx2_tim_ops.stop = otx2_tim_ring_stop;
580 otx2_tim_ops.get_info = otx2_tim_ring_info_get;
582 if (dev->enable_stats) {
583 otx2_tim_ops.stats_get = otx2_tim_stats_get;
584 otx2_tim_ops.stats_reset = otx2_tim_stats_reset;
587 /* Store evdev pointer for later use. */
588 dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
589 *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT |
590 RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC;
591 *ops = &otx2_tim_ops;
596 #define OTX2_TIM_DISABLE_NPA "tim_disable_npa"
597 #define OTX2_TIM_CHNK_SLOTS "tim_chnk_slots"
598 #define OTX2_TIM_STATS_ENA "tim_stats_ena"
599 #define OTX2_TIM_RINGS_LMT "tim_rings_lmt"
600 #define OTX2_TIM_RING_CTL "tim_ring_ctl"
603 tim_parse_ring_param(char *value, void *opaque)
605 struct otx2_tim_evdev *dev = opaque;
606 struct otx2_tim_ctl ring_ctl = {0};
607 char *tok = strtok(value, "-");
608 struct otx2_tim_ctl *old_ptr;
611 val = (uint16_t *)&ring_ctl;
616 while (tok != NULL) {
618 tok = strtok(NULL, "-");
622 if (val != (&ring_ctl.enable_stats + 1)) {
624 "Invalid ring param expected [ring-chunk_sz-disable_npa-enable_stats]");
629 old_ptr = dev->ring_ctl_data;
630 dev->ring_ctl_data = rte_realloc(dev->ring_ctl_data,
631 sizeof(struct otx2_tim_ctl) *
632 dev->ring_ctl_cnt, 0);
633 if (dev->ring_ctl_data == NULL) {
634 dev->ring_ctl_data = old_ptr;
639 dev->ring_ctl_data[dev->ring_ctl_cnt - 1] = ring_ctl;
643 tim_parse_ring_ctl_list(const char *value, void *opaque)
645 char *s = strdup(value);
656 if (start && start < end) {
658 tim_parse_ring_param(start + 1, opaque);
669 tim_parse_kvargs_dict(const char *key, const char *value, void *opaque)
673 /* Dict format [ring-chunk_sz-disable_npa-enable_stats] use '-' as ','
674 * isn't allowed. 0 represents default.
676 tim_parse_ring_ctl_list(value, opaque);
682 tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)
684 struct rte_kvargs *kvlist;
689 kvlist = rte_kvargs_parse(devargs->args, NULL);
693 rte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA,
694 &parse_kvargs_flag, &dev->disable_npa);
695 rte_kvargs_process(kvlist, OTX2_TIM_CHNK_SLOTS,
696 &parse_kvargs_value, &dev->chunk_slots);
697 rte_kvargs_process(kvlist, OTX2_TIM_STATS_ENA, &parse_kvargs_flag,
699 rte_kvargs_process(kvlist, OTX2_TIM_RINGS_LMT, &parse_kvargs_value,
701 rte_kvargs_process(kvlist, OTX2_TIM_RING_CTL,
702 &tim_parse_kvargs_dict, &dev);
704 rte_kvargs_free(kvlist);
708 otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)
710 struct rsrc_attach_req *atch_req;
711 struct rsrc_detach_req *dtch_req;
712 struct free_rsrcs_rsp *rsrc_cnt;
713 const struct rte_memzone *mz;
714 struct otx2_tim_evdev *dev;
717 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
720 mz = rte_memzone_reserve(RTE_STR(OTX2_TIM_EVDEV_NAME),
721 sizeof(struct otx2_tim_evdev),
724 otx2_tim_dbg("Unable to allocate memory for TIM Event device");
729 dev->pci_dev = pci_dev;
730 dev->mbox = cmn_dev->mbox;
731 dev->bar2 = cmn_dev->bar2;
733 tim_parse_devargs(pci_dev->device.devargs, dev);
735 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
736 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
738 otx2_err("Unable to get free rsrc count.");
742 dev->nb_rings = dev->min_ring_cnt ?
743 RTE_MIN(dev->min_ring_cnt, rsrc_cnt->tim) : rsrc_cnt->tim;
745 if (!dev->nb_rings) {
746 otx2_tim_dbg("No TIM Logical functions provisioned.");
750 atch_req = otx2_mbox_alloc_msg_attach_resources(dev->mbox);
751 atch_req->modify = true;
752 atch_req->timlfs = dev->nb_rings;
754 rc = otx2_mbox_process(dev->mbox);
756 otx2_err("Unable to attach TIM rings.");
760 rc = tim_get_msix_offsets();
762 otx2_err("Unable to get MSIX offsets for TIM.");
766 if (dev->chunk_slots &&
767 dev->chunk_slots <= OTX2_TIM_MAX_CHUNK_SLOTS &&
768 dev->chunk_slots >= OTX2_TIM_MIN_CHUNK_SLOTS) {
769 dev->chunk_sz = (dev->chunk_slots + 1) *
770 OTX2_TIM_CHUNK_ALIGNMENT;
772 dev->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ;
778 dtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);
779 dtch_req->partial = true;
780 dtch_req->timlfs = true;
782 otx2_mbox_process(dev->mbox);
784 rte_memzone_free(mz);
790 struct otx2_tim_evdev *dev = tim_priv_get();
791 struct rsrc_detach_req *dtch_req;
793 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
796 dtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);
797 dtch_req->partial = true;
798 dtch_req->timlfs = true;
800 otx2_mbox_process(dev->mbox);
801 rte_memzone_free(rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME)));