1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_kvargs.h>
6 #include <rte_malloc.h>
7 #include <rte_mbuf_pool_ops.h>
9 #include "otx2_evdev.h"
10 #include "otx2_tim_evdev.h"
12 static struct rte_event_timer_adapter_ops otx2_tim_ops;
15 tim_get_msix_offsets(void)
17 struct otx2_tim_evdev *dev = tim_priv_get();
18 struct otx2_mbox *mbox = dev->mbox;
19 struct msix_offset_rsp *msix_rsp;
22 /* Get TIM MSIX vector offsets */
23 otx2_mbox_alloc_msg_msix_offset(mbox);
24 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
26 for (i = 0; i < dev->nb_rings; i++)
27 dev->tim_msixoff[i] = msix_rsp->timlf_msixoff[i];
33 tim_set_fp_ops(struct otx2_tim_ring *tim_ring)
35 uint8_t prod_flag = !tim_ring->prod_type_sp;
37 /* [MOD/AND] [DFB/FB] [SP][MP]*/
38 const rte_event_timer_arm_burst_t arm_burst[2][2][2] = {
39 #define FP(_name, _f3, _f2, _f1, flags) \
40 [_f3][_f2][_f1] = otx2_tim_arm_burst_ ## _name,
41 TIM_ARM_FASTPATH_MODES
45 otx2_tim_ops.arm_burst = arm_burst[tim_ring->optimized]
46 [tim_ring->ena_dfb][prod_flag];
50 otx2_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,
51 struct rte_event_timer_adapter_info *adptr_info)
53 struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
55 adptr_info->max_tmo_ns = tim_ring->max_tout;
56 adptr_info->min_resolution_ns = tim_ring->tck_nsec;
57 rte_memcpy(&adptr_info->conf, &adptr->data->conf,
58 sizeof(struct rte_event_timer_adapter_conf));
62 tim_optimze_bkt_param(struct otx2_tim_ring *tim_ring)
68 hbkts = rte_align32pow2(tim_ring->nb_bkts);
69 tck_nsec = RTE_ALIGN_MUL_CEIL(tim_ring->max_tout / (hbkts - 1), 10);
71 if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
72 tim_ring->tenns_clk_freq) ||
73 hbkts > OTX2_TIM_MAX_BUCKETS))
76 lbkts = rte_align32prevpow2(tim_ring->nb_bkts);
77 tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout / (lbkts - 1)), 10);
79 if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
80 tim_ring->tenns_clk_freq) ||
81 lbkts > OTX2_TIM_MAX_BUCKETS))
88 tim_ring->nb_bkts = lbkts;
91 tim_ring->nb_bkts = hbkts;
95 tim_ring->nb_bkts = (hbkts - tim_ring->nb_bkts) <
96 (tim_ring->nb_bkts - lbkts) ? hbkts : lbkts;
98 tim_ring->optimized = true;
99 tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout /
100 (tim_ring->nb_bkts - 1)), 10);
101 otx2_tim_dbg("Optimized configured values");
102 otx2_tim_dbg("Nb_bkts : %" PRIu32 "", tim_ring->nb_bkts);
103 otx2_tim_dbg("Tck_nsec : %" PRIu64 "", tim_ring->tck_nsec);
107 tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,
108 struct rte_event_timer_adapter_conf *rcfg)
110 unsigned int cache_sz = (tim_ring->nb_chunks / 1.5);
111 unsigned int mp_flags = 0;
115 /* Create chunk pool. */
116 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
117 mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
118 otx2_tim_dbg("Using single producer mode");
119 tim_ring->prod_type_sp = true;
122 snprintf(pool_name, sizeof(pool_name), "otx2_tim_chunk_pool%d",
125 if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)
126 cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;
128 if (!tim_ring->disable_npa) {
129 /* NPA need not have cache as free is not visible to SW */
130 tim_ring->chunk_pool = rte_mempool_create_empty(pool_name,
131 tim_ring->nb_chunks, tim_ring->chunk_sz,
132 0, 0, rte_socket_id(), mp_flags);
134 if (tim_ring->chunk_pool == NULL) {
135 otx2_err("Unable to create chunkpool.");
139 rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
140 rte_mbuf_platform_mempool_ops(),
143 otx2_err("Unable to set chunkpool ops");
147 rc = rte_mempool_populate_default(tim_ring->chunk_pool);
149 otx2_err("Unable to set populate chunkpool.");
152 tim_ring->aura = npa_lf_aura_handle_to_aura(
153 tim_ring->chunk_pool->pool_id);
154 tim_ring->ena_dfb = 0;
156 tim_ring->chunk_pool = rte_mempool_create(pool_name,
157 tim_ring->nb_chunks, tim_ring->chunk_sz,
158 cache_sz, 0, NULL, NULL, NULL, NULL,
161 if (tim_ring->chunk_pool == NULL) {
162 otx2_err("Unable to create chunkpool.");
165 tim_ring->ena_dfb = 1;
171 rte_mempool_free(tim_ring->chunk_pool);
179 case TIM_AF_NO_RINGS_LEFT:
180 otx2_err("Unable to allocat new TIM ring.");
182 case TIM_AF_INVALID_NPA_PF_FUNC:
183 otx2_err("Invalid NPA pf func.");
185 case TIM_AF_INVALID_SSO_PF_FUNC:
186 otx2_err("Invalid SSO pf func.");
188 case TIM_AF_RING_STILL_RUNNING:
189 otx2_tim_dbg("Ring busy.");
191 case TIM_AF_LF_INVALID:
192 otx2_err("Invalid Ring id.");
194 case TIM_AF_CSIZE_NOT_ALIGNED:
195 otx2_err("Chunk size specified needs to be multiple of 16.");
197 case TIM_AF_CSIZE_TOO_SMALL:
198 otx2_err("Chunk size too small.");
200 case TIM_AF_CSIZE_TOO_BIG:
201 otx2_err("Chunk size too big.");
203 case TIM_AF_INTERVAL_TOO_SMALL:
204 otx2_err("Bucket traversal interval too small.");
206 case TIM_AF_INVALID_BIG_ENDIAN_VALUE:
207 otx2_err("Invalid Big endian value.");
209 case TIM_AF_INVALID_CLOCK_SOURCE:
210 otx2_err("Invalid Clock source specified.");
212 case TIM_AF_GPIO_CLK_SRC_NOT_ENABLED:
213 otx2_err("GPIO clock source not enabled.");
215 case TIM_AF_INVALID_BSIZE:
216 otx2_err("Invalid bucket size.");
218 case TIM_AF_INVALID_ENABLE_PERIODIC:
219 otx2_err("Invalid bucket size.");
221 case TIM_AF_INVALID_ENABLE_DONTFREE:
222 otx2_err("Invalid Don't free value.");
224 case TIM_AF_ENA_DONTFRE_NSET_PERIODIC:
225 otx2_err("Don't free bit not set when periodic is enabled.");
227 case TIM_AF_RING_ALREADY_DISABLED:
228 otx2_err("Ring already stopped");
231 otx2_err("Unknown Error.");
236 otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)
238 struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
239 struct otx2_tim_evdev *dev = tim_priv_get();
240 struct otx2_tim_ring *tim_ring;
241 struct tim_config_req *cfg_req;
242 struct tim_ring_req *free_req;
243 struct tim_lf_alloc_req *req;
244 struct tim_lf_alloc_rsp *rsp;
251 if (adptr->data->id >= dev->nb_rings)
254 req = otx2_mbox_alloc_msg_tim_lf_alloc(dev->mbox);
255 req->npa_pf_func = otx2_npa_pf_func_get();
256 req->sso_pf_func = otx2_sso_pf_func_get();
257 req->ring = adptr->data->id;
259 rc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);
265 if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10),
266 rsp->tenns_clk) < OTX2_TIM_MIN_TMO_TKS) {
267 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)
268 rcfg->timer_tick_ns = TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
276 tim_ring = rte_zmalloc("otx2_tim_prv", sizeof(struct otx2_tim_ring), 0);
277 if (tim_ring == NULL) {
282 adptr->data->adapter_priv = tim_ring;
284 tim_ring->tenns_clk_freq = rsp->tenns_clk;
285 tim_ring->clk_src = (int)rcfg->clk_src;
286 tim_ring->ring_id = adptr->data->id;
287 tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);
288 tim_ring->max_tout = rcfg->max_tmo_ns;
289 tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
290 tim_ring->chunk_sz = dev->chunk_sz;
291 nb_timers = rcfg->nb_timers;
292 tim_ring->disable_npa = dev->disable_npa;
294 tim_ring->nb_chunks = nb_timers / OTX2_TIM_NB_CHUNK_SLOTS(
296 tim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
298 /* Try to optimize the bucket parameters. */
299 if ((rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)) {
300 if (rte_is_power_of_2(tim_ring->nb_bkts))
301 tim_ring->optimized = true;
303 tim_optimze_bkt_param(tim_ring);
306 tim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts;
307 /* Create buckets. */
308 tim_ring->bkt = rte_zmalloc("otx2_tim_bucket", (tim_ring->nb_bkts) *
309 sizeof(struct otx2_tim_bkt),
310 RTE_CACHE_LINE_SIZE);
311 if (tim_ring->bkt == NULL)
314 rc = tim_chnk_pool_create(tim_ring, rcfg);
318 cfg_req = otx2_mbox_alloc_msg_tim_config_ring(dev->mbox);
320 cfg_req->ring = tim_ring->ring_id;
321 cfg_req->bigendian = false;
322 cfg_req->clocksource = tim_ring->clk_src;
323 cfg_req->enableperiodic = false;
324 cfg_req->enabledontfreebuffer = tim_ring->ena_dfb;
325 cfg_req->bucketsize = tim_ring->nb_bkts;
326 cfg_req->chunksize = tim_ring->chunk_sz;
327 cfg_req->interval = NSEC2TICK(tim_ring->tck_nsec,
328 tim_ring->tenns_clk_freq);
330 rc = otx2_mbox_process(dev->mbox);
336 tim_ring->base = dev->bar2 +
337 (RVU_BLOCK_ADDR_TIM << 20 | tim_ring->ring_id << 12);
339 rc = tim_register_irq(tim_ring->ring_id);
343 otx2_write64((uint64_t)tim_ring->bkt,
344 tim_ring->base + TIM_LF_RING_BASE);
345 otx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
347 /* Set fastpath ops. */
348 tim_set_fp_ops(tim_ring);
350 /* Update SSO xae count. */
351 sso_updt_xae_cnt(sso_pmd_priv(dev->event_dev), (void *)&nb_timers,
352 RTE_EVENT_TYPE_TIMER);
353 sso_xae_reconfigure(dev->event_dev);
358 rte_free(tim_ring->bkt);
362 free_req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
363 free_req->ring = adptr->data->id;
364 otx2_mbox_process(dev->mbox);
369 otx2_tim_ring_free(struct rte_event_timer_adapter *adptr)
371 struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
372 struct otx2_tim_evdev *dev = tim_priv_get();
373 struct tim_ring_req *req;
379 tim_unregister_irq(tim_ring->ring_id);
381 req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
382 req->ring = tim_ring->ring_id;
384 rc = otx2_mbox_process(dev->mbox);
390 rte_free(tim_ring->bkt);
391 rte_mempool_free(tim_ring->chunk_pool);
392 rte_free(adptr->data->adapter_priv);
398 otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
400 const struct rte_event_timer_adapter_ops **ops)
402 struct otx2_tim_evdev *dev = tim_priv_get();
408 otx2_tim_ops.init = otx2_tim_ring_create;
409 otx2_tim_ops.uninit = otx2_tim_ring_free;
410 otx2_tim_ops.get_info = otx2_tim_ring_info_get;
412 /* Store evdev pointer for later use. */
413 dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
414 *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
415 *ops = &otx2_tim_ops;
420 #define OTX2_TIM_DISABLE_NPA "tim_disable_npa"
421 #define OTX2_TIM_CHNK_SLOTS "tim_chnk_slots"
424 tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)
426 struct rte_kvargs *kvlist;
431 kvlist = rte_kvargs_parse(devargs->args, NULL);
435 rte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA,
436 &parse_kvargs_flag, &dev->disable_npa);
437 rte_kvargs_process(kvlist, OTX2_TIM_CHNK_SLOTS,
438 &parse_kvargs_value, &dev->chunk_slots);
442 otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)
444 struct rsrc_attach_req *atch_req;
445 struct rsrc_detach_req *dtch_req;
446 struct free_rsrcs_rsp *rsrc_cnt;
447 const struct rte_memzone *mz;
448 struct otx2_tim_evdev *dev;
451 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
454 mz = rte_memzone_reserve(RTE_STR(OTX2_TIM_EVDEV_NAME),
455 sizeof(struct otx2_tim_evdev),
458 otx2_tim_dbg("Unable to allocate memory for TIM Event device");
463 dev->pci_dev = pci_dev;
464 dev->mbox = cmn_dev->mbox;
465 dev->bar2 = cmn_dev->bar2;
467 tim_parse_devargs(pci_dev->device.devargs, dev);
469 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
470 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
472 otx2_err("Unable to get free rsrc count.");
476 dev->nb_rings = rsrc_cnt->tim;
478 if (!dev->nb_rings) {
479 otx2_tim_dbg("No TIM Logical functions provisioned.");
483 atch_req = otx2_mbox_alloc_msg_attach_resources(dev->mbox);
484 atch_req->modify = true;
485 atch_req->timlfs = dev->nb_rings;
487 rc = otx2_mbox_process(dev->mbox);
489 otx2_err("Unable to attach TIM rings.");
493 rc = tim_get_msix_offsets();
495 otx2_err("Unable to get MSIX offsets for TIM.");
499 if (dev->chunk_slots &&
500 dev->chunk_slots <= OTX2_TIM_MAX_CHUNK_SLOTS &&
501 dev->chunk_slots >= OTX2_TIM_MIN_CHUNK_SLOTS) {
502 dev->chunk_sz = (dev->chunk_slots + 1) *
503 OTX2_TIM_CHUNK_ALIGNMENT;
505 dev->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ;
511 dtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);
512 dtch_req->partial = true;
513 dtch_req->timlfs = true;
515 otx2_mbox_process(dev->mbox);
517 rte_memzone_free(mz);
523 struct otx2_tim_evdev *dev = tim_priv_get();
524 struct rsrc_detach_req *dtch_req;
526 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
529 dtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);
530 dtch_req->partial = true;
531 dtch_req->timlfs = true;
533 otx2_mbox_process(dev->mbox);
534 rte_memzone_free(rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME)));