1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_kvargs.h>
6 #include <rte_malloc.h>
7 #include <rte_mbuf_pool_ops.h>
9 #include "otx2_evdev.h"
10 #include "otx2_tim_evdev.h"
12 static struct rte_event_timer_adapter_ops otx2_tim_ops;
15 tim_get_msix_offsets(void)
17 struct otx2_tim_evdev *dev = tim_priv_get();
18 struct otx2_mbox *mbox = dev->mbox;
19 struct msix_offset_rsp *msix_rsp;
22 /* Get TIM MSIX vector offsets */
23 otx2_mbox_alloc_msg_msix_offset(mbox);
24 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
26 for (i = 0; i < dev->nb_rings; i++)
27 dev->tim_msixoff[i] = msix_rsp->timlf_msixoff[i];
33 tim_set_fp_ops(struct otx2_tim_ring *tim_ring)
35 uint8_t prod_flag = !tim_ring->prod_type_sp;
37 /* [MOD/AND] [DFB/FB] [SP][MP]*/
38 const rte_event_timer_arm_burst_t arm_burst[2][2][2][2] = {
39 #define FP(_name, _f4, _f3, _f2, _f1, flags) \
40 [_f4][_f3][_f2][_f1] = otx2_tim_arm_burst_ ## _name,
41 TIM_ARM_FASTPATH_MODES
45 const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2][2][2] = {
46 #define FP(_name, _f3, _f2, _f1, flags) \
47 [_f3][_f2][_f1] = otx2_tim_arm_tmo_tick_burst_ ## _name,
48 TIM_ARM_TMO_FASTPATH_MODES
52 otx2_tim_ops.arm_burst =
53 arm_burst[tim_ring->enable_stats][tim_ring->optimized]
54 [tim_ring->ena_dfb][prod_flag];
55 otx2_tim_ops.arm_tmo_tick_burst =
56 arm_tmo_burst[tim_ring->enable_stats][tim_ring->optimized]
58 otx2_tim_ops.cancel_burst = otx2_tim_timer_cancel_burst;
62 otx2_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,
63 struct rte_event_timer_adapter_info *adptr_info)
65 struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
67 adptr_info->max_tmo_ns = tim_ring->max_tout;
68 adptr_info->min_resolution_ns = tim_ring->tck_nsec;
69 rte_memcpy(&adptr_info->conf, &adptr->data->conf,
70 sizeof(struct rte_event_timer_adapter_conf));
74 tim_optimze_bkt_param(struct otx2_tim_ring *tim_ring)
80 hbkts = rte_align32pow2(tim_ring->nb_bkts);
81 tck_nsec = RTE_ALIGN_MUL_CEIL(tim_ring->max_tout / (hbkts - 1), 10);
83 if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
84 tim_ring->tenns_clk_freq) ||
85 hbkts > OTX2_TIM_MAX_BUCKETS))
88 lbkts = rte_align32prevpow2(tim_ring->nb_bkts);
89 tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout / (lbkts - 1)), 10);
91 if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
92 tim_ring->tenns_clk_freq) ||
93 lbkts > OTX2_TIM_MAX_BUCKETS))
100 tim_ring->nb_bkts = lbkts;
103 tim_ring->nb_bkts = hbkts;
107 tim_ring->nb_bkts = (hbkts - tim_ring->nb_bkts) <
108 (tim_ring->nb_bkts - lbkts) ? hbkts : lbkts;
110 tim_ring->optimized = true;
111 tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout /
112 (tim_ring->nb_bkts - 1)), 10);
113 otx2_tim_dbg("Optimized configured values");
114 otx2_tim_dbg("Nb_bkts : %" PRIu32 "", tim_ring->nb_bkts);
115 otx2_tim_dbg("Tck_nsec : %" PRIu64 "", tim_ring->tck_nsec);
119 tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,
120 struct rte_event_timer_adapter_conf *rcfg)
122 unsigned int cache_sz = (tim_ring->nb_chunks / 1.5);
123 unsigned int mp_flags = 0;
127 /* Create chunk pool. */
128 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
129 mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
130 otx2_tim_dbg("Using single producer mode");
131 tim_ring->prod_type_sp = true;
134 snprintf(pool_name, sizeof(pool_name), "otx2_tim_chunk_pool%d",
137 if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)
138 cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;
140 if (!tim_ring->disable_npa) {
141 /* NPA need not have cache as free is not visible to SW */
142 tim_ring->chunk_pool = rte_mempool_create_empty(pool_name,
143 tim_ring->nb_chunks, tim_ring->chunk_sz,
144 0, 0, rte_socket_id(), mp_flags);
146 if (tim_ring->chunk_pool == NULL) {
147 otx2_err("Unable to create chunkpool.");
151 rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
152 rte_mbuf_platform_mempool_ops(),
155 otx2_err("Unable to set chunkpool ops");
159 rc = rte_mempool_populate_default(tim_ring->chunk_pool);
161 otx2_err("Unable to set populate chunkpool.");
164 tim_ring->aura = npa_lf_aura_handle_to_aura(
165 tim_ring->chunk_pool->pool_id);
166 tim_ring->ena_dfb = 0;
168 tim_ring->chunk_pool = rte_mempool_create(pool_name,
169 tim_ring->nb_chunks, tim_ring->chunk_sz,
170 cache_sz, 0, NULL, NULL, NULL, NULL,
173 if (tim_ring->chunk_pool == NULL) {
174 otx2_err("Unable to create chunkpool.");
177 tim_ring->ena_dfb = 1;
183 rte_mempool_free(tim_ring->chunk_pool);
191 case TIM_AF_NO_RINGS_LEFT:
192 otx2_err("Unable to allocat new TIM ring.");
194 case TIM_AF_INVALID_NPA_PF_FUNC:
195 otx2_err("Invalid NPA pf func.");
197 case TIM_AF_INVALID_SSO_PF_FUNC:
198 otx2_err("Invalid SSO pf func.");
200 case TIM_AF_RING_STILL_RUNNING:
201 otx2_tim_dbg("Ring busy.");
203 case TIM_AF_LF_INVALID:
204 otx2_err("Invalid Ring id.");
206 case TIM_AF_CSIZE_NOT_ALIGNED:
207 otx2_err("Chunk size specified needs to be multiple of 16.");
209 case TIM_AF_CSIZE_TOO_SMALL:
210 otx2_err("Chunk size too small.");
212 case TIM_AF_CSIZE_TOO_BIG:
213 otx2_err("Chunk size too big.");
215 case TIM_AF_INTERVAL_TOO_SMALL:
216 otx2_err("Bucket traversal interval too small.");
218 case TIM_AF_INVALID_BIG_ENDIAN_VALUE:
219 otx2_err("Invalid Big endian value.");
221 case TIM_AF_INVALID_CLOCK_SOURCE:
222 otx2_err("Invalid Clock source specified.");
224 case TIM_AF_GPIO_CLK_SRC_NOT_ENABLED:
225 otx2_err("GPIO clock source not enabled.");
227 case TIM_AF_INVALID_BSIZE:
228 otx2_err("Invalid bucket size.");
230 case TIM_AF_INVALID_ENABLE_PERIODIC:
231 otx2_err("Invalid bucket size.");
233 case TIM_AF_INVALID_ENABLE_DONTFREE:
234 otx2_err("Invalid Don't free value.");
236 case TIM_AF_ENA_DONTFRE_NSET_PERIODIC:
237 otx2_err("Don't free bit not set when periodic is enabled.");
239 case TIM_AF_RING_ALREADY_DISABLED:
240 otx2_err("Ring already stopped");
243 otx2_err("Unknown Error.");
248 otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)
250 struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
251 struct otx2_tim_evdev *dev = tim_priv_get();
252 struct otx2_tim_ring *tim_ring;
253 struct tim_config_req *cfg_req;
254 struct tim_ring_req *free_req;
255 struct tim_lf_alloc_req *req;
256 struct tim_lf_alloc_rsp *rsp;
263 if (adptr->data->id >= dev->nb_rings)
266 req = otx2_mbox_alloc_msg_tim_lf_alloc(dev->mbox);
267 req->npa_pf_func = otx2_npa_pf_func_get();
268 req->sso_pf_func = otx2_sso_pf_func_get();
269 req->ring = adptr->data->id;
271 rc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);
277 if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10),
278 rsp->tenns_clk) < OTX2_TIM_MIN_TMO_TKS) {
279 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)
280 rcfg->timer_tick_ns = TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
288 tim_ring = rte_zmalloc("otx2_tim_prv", sizeof(struct otx2_tim_ring), 0);
289 if (tim_ring == NULL) {
294 adptr->data->adapter_priv = tim_ring;
296 tim_ring->tenns_clk_freq = rsp->tenns_clk;
297 tim_ring->clk_src = (int)rcfg->clk_src;
298 tim_ring->ring_id = adptr->data->id;
299 tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);
300 tim_ring->max_tout = rcfg->max_tmo_ns;
301 tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
302 tim_ring->chunk_sz = dev->chunk_sz;
303 nb_timers = rcfg->nb_timers;
304 tim_ring->disable_npa = dev->disable_npa;
305 tim_ring->enable_stats = dev->enable_stats;
307 tim_ring->nb_chunks = nb_timers / OTX2_TIM_NB_CHUNK_SLOTS(
309 tim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
311 /* Try to optimize the bucket parameters. */
312 if ((rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)) {
313 if (rte_is_power_of_2(tim_ring->nb_bkts))
314 tim_ring->optimized = true;
316 tim_optimze_bkt_param(tim_ring);
319 tim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts;
320 /* Create buckets. */
321 tim_ring->bkt = rte_zmalloc("otx2_tim_bucket", (tim_ring->nb_bkts) *
322 sizeof(struct otx2_tim_bkt),
323 RTE_CACHE_LINE_SIZE);
324 if (tim_ring->bkt == NULL)
327 rc = tim_chnk_pool_create(tim_ring, rcfg);
331 cfg_req = otx2_mbox_alloc_msg_tim_config_ring(dev->mbox);
333 cfg_req->ring = tim_ring->ring_id;
334 cfg_req->bigendian = false;
335 cfg_req->clocksource = tim_ring->clk_src;
336 cfg_req->enableperiodic = false;
337 cfg_req->enabledontfreebuffer = tim_ring->ena_dfb;
338 cfg_req->bucketsize = tim_ring->nb_bkts;
339 cfg_req->chunksize = tim_ring->chunk_sz;
340 cfg_req->interval = NSEC2TICK(tim_ring->tck_nsec,
341 tim_ring->tenns_clk_freq);
343 rc = otx2_mbox_process(dev->mbox);
349 tim_ring->base = dev->bar2 +
350 (RVU_BLOCK_ADDR_TIM << 20 | tim_ring->ring_id << 12);
352 rc = tim_register_irq(tim_ring->ring_id);
356 otx2_write64((uint64_t)tim_ring->bkt,
357 tim_ring->base + TIM_LF_RING_BASE);
358 otx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
360 /* Set fastpath ops. */
361 tim_set_fp_ops(tim_ring);
363 /* Update SSO xae count. */
364 sso_updt_xae_cnt(sso_pmd_priv(dev->event_dev), (void *)&nb_timers,
365 RTE_EVENT_TYPE_TIMER);
366 sso_xae_reconfigure(dev->event_dev);
371 rte_free(tim_ring->bkt);
375 free_req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
376 free_req->ring = adptr->data->id;
377 otx2_mbox_process(dev->mbox);
382 otx2_tim_ring_free(struct rte_event_timer_adapter *adptr)
384 struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
385 struct otx2_tim_evdev *dev = tim_priv_get();
386 struct tim_ring_req *req;
392 tim_unregister_irq(tim_ring->ring_id);
394 req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
395 req->ring = tim_ring->ring_id;
397 rc = otx2_mbox_process(dev->mbox);
403 rte_free(tim_ring->bkt);
404 rte_mempool_free(tim_ring->chunk_pool);
405 rte_free(adptr->data->adapter_priv);
411 otx2_tim_stats_get(const struct rte_event_timer_adapter *adapter,
412 struct rte_event_timer_adapter_stats *stats)
414 struct otx2_tim_ring *tim_ring = adapter->data->adapter_priv;
415 uint64_t bkt_cyc = rte_rdtsc() - tim_ring->ring_start_cyc;
418 stats->evtim_exp_count = rte_atomic64_read(&tim_ring->arm_cnt);
419 stats->ev_enq_count = stats->evtim_exp_count;
420 stats->adapter_tick_count = rte_reciprocal_divide_u64(bkt_cyc,
421 &tim_ring->fast_div);
426 otx2_tim_stats_reset(const struct rte_event_timer_adapter *adapter)
428 struct otx2_tim_ring *tim_ring = adapter->data->adapter_priv;
430 rte_atomic64_clear(&tim_ring->arm_cnt);
435 otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
437 const struct rte_event_timer_adapter_ops **ops)
439 struct otx2_tim_evdev *dev = tim_priv_get();
445 otx2_tim_ops.init = otx2_tim_ring_create;
446 otx2_tim_ops.uninit = otx2_tim_ring_free;
447 otx2_tim_ops.get_info = otx2_tim_ring_info_get;
449 if (dev->enable_stats) {
450 otx2_tim_ops.stats_get = otx2_tim_stats_get;
451 otx2_tim_ops.stats_reset = otx2_tim_stats_reset;
454 /* Store evdev pointer for later use. */
455 dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
456 *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
457 *ops = &otx2_tim_ops;
462 #define OTX2_TIM_DISABLE_NPA "tim_disable_npa"
463 #define OTX2_TIM_CHNK_SLOTS "tim_chnk_slots"
464 #define OTX2_TIM_STATS_ENA "tim_stats_ena"
467 tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)
469 struct rte_kvargs *kvlist;
474 kvlist = rte_kvargs_parse(devargs->args, NULL);
478 rte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA,
479 &parse_kvargs_flag, &dev->disable_npa);
480 rte_kvargs_process(kvlist, OTX2_TIM_CHNK_SLOTS,
481 &parse_kvargs_value, &dev->chunk_slots);
482 rte_kvargs_process(kvlist, OTX2_TIM_STATS_ENA, &parse_kvargs_flag,
487 otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)
489 struct rsrc_attach_req *atch_req;
490 struct rsrc_detach_req *dtch_req;
491 struct free_rsrcs_rsp *rsrc_cnt;
492 const struct rte_memzone *mz;
493 struct otx2_tim_evdev *dev;
496 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
499 mz = rte_memzone_reserve(RTE_STR(OTX2_TIM_EVDEV_NAME),
500 sizeof(struct otx2_tim_evdev),
503 otx2_tim_dbg("Unable to allocate memory for TIM Event device");
508 dev->pci_dev = pci_dev;
509 dev->mbox = cmn_dev->mbox;
510 dev->bar2 = cmn_dev->bar2;
512 tim_parse_devargs(pci_dev->device.devargs, dev);
514 otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
515 rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
517 otx2_err("Unable to get free rsrc count.");
521 dev->nb_rings = rsrc_cnt->tim;
523 if (!dev->nb_rings) {
524 otx2_tim_dbg("No TIM Logical functions provisioned.");
528 atch_req = otx2_mbox_alloc_msg_attach_resources(dev->mbox);
529 atch_req->modify = true;
530 atch_req->timlfs = dev->nb_rings;
532 rc = otx2_mbox_process(dev->mbox);
534 otx2_err("Unable to attach TIM rings.");
538 rc = tim_get_msix_offsets();
540 otx2_err("Unable to get MSIX offsets for TIM.");
544 if (dev->chunk_slots &&
545 dev->chunk_slots <= OTX2_TIM_MAX_CHUNK_SLOTS &&
546 dev->chunk_slots >= OTX2_TIM_MIN_CHUNK_SLOTS) {
547 dev->chunk_sz = (dev->chunk_slots + 1) *
548 OTX2_TIM_CHUNK_ALIGNMENT;
550 dev->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ;
556 dtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);
557 dtch_req->partial = true;
558 dtch_req->timlfs = true;
560 otx2_mbox_process(dev->mbox);
562 rte_memzone_free(mz);
568 struct otx2_tim_evdev *dev = tim_priv_get();
569 struct rsrc_detach_req *dtch_req;
571 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
574 dtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);
575 dtch_req->partial = true;
576 dtch_req->timlfs = true;
578 otx2_mbox_process(dev->mbox);
579 rte_memzone_free(rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME)));