drivers/event/octeontx2/otx2_tim_evdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2019 Marvell International Ltd.
   3  */
   4
   5 #ifndef __OTX2_TIM_EVDEV_H__
   6 #define __OTX2_TIM_EVDEV_H__
   7
   8 #include <rte_event_timer_adapter.h>
   9 #include <rte_event_timer_adapter_pmd.h>
  10
  11 #include "otx2_dev.h"
  12
  13 #define OTX2_TIM_EVDEV_NAME otx2_tim_eventdev
  14
  15 #define otx2_tim_func_trace otx2_tim_dbg
  16
  17 #define TIM_LF_RING_AURA                (0x0)
  18 #define TIM_LF_RING_BASE                (0x130)
  19 #define TIM_LF_NRSPERR_INT              (0x200)
  20 #define TIM_LF_NRSPERR_INT_W1S          (0x208)
  21 #define TIM_LF_NRSPERR_INT_ENA_W1S      (0x210)
  22 #define TIM_LF_NRSPERR_INT_ENA_W1C      (0x218)
  23 #define TIM_LF_RAS_INT                  (0x300)
  24 #define TIM_LF_RAS_INT_W1S              (0x308)
  25 #define TIM_LF_RAS_INT_ENA_W1S          (0x310)
  26 #define TIM_LF_RAS_INT_ENA_W1C          (0x318)
  27
  28 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48)
  29 #define TIM_BUCKET_W1_M_CHUNK_REMAINDER ((1ULL << (64 - \
  30                                          TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1)
  31 #define TIM_BUCKET_W1_S_LOCK            (40)
  32 #define TIM_BUCKET_W1_M_LOCK            ((1ULL <<       \
  33                                          (TIM_BUCKET_W1_S_CHUNK_REMAINDER - \
  34                                           TIM_BUCKET_W1_S_LOCK)) - 1)
  35 #define TIM_BUCKET_W1_S_RSVD            (35)
  36 #define TIM_BUCKET_W1_S_BSK             (34)
  37 #define TIM_BUCKET_W1_M_BSK             ((1ULL <<       \
  38                                          (TIM_BUCKET_W1_S_RSVD -            \
  39                                           TIM_BUCKET_W1_S_BSK)) - 1)
  40 #define TIM_BUCKET_W1_S_HBT             (33)
  41 #define TIM_BUCKET_W1_M_HBT             ((1ULL <<       \
  42                                          (TIM_BUCKET_W1_S_BSK -             \
  43                                           TIM_BUCKET_W1_S_HBT)) - 1)
  44 #define TIM_BUCKET_W1_S_SBT             (32)
  45 #define TIM_BUCKET_W1_M_SBT             ((1ULL <<       \
  46                                          (TIM_BUCKET_W1_S_HBT -             \
  47                                           TIM_BUCKET_W1_S_SBT)) - 1)
  48 #define TIM_BUCKET_W1_S_NUM_ENTRIES     (0)
  49 #define TIM_BUCKET_W1_M_NUM_ENTRIES     ((1ULL <<       \
  50                                          (TIM_BUCKET_W1_S_SBT -             \
  51                                           TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1)
  52
  53 #define TIM_BUCKET_SEMA                 (TIM_BUCKET_CHUNK_REMAIN)
  54
  55 #define TIM_BUCKET_CHUNK_REMAIN \
  56         (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)
  57
  58 #define TIM_BUCKET_LOCK \
  59         (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)
  60
  61 #define TIM_BUCKET_SEMA_WLOCK \
  62         (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))
  63
  64 #define OTX2_MAX_TIM_RINGS              (256)
  65 #define OTX2_TIM_MAX_BUCKETS            (0xFFFFF)
  66 #define OTX2_TIM_RING_DEF_CHUNK_SZ      (4096)
  67 #define OTX2_TIM_CHUNK_ALIGNMENT        (16)
  68 #define OTX2_TIM_NB_CHUNK_SLOTS(sz)     (((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)
  69 #define OTX2_TIM_MIN_CHUNK_SLOTS        (0x1)
  70 #define OTX2_TIM_MAX_CHUNK_SLOTS        (0x1FFE)
  71 #define OTX2_TIM_MIN_TMO_TKS            (256)
  72
  73 enum otx2_tim_clk_src {
  74         OTX2_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
  75         OTX2_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
  76         OTX2_TIM_CLK_SRC_GTI  = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
  77         OTX2_TIM_CLK_SRC_PTP  = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
  78 };
  79
  80 struct otx2_tim_bkt {
  81         uint64_t first_chunk;
  82         union {
  83                 uint64_t w1;
  84                 struct {
  85                         uint32_t nb_entry;
  86                         uint8_t sbt:1;
  87                         uint8_t hbt:1;
  88                         uint8_t bsk:1;
  89                         uint8_t rsvd:5;
  90                         uint8_t lock;
  91                         int16_t chunk_remainder;
  92                 };
  93         };
  94         uint64_t current_chunk;
  95         uint64_t pad;
  96 } __rte_packed __rte_aligned(32);
  97
  98 struct otx2_tim_evdev {
  99         struct rte_pci_device *pci_dev;
 100         struct rte_eventdev *event_dev;
 101         struct otx2_mbox *mbox;
 102         uint16_t nb_rings;
 103         uint32_t chunk_sz;
 104         uintptr_t bar2;
 105         /* Dev args */
 106         uint8_t disable_npa;
 107         uint16_t chunk_slots;
 108         /* MSIX offsets */
 109         uint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];
 110 };
 111
 112 struct otx2_tim_ring {
 113         uintptr_t base;
 114         uint16_t nb_chunk_slots;
 115         uint32_t nb_bkts;
 116         struct otx2_tim_bkt *bkt;
 117         struct rte_mempool *chunk_pool;
 118         uint64_t tck_int;
 119         uint8_t prod_type_sp;
 120         uint8_t disable_npa;
 121         uint8_t optimized;
 122         uint8_t ena_dfb;
 123         uint16_t ring_id;
 124         uint32_t aura;
 125         uint64_t tck_nsec;
 126         uint64_t max_tout;
 127         uint64_t nb_chunks;
 128         uint64_t chunk_sz;
 129         uint64_t tenns_clk_freq;
 130         enum otx2_tim_clk_src clk_src;
 131 } __rte_cache_aligned;
 132
 133 static inline struct otx2_tim_evdev *
 134 tim_priv_get(void)
 135 {
 136         const struct rte_memzone *mz;
 137
 138         mz = rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME));
 139         if (mz == NULL)
 140                 return NULL;
 141
 142         return mz->addr;
 143 }
 144
 145 int otx2_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
 146                       uint32_t *caps,
 147                       const struct rte_event_timer_adapter_ops **ops);
 148
 149 void otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev);
 150 void otx2_tim_fini(void);
 151
 152 /* TIM IRQ */
 153 int tim_register_irq(uint16_t ring_id);
 154 void tim_unregister_irq(uint16_t ring_id);
 155
 156 #endif /* __OTX2_TIM_EVDEV_H__ */