1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016-2017 Intel Corporation
8 #include <rte_bus_vdev.h>
9 #include <rte_kvargs.h>
11 #include <rte_errno.h>
12 #include <rte_event_ring.h>
13 #include <rte_service_component.h>
18 #define EVENTDEV_NAME_SW_PMD event_sw
19 #define NUMA_NODE_ARG "numa_node"
20 #define SCHED_QUANTA_ARG "sched_quanta"
21 #define CREDIT_QUANTA_ARG "credit_quanta"
24 sw_info_get(struct rte_eventdev *dev, struct rte_event_dev_info *info);
27 sw_port_link(struct rte_eventdev *dev, void *port, const uint8_t queues[],
28 const uint8_t priorities[], uint16_t num)
30 struct sw_port *p = port;
31 struct sw_evdev *sw = sw_pmd_priv(dev);
34 RTE_SET_USED(priorities);
35 for (i = 0; i < num; i++) {
36 struct sw_qid *q = &sw->qids[queues[i]];
39 /* check for qid map overflow */
40 if (q->cq_num_mapped_cqs >= RTE_DIM(q->cq_map)) {
45 if (p->is_directed && p->num_qids_mapped > 0) {
50 for (j = 0; j < q->cq_num_mapped_cqs; j++) {
51 if (q->cq_map[j] == p->id)
55 /* check if port is already linked */
56 if (j < q->cq_num_mapped_cqs)
59 if (q->type == SW_SCHED_TYPE_DIRECT) {
60 /* check directed qids only map to one port */
61 if (p->num_qids_mapped > 0) {
65 /* check port only takes a directed flow */
72 p->num_qids_mapped = 1;
73 } else if (q->type == RTE_SCHED_TYPE_ORDERED) {
74 p->num_ordered_qids++;
76 } else if (q->type == RTE_SCHED_TYPE_ATOMIC ||
77 q->type == RTE_SCHED_TYPE_PARALLEL) {
81 q->cq_map[q->cq_num_mapped_cqs] = p->id;
83 q->cq_num_mapped_cqs++;
89 sw_port_unlink(struct rte_eventdev *dev, void *port, uint8_t queues[],
92 struct sw_port *p = port;
93 struct sw_evdev *sw = sw_pmd_priv(dev);
97 for (i = 0; i < nb_unlinks; i++) {
98 struct sw_qid *q = &sw->qids[queues[i]];
99 for (j = 0; j < q->cq_num_mapped_cqs; j++) {
100 if (q->cq_map[j] == p->id) {
102 q->cq_map[q->cq_num_mapped_cqs - 1];
104 q->cq_num_mapped_cqs--;
107 p->num_qids_mapped--;
109 if (q->type == RTE_SCHED_TYPE_ORDERED)
110 p->num_ordered_qids--;
117 p->unlinks_in_progress += unlinked;
124 sw_port_unlinks_in_progress(struct rte_eventdev *dev, void *port)
127 struct sw_port *p = port;
128 return p->unlinks_in_progress;
132 sw_port_setup(struct rte_eventdev *dev, uint8_t port_id,
133 const struct rte_event_port_conf *conf)
135 struct sw_evdev *sw = sw_pmd_priv(dev);
136 struct sw_port *p = &sw->ports[port_id];
137 char buf[RTE_RING_NAMESIZE];
140 struct rte_event_dev_info info;
141 sw_info_get(dev, &info);
143 /* detect re-configuring and return credits to instance if needed */
144 if (p->initialized) {
145 /* taking credits from pool is done one quanta at a time, and
146 * credits may be spend (counted in p->inflights) or still
147 * available in the port (p->inflight_credits). We must return
148 * the sum to no leak credits
150 int possible_inflights = p->inflight_credits + p->inflights;
151 rte_atomic32_sub(&sw->inflights, possible_inflights);
154 *p = (struct sw_port){0}; /* zero entire structure */
158 /* check to see if rings exists - port_setup() can be called multiple
159 * times legally (assuming device is stopped). If ring exists, free it
160 * to so it gets re-created with the correct size
162 snprintf(buf, sizeof(buf), "sw%d_p%u_%s", dev->data->dev_id,
163 port_id, "rx_worker_ring");
164 struct rte_event_ring *existing_ring = rte_event_ring_lookup(buf);
166 rte_event_ring_free(existing_ring);
168 p->rx_worker_ring = rte_event_ring_create(buf, MAX_SW_PROD_Q_DEPTH,
169 dev->data->socket_id,
170 RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ);
171 if (p->rx_worker_ring == NULL) {
172 SW_LOG_ERR("Error creating RX worker ring for port %d\n",
177 p->inflight_max = conf->new_event_threshold;
178 p->implicit_release = !conf->disable_implicit_release;
180 /* check if ring exists, same as rx_worker above */
181 snprintf(buf, sizeof(buf), "sw%d_p%u, %s", dev->data->dev_id,
182 port_id, "cq_worker_ring");
183 existing_ring = rte_event_ring_lookup(buf);
185 rte_event_ring_free(existing_ring);
187 p->cq_worker_ring = rte_event_ring_create(buf, conf->dequeue_depth,
188 dev->data->socket_id,
189 RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ);
190 if (p->cq_worker_ring == NULL) {
191 rte_event_ring_free(p->rx_worker_ring);
192 SW_LOG_ERR("Error creating CQ worker ring for port %d\n",
196 sw->cq_ring_space[port_id] = conf->dequeue_depth;
198 /* set hist list contents to empty */
199 for (i = 0; i < SW_PORT_HIST_LIST; i++) {
200 p->hist_list[i].fid = -1;
201 p->hist_list[i].qid = -1;
203 dev->data->ports[port_id] = p;
211 sw_port_release(void *port)
213 struct sw_port *p = (void *)port;
217 rte_event_ring_free(p->rx_worker_ring);
218 rte_event_ring_free(p->cq_worker_ring);
219 memset(p, 0, sizeof(*p));
223 qid_init(struct sw_evdev *sw, unsigned int idx, int type,
224 const struct rte_event_queue_conf *queue_conf)
227 int dev_id = sw->data->dev_id;
228 int socket_id = sw->data->socket_id;
229 char buf[IQ_ROB_NAMESIZE];
230 struct sw_qid *qid = &sw->qids[idx];
232 /* Initialize the FID structures to no pinning (-1), and zero packets */
233 const struct sw_fid_t fid = {.cq = -1, .pcount = 0};
234 for (i = 0; i < RTE_DIM(qid->fids); i++)
239 qid->priority = queue_conf->priority;
241 if (qid->type == RTE_SCHED_TYPE_ORDERED) {
242 char ring_name[RTE_RING_NAMESIZE];
243 uint32_t window_size;
245 /* rte_ring and window_size_mask require require window_size to
248 window_size = rte_align32pow2(
249 queue_conf->nb_atomic_order_sequences);
251 qid->window_size = window_size - 1;
255 "invalid reorder_window_size for ordered queue\n"
260 snprintf(buf, sizeof(buf), "sw%d_iq_%d_rob", dev_id, i);
261 qid->reorder_buffer = rte_zmalloc_socket(buf,
262 window_size * sizeof(qid->reorder_buffer[0]),
264 if (!qid->reorder_buffer) {
265 SW_LOG_DBG("reorder_buffer malloc failed\n");
269 memset(&qid->reorder_buffer[0],
271 window_size * sizeof(qid->reorder_buffer[0]));
273 snprintf(ring_name, sizeof(ring_name), "sw%d_q%d_freelist",
276 /* lookup the ring, and if it already exists, free it */
277 struct rte_ring *cleanup = rte_ring_lookup(ring_name);
279 rte_ring_free(cleanup);
281 qid->reorder_buffer_freelist = rte_ring_create(ring_name,
284 RING_F_SP_ENQ | RING_F_SC_DEQ);
285 if (!qid->reorder_buffer_freelist) {
286 SW_LOG_DBG("freelist ring create failed");
290 /* Populate the freelist with reorder buffer entries. Enqueue
291 * 'window_size - 1' entries because the rte_ring holds only
294 for (i = 0; i < window_size - 1; i++) {
295 if (rte_ring_sp_enqueue(qid->reorder_buffer_freelist,
296 &qid->reorder_buffer[i]) < 0)
300 qid->reorder_buffer_index = 0;
304 qid->initialized = 1;
309 if (qid->reorder_buffer) {
310 rte_free(qid->reorder_buffer);
311 qid->reorder_buffer = NULL;
314 if (qid->reorder_buffer_freelist) {
315 rte_ring_free(qid->reorder_buffer_freelist);
316 qid->reorder_buffer_freelist = NULL;
323 sw_queue_release(struct rte_eventdev *dev, uint8_t id)
325 struct sw_evdev *sw = sw_pmd_priv(dev);
326 struct sw_qid *qid = &sw->qids[id];
328 if (qid->type == RTE_SCHED_TYPE_ORDERED) {
329 rte_free(qid->reorder_buffer);
330 rte_ring_free(qid->reorder_buffer_freelist);
332 memset(qid, 0, sizeof(*qid));
336 sw_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
337 const struct rte_event_queue_conf *conf)
341 type = conf->schedule_type;
343 if (RTE_EVENT_QUEUE_CFG_SINGLE_LINK & conf->event_queue_cfg) {
344 type = SW_SCHED_TYPE_DIRECT;
345 } else if (RTE_EVENT_QUEUE_CFG_ALL_TYPES
346 & conf->event_queue_cfg) {
347 SW_LOG_ERR("QUEUE_CFG_ALL_TYPES not supported\n");
351 struct sw_evdev *sw = sw_pmd_priv(dev);
353 if (sw->qids[queue_id].initialized)
354 sw_queue_release(dev, queue_id);
356 return qid_init(sw, queue_id, type, conf);
360 sw_init_qid_iqs(struct sw_evdev *sw)
364 /* Initialize the IQ memory of all configured qids */
365 for (i = 0; i < RTE_EVENT_MAX_QUEUES_PER_DEV; i++) {
366 struct sw_qid *qid = &sw->qids[i];
368 if (!qid->initialized)
371 for (j = 0; j < SW_IQS_MAX; j++)
372 iq_init(sw, &qid->iq[j]);
377 sw_qids_empty(struct sw_evdev *sw)
381 for (i = 0; i < sw->qid_count; i++) {
382 for (j = 0; j < SW_IQS_MAX; j++) {
383 if (iq_count(&sw->qids[i].iq[j]))
392 sw_ports_empty(struct sw_evdev *sw)
396 for (i = 0; i < sw->port_count; i++) {
397 if ((rte_event_ring_count(sw->ports[i].rx_worker_ring)) ||
398 rte_event_ring_count(sw->ports[i].cq_worker_ring))
406 sw_drain_ports(struct rte_eventdev *dev)
408 struct sw_evdev *sw = sw_pmd_priv(dev);
409 eventdev_stop_flush_t flush;
414 flush = dev->dev_ops->dev_stop_flush;
415 dev_id = dev->data->dev_id;
416 arg = dev->data->dev_stop_flush_arg;
418 for (i = 0; i < sw->port_count; i++) {
421 while (rte_event_dequeue_burst(dev_id, i, &ev, 1, 0)) {
423 flush(dev_id, ev, arg);
425 ev.op = RTE_EVENT_OP_RELEASE;
426 rte_event_enqueue_burst(dev_id, i, &ev, 1);
432 sw_drain_queue(struct rte_eventdev *dev, struct sw_iq *iq)
434 struct sw_evdev *sw = sw_pmd_priv(dev);
435 eventdev_stop_flush_t flush;
439 flush = dev->dev_ops->dev_stop_flush;
440 dev_id = dev->data->dev_id;
441 arg = dev->data->dev_stop_flush_arg;
443 while (iq_count(iq) > 0) {
446 iq_dequeue_burst(sw, iq, &ev, 1);
449 flush(dev_id, ev, arg);
454 sw_drain_queues(struct rte_eventdev *dev)
456 struct sw_evdev *sw = sw_pmd_priv(dev);
459 for (i = 0; i < sw->qid_count; i++) {
460 for (j = 0; j < SW_IQS_MAX; j++)
461 sw_drain_queue(dev, &sw->qids[i].iq[j]);
466 sw_clean_qid_iqs(struct rte_eventdev *dev)
468 struct sw_evdev *sw = sw_pmd_priv(dev);
471 /* Release the IQ memory of all configured qids */
472 for (i = 0; i < RTE_EVENT_MAX_QUEUES_PER_DEV; i++) {
473 struct sw_qid *qid = &sw->qids[i];
475 for (j = 0; j < SW_IQS_MAX; j++) {
476 if (!qid->iq[j].head)
478 iq_free_chunk_list(sw, qid->iq[j].head);
479 qid->iq[j].head = NULL;
485 sw_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
486 struct rte_event_queue_conf *conf)
489 RTE_SET_USED(queue_id);
491 static const struct rte_event_queue_conf default_conf = {
492 .nb_atomic_flows = 4096,
493 .nb_atomic_order_sequences = 1,
494 .schedule_type = RTE_SCHED_TYPE_ATOMIC,
495 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
498 *conf = default_conf;
502 sw_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
503 struct rte_event_port_conf *port_conf)
506 RTE_SET_USED(port_id);
508 port_conf->new_event_threshold = 1024;
509 port_conf->dequeue_depth = 16;
510 port_conf->enqueue_depth = 16;
511 port_conf->disable_implicit_release = 0;
515 sw_dev_configure(const struct rte_eventdev *dev)
517 struct sw_evdev *sw = sw_pmd_priv(dev);
518 const struct rte_eventdev_data *data = dev->data;
519 const struct rte_event_dev_config *conf = &data->dev_conf;
522 sw->qid_count = conf->nb_event_queues;
523 sw->port_count = conf->nb_event_ports;
524 sw->nb_events_limit = conf->nb_events_limit;
525 rte_atomic32_set(&sw->inflights, 0);
527 /* Number of chunks sized for worst-case spread of events across IQs */
528 num_chunks = ((SW_INFLIGHT_EVENTS_TOTAL/SW_EVS_PER_Q_CHUNK)+1) +
529 sw->qid_count*SW_IQS_MAX*2;
531 /* If this is a reconfiguration, free the previous IQ allocation. All
532 * IQ chunk references were cleaned out of the QIDs in sw_stop(), and
533 * will be reinitialized in sw_start().
536 rte_free(sw->chunks);
538 sw->chunks = rte_malloc_socket(NULL,
539 sizeof(struct sw_queue_chunk) *
542 sw->data->socket_id);
546 sw->chunk_list_head = NULL;
547 for (i = 0; i < num_chunks; i++)
548 iq_free_chunk(sw, &sw->chunks[i]);
550 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
559 sw_eth_rx_adapter_caps_get(const struct rte_eventdev *dev,
560 const struct rte_eth_dev *eth_dev,
564 RTE_SET_USED(eth_dev);
565 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
570 sw_timer_adapter_caps_get(const struct rte_eventdev *dev,
573 const struct rte_event_timer_adapter_ops **ops)
579 /* Use default SW ops */
586 sw_crypto_adapter_caps_get(const struct rte_eventdev *dev,
587 const struct rte_cryptodev *cdev,
592 *caps = RTE_EVENT_CRYPTO_ADAPTER_SW_CAP;
597 sw_info_get(struct rte_eventdev *dev, struct rte_event_dev_info *info)
601 static const struct rte_event_dev_info evdev_sw_info = {
602 .driver_name = SW_PMD_NAME,
603 .max_event_queues = RTE_EVENT_MAX_QUEUES_PER_DEV,
604 .max_event_queue_flows = SW_QID_NUM_FIDS,
605 .max_event_queue_priority_levels = SW_Q_PRIORITY_MAX,
606 .max_event_priority_levels = SW_IQS_MAX,
607 .max_event_ports = SW_PORTS_MAX,
608 .max_event_port_dequeue_depth = MAX_SW_CONS_Q_DEPTH,
609 .max_event_port_enqueue_depth = MAX_SW_PROD_Q_DEPTH,
610 .max_num_events = SW_INFLIGHT_EVENTS_TOTAL,
612 RTE_EVENT_DEV_CAP_QUEUE_QOS |
613 RTE_EVENT_DEV_CAP_BURST_MODE |
614 RTE_EVENT_DEV_CAP_EVENT_QOS |
615 RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE|
616 RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
617 RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
618 RTE_EVENT_DEV_CAP_NONSEQ_MODE),
621 *info = evdev_sw_info;
625 sw_dump(struct rte_eventdev *dev, FILE *f)
627 const struct sw_evdev *sw = sw_pmd_priv(dev);
629 static const char * const q_type_strings[] = {
630 "Ordered", "Atomic", "Parallel", "Directed"
633 fprintf(f, "EventDev %s: ports %d, qids %d\n", "todo-fix-name",
634 sw->port_count, sw->qid_count);
636 fprintf(f, "\trx %"PRIu64"\n\tdrop %"PRIu64"\n\ttx %"PRIu64"\n",
637 sw->stats.rx_pkts, sw->stats.rx_dropped, sw->stats.tx_pkts);
638 fprintf(f, "\tsched calls: %"PRIu64"\n", sw->sched_called);
639 fprintf(f, "\tsched cq/qid call: %"PRIu64"\n", sw->sched_cq_qid_called);
640 fprintf(f, "\tsched no IQ enq: %"PRIu64"\n", sw->sched_no_iq_enqueues);
641 fprintf(f, "\tsched no CQ enq: %"PRIu64"\n", sw->sched_no_cq_enqueues);
642 uint32_t inflights = rte_atomic32_read(&sw->inflights);
643 uint32_t credits = sw->nb_events_limit - inflights;
644 fprintf(f, "\tinflight %d, credits: %d\n", inflights, credits);
646 #define COL_RED "\x1b[31m"
647 #define COL_RESET "\x1b[0m"
649 for (i = 0; i < sw->port_count; i++) {
651 const struct sw_port *p = &sw->ports[i];
652 if (!p->initialized) {
653 fprintf(f, " %sPort %d not initialized.%s\n",
654 COL_RED, i, COL_RESET);
657 fprintf(f, " Port %d %s\n", i,
658 p->is_directed ? " (SingleCons)" : "");
659 fprintf(f, "\trx %"PRIu64"\tdrop %"PRIu64"\ttx %"PRIu64
660 "\t%sinflight %d%s\n", sw->ports[i].stats.rx_pkts,
661 sw->ports[i].stats.rx_dropped,
662 sw->ports[i].stats.tx_pkts,
663 (p->inflights == p->inflight_max) ?
665 sw->ports[i].inflights, COL_RESET);
667 fprintf(f, "\tMax New: %u"
668 "\tAvg cycles PP: %"PRIu64"\tCredits: %u\n",
669 sw->ports[i].inflight_max,
670 sw->ports[i].avg_pkt_ticks,
671 sw->ports[i].inflight_credits);
672 fprintf(f, "\tReceive burst distribution:\n");
673 float zp_percent = p->zero_polls * 100.0 / p->total_polls;
674 fprintf(f, zp_percent < 10 ? "\t\t0:%.02f%% " : "\t\t0:%.0f%% ",
676 for (max = (int)RTE_DIM(p->poll_buckets); max-- > 0;)
677 if (p->poll_buckets[max] != 0)
679 for (j = 0; j <= max; j++) {
680 if (p->poll_buckets[j] != 0) {
681 float poll_pc = p->poll_buckets[j] * 100.0 /
683 fprintf(f, "%u-%u:%.02f%% ",
684 ((j << SW_DEQ_STAT_BUCKET_SHIFT) + 1),
685 ((j+1) << SW_DEQ_STAT_BUCKET_SHIFT),
691 if (p->rx_worker_ring) {
692 uint64_t used = rte_event_ring_count(p->rx_worker_ring);
693 uint64_t space = rte_event_ring_free_count(
695 const char *col = (space == 0) ? COL_RED : COL_RESET;
696 fprintf(f, "\t%srx ring used: %4"PRIu64"\tfree: %4"
697 PRIu64 COL_RESET"\n", col, used, space);
699 fprintf(f, "\trx ring not initialized.\n");
701 if (p->cq_worker_ring) {
702 uint64_t used = rte_event_ring_count(p->cq_worker_ring);
703 uint64_t space = rte_event_ring_free_count(
705 const char *col = (space == 0) ? COL_RED : COL_RESET;
706 fprintf(f, "\t%scq ring used: %4"PRIu64"\tfree: %4"
707 PRIu64 COL_RESET"\n", col, used, space);
709 fprintf(f, "\tcq ring not initialized.\n");
712 for (i = 0; i < sw->qid_count; i++) {
713 const struct sw_qid *qid = &sw->qids[i];
714 if (!qid->initialized) {
715 fprintf(f, " %sQueue %d not initialized.%s\n",
716 COL_RED, i, COL_RESET);
719 int affinities_per_port[SW_PORTS_MAX] = {0};
720 uint32_t inflights = 0;
722 fprintf(f, " Queue %d (%s)\n", i, q_type_strings[qid->type]);
723 fprintf(f, "\trx %"PRIu64"\tdrop %"PRIu64"\ttx %"PRIu64"\n",
724 qid->stats.rx_pkts, qid->stats.rx_dropped,
726 if (qid->type == RTE_SCHED_TYPE_ORDERED) {
727 struct rte_ring *rob_buf_free =
728 qid->reorder_buffer_freelist;
730 fprintf(f, "\tReorder entries in use: %u\n",
731 rte_ring_free_count(rob_buf_free));
734 "\tReorder buffer not initialized\n");
738 for (flow = 0; flow < RTE_DIM(qid->fids); flow++)
739 if (qid->fids[flow].cq != -1) {
740 affinities_per_port[qid->fids[flow].cq]++;
741 inflights += qid->fids[flow].pcount;
745 fprintf(f, "\tPer Port Stats:\n");
746 for (port = 0; port < sw->port_count; port++) {
747 fprintf(f, "\t Port %d: Pkts: %"PRIu64, port,
749 fprintf(f, "\tFlows: %d\n", affinities_per_port[port]);
753 uint32_t iq_printed = 0;
754 for (iq = 0; iq < SW_IQS_MAX; iq++) {
755 if (!qid->iq[iq].head) {
756 fprintf(f, "\tiq %d is not initialized.\n", iq);
760 uint32_t used = iq_count(&qid->iq[iq]);
761 const char *col = COL_RESET;
763 fprintf(f, "\t%siq %d: Used %d"
764 COL_RESET"\n", col, iq, used);
769 fprintf(f, "\t-- iqs empty --\n");
774 sw_start(struct rte_eventdev *dev)
777 struct sw_evdev *sw = sw_pmd_priv(dev);
779 rte_service_component_runstate_set(sw->service_id, 1);
781 /* check a service core is mapped to this service */
782 if (!rte_service_runstate_get(sw->service_id)) {
783 SW_LOG_ERR("Warning: No Service core enabled on service %s\n",
788 /* check all ports are set up */
789 for (i = 0; i < sw->port_count; i++)
790 if (sw->ports[i].rx_worker_ring == NULL) {
791 SW_LOG_ERR("Port %d not configured\n", i);
795 /* check all queues are configured and mapped to ports*/
796 for (i = 0; i < sw->qid_count; i++)
797 if (!sw->qids[i].initialized ||
798 sw->qids[i].cq_num_mapped_cqs == 0) {
799 SW_LOG_ERR("Queue %d not configured\n", i);
803 /* build up our prioritized array of qids */
804 /* We don't use qsort here, as if all/multiple entries have the same
805 * priority, the result is non-deterministic. From "man 3 qsort":
806 * "If two members compare as equal, their order in the sorted
807 * array is undefined."
810 for (j = 0; j <= RTE_EVENT_DEV_PRIORITY_LOWEST; j++) {
811 for (i = 0; i < sw->qid_count; i++) {
812 if (sw->qids[i].priority == j) {
813 sw->qids_prioritized[qidx] = &sw->qids[i];
821 if (sw_xstats_init(sw) < 0)
831 sw_stop(struct rte_eventdev *dev)
833 struct sw_evdev *sw = sw_pmd_priv(dev);
836 /* Stop the scheduler if it's running */
837 runstate = rte_service_runstate_get(sw->service_id);
839 rte_service_runstate_set(sw->service_id, 0);
841 while (rte_service_may_be_active(sw->service_id))
844 /* Flush all events out of the device */
845 while (!(sw_qids_empty(sw) && sw_ports_empty(sw))) {
846 sw_event_schedule(dev);
848 sw_drain_queues(dev);
851 sw_clean_qid_iqs(dev);
852 sw_xstats_uninit(sw);
857 rte_service_runstate_set(sw->service_id, 1);
861 sw_close(struct rte_eventdev *dev)
863 struct sw_evdev *sw = sw_pmd_priv(dev);
866 for (i = 0; i < sw->qid_count; i++)
867 sw_queue_release(dev, i);
870 for (i = 0; i < sw->port_count; i++)
871 sw_port_release(&sw->ports[i]);
874 memset(&sw->stats, 0, sizeof(sw->stats));
875 sw->sched_called = 0;
876 sw->sched_no_iq_enqueues = 0;
877 sw->sched_no_cq_enqueues = 0;
878 sw->sched_cq_qid_called = 0;
884 assign_numa_node(const char *key __rte_unused, const char *value, void *opaque)
886 int *socket_id = opaque;
887 *socket_id = atoi(value);
888 if (*socket_id >= RTE_MAX_NUMA_NODES)
894 set_sched_quanta(const char *key __rte_unused, const char *value, void *opaque)
896 int *quanta = opaque;
897 *quanta = atoi(value);
898 if (*quanta < 0 || *quanta >= 4096)
904 set_credit_quanta(const char *key __rte_unused, const char *value, void *opaque)
906 int *credit = opaque;
907 *credit = atoi(value);
908 if (*credit < 0 || *credit >= 128)
914 static int32_t sw_sched_service_func(void *args)
916 struct rte_eventdev *dev = args;
917 sw_event_schedule(dev);
922 sw_probe(struct rte_vdev_device *vdev)
924 static struct rte_eventdev_ops evdev_sw_ops = {
925 .dev_configure = sw_dev_configure,
926 .dev_infos_get = sw_info_get,
927 .dev_close = sw_close,
928 .dev_start = sw_start,
932 .queue_def_conf = sw_queue_def_conf,
933 .queue_setup = sw_queue_setup,
934 .queue_release = sw_queue_release,
935 .port_def_conf = sw_port_def_conf,
936 .port_setup = sw_port_setup,
937 .port_release = sw_port_release,
938 .port_link = sw_port_link,
939 .port_unlink = sw_port_unlink,
940 .port_unlinks_in_progress = sw_port_unlinks_in_progress,
942 .eth_rx_adapter_caps_get = sw_eth_rx_adapter_caps_get,
944 .timer_adapter_caps_get = sw_timer_adapter_caps_get,
946 .crypto_adapter_caps_get = sw_crypto_adapter_caps_get,
948 .xstats_get = sw_xstats_get,
949 .xstats_get_names = sw_xstats_get_names,
950 .xstats_get_by_name = sw_xstats_get_by_name,
951 .xstats_reset = sw_xstats_reset,
953 .dev_selftest = test_sw_eventdev,
956 static const char *const args[] = {
964 struct rte_eventdev *dev;
966 int socket_id = rte_socket_id();
967 int sched_quanta = SW_DEFAULT_SCHED_QUANTA;
968 int credit_quanta = SW_DEFAULT_CREDIT_QUANTA;
970 name = rte_vdev_device_name(vdev);
971 params = rte_vdev_device_args(vdev);
972 if (params != NULL && params[0] != '\0') {
973 struct rte_kvargs *kvlist = rte_kvargs_parse(params, args);
977 "Ignoring unsupported parameters when creating device '%s'\n",
980 int ret = rte_kvargs_process(kvlist, NUMA_NODE_ARG,
981 assign_numa_node, &socket_id);
984 "%s: Error parsing numa node parameter",
986 rte_kvargs_free(kvlist);
990 ret = rte_kvargs_process(kvlist, SCHED_QUANTA_ARG,
991 set_sched_quanta, &sched_quanta);
994 "%s: Error parsing sched quanta parameter",
996 rte_kvargs_free(kvlist);
1000 ret = rte_kvargs_process(kvlist, CREDIT_QUANTA_ARG,
1001 set_credit_quanta, &credit_quanta);
1004 "%s: Error parsing credit quanta parameter",
1006 rte_kvargs_free(kvlist);
1010 rte_kvargs_free(kvlist);
1015 "Creating eventdev sw device %s, numa_node=%d, sched_quanta=%d, credit_quanta=%d\n",
1016 name, socket_id, sched_quanta, credit_quanta);
1018 dev = rte_event_pmd_vdev_init(name,
1019 sizeof(struct sw_evdev), socket_id);
1021 SW_LOG_ERR("eventdev vdev init() failed");
1024 dev->dev_ops = &evdev_sw_ops;
1025 dev->enqueue = sw_event_enqueue;
1026 dev->enqueue_burst = sw_event_enqueue_burst;
1027 dev->enqueue_new_burst = sw_event_enqueue_burst;
1028 dev->enqueue_forward_burst = sw_event_enqueue_burst;
1029 dev->dequeue = sw_event_dequeue;
1030 dev->dequeue_burst = sw_event_dequeue_burst;
1032 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1035 sw = dev->data->dev_private;
1036 sw->data = dev->data;
1038 /* copy values passed from vdev command line to instance */
1039 sw->credit_update_quanta = credit_quanta;
1040 sw->sched_quanta = sched_quanta;
1042 /* register service with EAL */
1043 struct rte_service_spec service;
1044 memset(&service, 0, sizeof(struct rte_service_spec));
1045 snprintf(service.name, sizeof(service.name), "%s_service", name);
1046 snprintf(sw->service_name, sizeof(sw->service_name), "%s_service",
1048 service.socket_id = socket_id;
1049 service.callback = sw_sched_service_func;
1050 service.callback_userdata = (void *)dev;
1052 int32_t ret = rte_service_component_register(&service, &sw->service_id);
1054 SW_LOG_ERR("service register() failed");
1058 dev->data->service_inited = 1;
1059 dev->data->service_id = sw->service_id;
1065 sw_remove(struct rte_vdev_device *vdev)
1069 name = rte_vdev_device_name(vdev);
1073 SW_LOG_INFO("Closing eventdev sw device %s\n", name);
1075 return rte_event_pmd_vdev_uninit(name);
1078 static struct rte_vdev_driver evdev_sw_pmd_drv = {
1083 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_SW_PMD, evdev_sw_pmd_drv);
1084 RTE_PMD_REGISTER_PARAM_STRING(event_sw, NUMA_NODE_ARG "=<int> "
1085 SCHED_QUANTA_ARG "=<int>" CREDIT_QUANTA_ARG "=<int>");
1087 /* declared extern in header, for access from other .c files */
1088 int eventdev_sw_log_level;
1090 RTE_INIT(evdev_sw_init_log)
1092 eventdev_sw_log_level = rte_log_register("pmd.event.sw");
1093 if (eventdev_sw_log_level >= 0)
1094 rte_log_set_level(eventdev_sw_log_level, RTE_LOG_NOTICE);