4 * Copyright(c) 2016-2017 Intel Corporation. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Intel Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <rte_memzone.h>
38 #include <rte_kvargs.h>
40 #include <rte_errno.h>
41 #include <rte_event_ring.h>
46 #define EVENTDEV_NAME_SW_PMD event_sw
47 #define NUMA_NODE_ARG "numa_node"
48 #define SCHED_QUANTA_ARG "sched_quanta"
49 #define CREDIT_QUANTA_ARG "credit_quanta"
52 sw_info_get(struct rte_eventdev *dev, struct rte_event_dev_info *info);
55 sw_port_link(struct rte_eventdev *dev, void *port, const uint8_t queues[],
56 const uint8_t priorities[], uint16_t num)
58 struct sw_port *p = port;
59 struct sw_evdev *sw = sw_pmd_priv(dev);
62 RTE_SET_USED(priorities);
63 for (i = 0; i < num; i++) {
64 struct sw_qid *q = &sw->qids[queues[i]];
66 /* check for qid map overflow */
67 if (q->cq_num_mapped_cqs >= RTE_DIM(q->cq_map)) {
72 if (p->is_directed && p->num_qids_mapped > 0) {
77 if (q->type == SW_SCHED_TYPE_DIRECT) {
78 /* check directed qids only map to one port */
79 if (p->num_qids_mapped > 0) {
83 /* check port only takes a directed flow */
90 p->num_qids_mapped = 1;
91 } else if (q->type == RTE_SCHED_TYPE_ORDERED) {
92 p->num_ordered_qids++;
94 } else if (q->type == RTE_SCHED_TYPE_ATOMIC ||
95 q->type == RTE_SCHED_TYPE_PARALLEL) {
99 q->cq_map[q->cq_num_mapped_cqs] = p->id;
101 q->cq_num_mapped_cqs++;
107 sw_port_unlink(struct rte_eventdev *dev, void *port, uint8_t queues[],
110 struct sw_port *p = port;
111 struct sw_evdev *sw = sw_pmd_priv(dev);
115 for (i = 0; i < nb_unlinks; i++) {
116 struct sw_qid *q = &sw->qids[queues[i]];
117 for (j = 0; j < q->cq_num_mapped_cqs; j++) {
118 if (q->cq_map[j] == p->id) {
120 q->cq_map[q->cq_num_mapped_cqs - 1];
122 q->cq_num_mapped_cqs--;
125 p->num_qids_mapped--;
127 if (q->type == RTE_SCHED_TYPE_ORDERED)
128 p->num_ordered_qids--;
138 sw_port_setup(struct rte_eventdev *dev, uint8_t port_id,
139 const struct rte_event_port_conf *conf)
141 struct sw_evdev *sw = sw_pmd_priv(dev);
142 struct sw_port *p = &sw->ports[port_id];
143 char buf[RTE_RING_NAMESIZE];
146 struct rte_event_dev_info info;
147 sw_info_get(dev, &info);
149 /* detect re-configuring and return credits to instance if needed */
150 if (p->initialized) {
151 /* taking credits from pool is done one quanta at a time, and
152 * credits may be spend (counted in p->inflights) or still
153 * available in the port (p->inflight_credits). We must return
154 * the sum to no leak credits
156 int possible_inflights = p->inflight_credits + p->inflights;
157 rte_atomic32_sub(&sw->inflights, possible_inflights);
160 *p = (struct sw_port){0}; /* zero entire structure */
164 /* check to see if rings exists - port_setup() can be called multiple
165 * times legally (assuming device is stopped). If ring exists, free it
166 * to so it gets re-created with the correct size
168 snprintf(buf, sizeof(buf), "sw%d_p%u_%s", dev->data->dev_id,
169 port_id, "rx_worker_ring");
170 struct rte_event_ring *existing_ring = rte_event_ring_lookup(buf);
172 rte_event_ring_free(existing_ring);
174 p->rx_worker_ring = rte_event_ring_create(buf, MAX_SW_PROD_Q_DEPTH,
175 dev->data->socket_id,
176 RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ);
177 if (p->rx_worker_ring == NULL) {
178 SW_LOG_ERR("Error creating RX worker ring for port %d\n",
183 p->inflight_max = conf->new_event_threshold;
185 /* check if ring exists, same as rx_worker above */
186 snprintf(buf, sizeof(buf), "sw%d_p%u, %s", dev->data->dev_id,
187 port_id, "cq_worker_ring");
188 existing_ring = rte_event_ring_lookup(buf);
190 rte_event_ring_free(existing_ring);
192 p->cq_worker_ring = rte_event_ring_create(buf, conf->dequeue_depth,
193 dev->data->socket_id,
194 RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ);
195 if (p->cq_worker_ring == NULL) {
196 rte_event_ring_free(p->rx_worker_ring);
197 SW_LOG_ERR("Error creating CQ worker ring for port %d\n",
201 sw->cq_ring_space[port_id] = conf->dequeue_depth;
203 /* set hist list contents to empty */
204 for (i = 0; i < SW_PORT_HIST_LIST; i++) {
205 p->hist_list[i].fid = -1;
206 p->hist_list[i].qid = -1;
208 dev->data->ports[port_id] = p;
216 sw_port_release(void *port)
218 struct sw_port *p = (void *)port;
222 rte_event_ring_free(p->rx_worker_ring);
223 rte_event_ring_free(p->cq_worker_ring);
224 memset(p, 0, sizeof(*p));
228 qid_init(struct sw_evdev *sw, unsigned int idx, int type,
229 const struct rte_event_queue_conf *queue_conf)
232 int dev_id = sw->data->dev_id;
233 int socket_id = sw->data->socket_id;
234 char buf[IQ_RING_NAMESIZE];
235 struct sw_qid *qid = &sw->qids[idx];
237 for (i = 0; i < SW_IQS_MAX; i++) {
238 snprintf(buf, sizeof(buf), "q_%u_iq_%d", idx, i);
239 qid->iq[i] = iq_ring_create(buf, socket_id);
241 SW_LOG_DBG("ring create failed");
246 /* Initialize the FID structures to no pinning (-1), and zero packets */
247 const struct sw_fid_t fid = {.cq = -1, .pcount = 0};
248 for (i = 0; i < RTE_DIM(qid->fids); i++)
253 qid->priority = queue_conf->priority;
255 if (qid->type == RTE_SCHED_TYPE_ORDERED) {
256 char ring_name[RTE_RING_NAMESIZE];
257 uint32_t window_size;
259 /* rte_ring and window_size_mask require require window_size to
262 window_size = rte_align32pow2(
263 queue_conf->nb_atomic_order_sequences);
265 qid->window_size = window_size - 1;
269 "invalid reorder_window_size for ordered queue\n"
274 snprintf(buf, sizeof(buf), "sw%d_iq_%d_rob", dev_id, i);
275 qid->reorder_buffer = rte_zmalloc_socket(buf,
276 window_size * sizeof(qid->reorder_buffer[0]),
278 if (!qid->reorder_buffer) {
279 SW_LOG_DBG("reorder_buffer malloc failed\n");
283 memset(&qid->reorder_buffer[0],
285 window_size * sizeof(qid->reorder_buffer[0]));
287 snprintf(ring_name, sizeof(ring_name), "sw%d_q%d_freelist",
290 /* lookup the ring, and if it already exists, free it */
291 struct rte_ring *cleanup = rte_ring_lookup(ring_name);
293 rte_ring_free(cleanup);
295 qid->reorder_buffer_freelist = rte_ring_create(ring_name,
298 RING_F_SP_ENQ | RING_F_SC_DEQ);
299 if (!qid->reorder_buffer_freelist) {
300 SW_LOG_DBG("freelist ring create failed");
304 /* Populate the freelist with reorder buffer entries. Enqueue
305 * 'window_size - 1' entries because the rte_ring holds only
308 for (i = 0; i < window_size - 1; i++) {
309 if (rte_ring_sp_enqueue(qid->reorder_buffer_freelist,
310 &qid->reorder_buffer[i]) < 0)
314 qid->reorder_buffer_index = 0;
318 qid->initialized = 1;
323 for (i = 0; i < SW_IQS_MAX; i++) {
325 iq_ring_destroy(qid->iq[i]);
328 if (qid->reorder_buffer) {
329 rte_free(qid->reorder_buffer);
330 qid->reorder_buffer = NULL;
333 if (qid->reorder_buffer_freelist) {
334 rte_ring_free(qid->reorder_buffer_freelist);
335 qid->reorder_buffer_freelist = NULL;
342 sw_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
343 const struct rte_event_queue_conf *conf)
347 /* SINGLE_LINK can be OR-ed with other types, so handle first */
348 if (RTE_EVENT_QUEUE_CFG_SINGLE_LINK & conf->event_queue_cfg) {
349 type = SW_SCHED_TYPE_DIRECT;
351 switch (conf->event_queue_cfg) {
352 case RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY:
353 type = RTE_SCHED_TYPE_ATOMIC;
355 case RTE_EVENT_QUEUE_CFG_ORDERED_ONLY:
356 type = RTE_SCHED_TYPE_ORDERED;
358 case RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY:
359 type = RTE_SCHED_TYPE_PARALLEL;
361 case RTE_EVENT_QUEUE_CFG_ALL_TYPES:
362 SW_LOG_ERR("QUEUE_CFG_ALL_TYPES not supported\n");
365 SW_LOG_ERR("Unknown queue type %d requested\n",
366 conf->event_queue_cfg);
371 struct sw_evdev *sw = sw_pmd_priv(dev);
372 return qid_init(sw, queue_id, type, conf);
376 sw_queue_release(struct rte_eventdev *dev, uint8_t id)
378 struct sw_evdev *sw = sw_pmd_priv(dev);
379 struct sw_qid *qid = &sw->qids[id];
382 for (i = 0; i < SW_IQS_MAX; i++)
383 iq_ring_destroy(qid->iq[i]);
385 if (qid->type == RTE_SCHED_TYPE_ORDERED) {
386 rte_free(qid->reorder_buffer);
387 rte_ring_free(qid->reorder_buffer_freelist);
389 memset(qid, 0, sizeof(*qid));
393 sw_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
394 struct rte_event_queue_conf *conf)
397 RTE_SET_USED(queue_id);
399 static const struct rte_event_queue_conf default_conf = {
400 .nb_atomic_flows = 4096,
401 .nb_atomic_order_sequences = 1,
402 .event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY,
403 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
406 *conf = default_conf;
410 sw_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
411 struct rte_event_port_conf *port_conf)
414 RTE_SET_USED(port_id);
416 port_conf->new_event_threshold = 1024;
417 port_conf->dequeue_depth = 16;
418 port_conf->enqueue_depth = 16;
422 sw_dev_configure(const struct rte_eventdev *dev)
424 struct sw_evdev *sw = sw_pmd_priv(dev);
425 const struct rte_eventdev_data *data = dev->data;
426 const struct rte_event_dev_config *conf = &data->dev_conf;
428 sw->qid_count = conf->nb_event_queues;
429 sw->port_count = conf->nb_event_ports;
430 sw->nb_events_limit = conf->nb_events_limit;
431 rte_atomic32_set(&sw->inflights, 0);
433 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
440 sw_info_get(struct rte_eventdev *dev, struct rte_event_dev_info *info)
444 static const struct rte_event_dev_info evdev_sw_info = {
445 .driver_name = SW_PMD_NAME,
446 .max_event_queues = RTE_EVENT_MAX_QUEUES_PER_DEV,
447 .max_event_queue_flows = SW_QID_NUM_FIDS,
448 .max_event_queue_priority_levels = SW_Q_PRIORITY_MAX,
449 .max_event_priority_levels = SW_IQS_MAX,
450 .max_event_ports = SW_PORTS_MAX,
451 .max_event_port_dequeue_depth = MAX_SW_CONS_Q_DEPTH,
452 .max_event_port_enqueue_depth = MAX_SW_PROD_Q_DEPTH,
453 .max_num_events = SW_INFLIGHT_EVENTS_TOTAL,
454 .event_dev_cap = (RTE_EVENT_DEV_CAP_QUEUE_QOS |
455 RTE_EVENT_DEV_CAP_BURST_MODE |
456 RTE_EVENT_DEV_CAP_EVENT_QOS),
459 *info = evdev_sw_info;
463 sw_dump(struct rte_eventdev *dev, FILE *f)
465 const struct sw_evdev *sw = sw_pmd_priv(dev);
467 static const char * const q_type_strings[] = {
468 "Ordered", "Atomic", "Parallel", "Directed"
471 fprintf(f, "EventDev %s: ports %d, qids %d\n", "todo-fix-name",
472 sw->port_count, sw->qid_count);
474 fprintf(f, "\trx %"PRIu64"\n\tdrop %"PRIu64"\n\ttx %"PRIu64"\n",
475 sw->stats.rx_pkts, sw->stats.rx_dropped, sw->stats.tx_pkts);
476 fprintf(f, "\tsched calls: %"PRIu64"\n", sw->sched_called);
477 fprintf(f, "\tsched cq/qid call: %"PRIu64"\n", sw->sched_cq_qid_called);
478 fprintf(f, "\tsched no IQ enq: %"PRIu64"\n", sw->sched_no_iq_enqueues);
479 fprintf(f, "\tsched no CQ enq: %"PRIu64"\n", sw->sched_no_cq_enqueues);
480 uint32_t inflights = rte_atomic32_read(&sw->inflights);
481 uint32_t credits = sw->nb_events_limit - inflights;
482 fprintf(f, "\tinflight %d, credits: %d\n", inflights, credits);
484 #define COL_RED "\x1b[31m"
485 #define COL_RESET "\x1b[0m"
487 for (i = 0; i < sw->port_count; i++) {
489 const struct sw_port *p = &sw->ports[i];
490 if (!p->initialized) {
491 fprintf(f, " %sPort %d not initialized.%s\n",
492 COL_RED, i, COL_RESET);
495 fprintf(f, " Port %d %s\n", i,
496 p->is_directed ? " (SingleCons)" : "");
497 fprintf(f, "\trx %"PRIu64"\tdrop %"PRIu64"\ttx %"PRIu64
498 "\t%sinflight %d%s\n", sw->ports[i].stats.rx_pkts,
499 sw->ports[i].stats.rx_dropped,
500 sw->ports[i].stats.tx_pkts,
501 (p->inflights == p->inflight_max) ?
503 sw->ports[i].inflights, COL_RESET);
505 fprintf(f, "\tMax New: %u"
506 "\tAvg cycles PP: %"PRIu64"\tCredits: %u\n",
507 sw->ports[i].inflight_max,
508 sw->ports[i].avg_pkt_ticks,
509 sw->ports[i].inflight_credits);
510 fprintf(f, "\tReceive burst distribution:\n");
511 float zp_percent = p->zero_polls * 100.0 / p->total_polls;
512 fprintf(f, zp_percent < 10 ? "\t\t0:%.02f%% " : "\t\t0:%.0f%% ",
514 for (max = (int)RTE_DIM(p->poll_buckets); max-- > 0;)
515 if (p->poll_buckets[max] != 0)
517 for (j = 0; j <= max; j++) {
518 if (p->poll_buckets[j] != 0) {
519 float poll_pc = p->poll_buckets[j] * 100.0 /
521 fprintf(f, "%u-%u:%.02f%% ",
522 ((j << SW_DEQ_STAT_BUCKET_SHIFT) + 1),
523 ((j+1) << SW_DEQ_STAT_BUCKET_SHIFT),
529 if (p->rx_worker_ring) {
530 uint64_t used = rte_event_ring_count(p->rx_worker_ring);
531 uint64_t space = rte_event_ring_free_count(
533 const char *col = (space == 0) ? COL_RED : COL_RESET;
534 fprintf(f, "\t%srx ring used: %4"PRIu64"\tfree: %4"
535 PRIu64 COL_RESET"\n", col, used, space);
537 fprintf(f, "\trx ring not initialized.\n");
539 if (p->cq_worker_ring) {
540 uint64_t used = rte_event_ring_count(p->cq_worker_ring);
541 uint64_t space = rte_event_ring_free_count(
543 const char *col = (space == 0) ? COL_RED : COL_RESET;
544 fprintf(f, "\t%scq ring used: %4"PRIu64"\tfree: %4"
545 PRIu64 COL_RESET"\n", col, used, space);
547 fprintf(f, "\tcq ring not initialized.\n");
550 for (i = 0; i < sw->qid_count; i++) {
551 const struct sw_qid *qid = &sw->qids[i];
552 if (!qid->initialized) {
553 fprintf(f, " %sQueue %d not initialized.%s\n",
554 COL_RED, i, COL_RESET);
557 int affinities_per_port[SW_PORTS_MAX] = {0};
558 uint32_t inflights = 0;
560 fprintf(f, " Queue %d (%s)\n", i, q_type_strings[qid->type]);
561 fprintf(f, "\trx %"PRIu64"\tdrop %"PRIu64"\ttx %"PRIu64"\n",
562 qid->stats.rx_pkts, qid->stats.rx_dropped,
564 if (qid->type == RTE_SCHED_TYPE_ORDERED) {
565 struct rte_ring *rob_buf_free =
566 qid->reorder_buffer_freelist;
568 fprintf(f, "\tReorder entries in use: %u\n",
569 rte_ring_free_count(rob_buf_free));
572 "\tReorder buffer not initialized\n");
576 for (flow = 0; flow < RTE_DIM(qid->fids); flow++)
577 if (qid->fids[flow].cq != -1) {
578 affinities_per_port[qid->fids[flow].cq]++;
579 inflights += qid->fids[flow].pcount;
583 fprintf(f, "\tPer Port Stats:\n");
584 for (port = 0; port < sw->port_count; port++) {
585 fprintf(f, "\t Port %d: Pkts: %"PRIu64, port,
587 fprintf(f, "\tFlows: %d\n", affinities_per_port[port]);
591 uint32_t iq_printed = 0;
592 for (iq = 0; iq < SW_IQS_MAX; iq++) {
594 fprintf(f, "\tiq %d is not initialized.\n", iq);
598 uint32_t used = iq_ring_count(qid->iq[iq]);
599 uint32_t free = iq_ring_free_count(qid->iq[iq]);
600 const char *col = (free == 0) ? COL_RED : COL_RESET;
602 fprintf(f, "\t%siq %d: Used %d\tFree %d"
603 COL_RESET"\n", col, iq, used, free);
608 fprintf(f, "\t-- iqs empty --\n");
613 sw_start(struct rte_eventdev *dev)
616 struct sw_evdev *sw = sw_pmd_priv(dev);
617 /* check all ports are set up */
618 for (i = 0; i < sw->port_count; i++)
619 if (sw->ports[i].rx_worker_ring == NULL) {
620 SW_LOG_ERR("Port %d not configured\n", i);
624 /* check all queues are configured and mapped to ports*/
625 for (i = 0; i < sw->qid_count; i++)
626 if (sw->qids[i].iq[0] == NULL ||
627 sw->qids[i].cq_num_mapped_cqs == 0) {
628 SW_LOG_ERR("Queue %d not configured\n", i);
632 /* build up our prioritized array of qids */
633 /* We don't use qsort here, as if all/multiple entries have the same
634 * priority, the result is non-deterministic. From "man 3 qsort":
635 * "If two members compare as equal, their order in the sorted
636 * array is undefined."
639 for (j = 0; j <= RTE_EVENT_DEV_PRIORITY_LOWEST; j++) {
640 for (i = 0; i < sw->qid_count; i++) {
641 if (sw->qids[i].priority == j) {
642 sw->qids_prioritized[qidx] = &sw->qids[i];
648 if (sw_xstats_init(sw) < 0)
658 sw_stop(struct rte_eventdev *dev)
660 struct sw_evdev *sw = sw_pmd_priv(dev);
661 sw_xstats_uninit(sw);
667 sw_close(struct rte_eventdev *dev)
669 struct sw_evdev *sw = sw_pmd_priv(dev);
672 for (i = 0; i < sw->qid_count; i++)
673 sw_queue_release(dev, i);
676 for (i = 0; i < sw->port_count; i++)
677 sw_port_release(&sw->ports[i]);
680 memset(&sw->stats, 0, sizeof(sw->stats));
681 sw->sched_called = 0;
682 sw->sched_no_iq_enqueues = 0;
683 sw->sched_no_cq_enqueues = 0;
684 sw->sched_cq_qid_called = 0;
690 assign_numa_node(const char *key __rte_unused, const char *value, void *opaque)
692 int *socket_id = opaque;
693 *socket_id = atoi(value);
694 if (*socket_id >= RTE_MAX_NUMA_NODES)
700 set_sched_quanta(const char *key __rte_unused, const char *value, void *opaque)
702 int *quanta = opaque;
703 *quanta = atoi(value);
704 if (*quanta < 0 || *quanta >= 4096)
710 set_credit_quanta(const char *key __rte_unused, const char *value, void *opaque)
712 int *credit = opaque;
713 *credit = atoi(value);
714 if (*credit < 0 || *credit >= 128)
720 sw_probe(struct rte_vdev_device *vdev)
722 static const struct rte_eventdev_ops evdev_sw_ops = {
723 .dev_configure = sw_dev_configure,
724 .dev_infos_get = sw_info_get,
725 .dev_close = sw_close,
726 .dev_start = sw_start,
730 .queue_def_conf = sw_queue_def_conf,
731 .queue_setup = sw_queue_setup,
732 .queue_release = sw_queue_release,
733 .port_def_conf = sw_port_def_conf,
734 .port_setup = sw_port_setup,
735 .port_release = sw_port_release,
736 .port_link = sw_port_link,
737 .port_unlink = sw_port_unlink,
739 .xstats_get = sw_xstats_get,
740 .xstats_get_names = sw_xstats_get_names,
741 .xstats_get_by_name = sw_xstats_get_by_name,
742 .xstats_reset = sw_xstats_reset,
745 static const char *const args[] = {
753 struct rte_eventdev *dev;
755 int socket_id = rte_socket_id();
756 int sched_quanta = SW_DEFAULT_SCHED_QUANTA;
757 int credit_quanta = SW_DEFAULT_CREDIT_QUANTA;
759 name = rte_vdev_device_name(vdev);
760 params = rte_vdev_device_args(vdev);
761 if (params != NULL && params[0] != '\0') {
762 struct rte_kvargs *kvlist = rte_kvargs_parse(params, args);
766 "Ignoring unsupported parameters when creating device '%s'\n",
769 int ret = rte_kvargs_process(kvlist, NUMA_NODE_ARG,
770 assign_numa_node, &socket_id);
773 "%s: Error parsing numa node parameter",
775 rte_kvargs_free(kvlist);
779 ret = rte_kvargs_process(kvlist, SCHED_QUANTA_ARG,
780 set_sched_quanta, &sched_quanta);
783 "%s: Error parsing sched quanta parameter",
785 rte_kvargs_free(kvlist);
789 ret = rte_kvargs_process(kvlist, CREDIT_QUANTA_ARG,
790 set_credit_quanta, &credit_quanta);
793 "%s: Error parsing credit quanta parameter",
795 rte_kvargs_free(kvlist);
799 rte_kvargs_free(kvlist);
804 "Creating eventdev sw device %s, numa_node=%d, sched_quanta=%d, credit_quanta=%d\n",
805 name, socket_id, sched_quanta, credit_quanta);
807 dev = rte_event_pmd_vdev_init(name,
808 sizeof(struct sw_evdev), socket_id);
810 SW_LOG_ERR("eventdev vdev init() failed");
813 dev->dev_ops = &evdev_sw_ops;
814 dev->enqueue = sw_event_enqueue;
815 dev->enqueue_burst = sw_event_enqueue_burst;
816 dev->enqueue_new_burst = sw_event_enqueue_burst;
817 dev->enqueue_forward_burst = sw_event_enqueue_burst;
818 dev->dequeue = sw_event_dequeue;
819 dev->dequeue_burst = sw_event_dequeue_burst;
820 dev->schedule = sw_event_schedule;
822 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
825 sw = dev->data->dev_private;
826 sw->data = dev->data;
828 /* copy values passed from vdev command line to instance */
829 sw->credit_update_quanta = credit_quanta;
830 sw->sched_quanta = sched_quanta;
836 sw_remove(struct rte_vdev_device *vdev)
840 name = rte_vdev_device_name(vdev);
844 SW_LOG_INFO("Closing eventdev sw device %s\n", name);
846 return rte_event_pmd_vdev_uninit(name);
849 static struct rte_vdev_driver evdev_sw_pmd_drv = {
854 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_SW_PMD, evdev_sw_pmd_drv);
855 RTE_PMD_REGISTER_PARAM_STRING(event_sw, NUMA_NODE_ARG "=<int> "
856 SCHED_QUANTA_ARG "=<int>" CREDIT_QUANTA_ARG "=<int>");