4 * Copyright(c) 2016-2017 Intel Corporation. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Intel Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <rte_memzone.h>
37 #include <rte_kvargs.h>
39 #include <rte_errno.h>
43 #include "event_ring.h"
45 #define EVENTDEV_NAME_SW_PMD event_sw
46 #define NUMA_NODE_ARG "numa_node"
47 #define SCHED_QUANTA_ARG "sched_quanta"
48 #define CREDIT_QUANTA_ARG "credit_quanta"
51 sw_info_get(struct rte_eventdev *dev, struct rte_event_dev_info *info);
54 sw_port_link(struct rte_eventdev *dev, void *port, const uint8_t queues[],
55 const uint8_t priorities[], uint16_t num)
57 struct sw_port *p = port;
58 struct sw_evdev *sw = sw_pmd_priv(dev);
61 RTE_SET_USED(priorities);
62 for (i = 0; i < num; i++) {
63 struct sw_qid *q = &sw->qids[queues[i]];
65 /* check for qid map overflow */
66 if (q->cq_num_mapped_cqs >= RTE_DIM(q->cq_map)) {
71 if (p->is_directed && p->num_qids_mapped > 0) {
76 if (q->type == SW_SCHED_TYPE_DIRECT) {
77 /* check directed qids only map to one port */
78 if (p->num_qids_mapped > 0) {
82 /* check port only takes a directed flow */
89 p->num_qids_mapped = 1;
90 } else if (q->type == RTE_SCHED_TYPE_ORDERED) {
91 p->num_ordered_qids++;
93 } else if (q->type == RTE_SCHED_TYPE_ATOMIC ||
94 q->type == RTE_SCHED_TYPE_PARALLEL) {
98 q->cq_map[q->cq_num_mapped_cqs] = p->id;
100 q->cq_num_mapped_cqs++;
106 sw_port_unlink(struct rte_eventdev *dev, void *port, uint8_t queues[],
109 struct sw_port *p = port;
110 struct sw_evdev *sw = sw_pmd_priv(dev);
114 for (i = 0; i < nb_unlinks; i++) {
115 struct sw_qid *q = &sw->qids[queues[i]];
116 for (j = 0; j < q->cq_num_mapped_cqs; j++) {
117 if (q->cq_map[j] == p->id) {
119 q->cq_map[q->cq_num_mapped_cqs - 1];
121 q->cq_num_mapped_cqs--;
124 p->num_qids_mapped--;
126 if (q->type == RTE_SCHED_TYPE_ORDERED)
127 p->num_ordered_qids--;
137 sw_port_setup(struct rte_eventdev *dev, uint8_t port_id,
138 const struct rte_event_port_conf *conf)
140 struct sw_evdev *sw = sw_pmd_priv(dev);
141 struct sw_port *p = &sw->ports[port_id];
142 char buf[QE_RING_NAMESIZE];
145 struct rte_event_dev_info info;
146 sw_info_get(dev, &info);
148 /* detect re-configuring and return credits to instance if needed */
149 if (p->initialized) {
150 /* taking credits from pool is done one quanta at a time, and
151 * credits may be spend (counted in p->inflights) or still
152 * available in the port (p->inflight_credits). We must return
153 * the sum to no leak credits
155 int possible_inflights = p->inflight_credits + p->inflights;
156 rte_atomic32_sub(&sw->inflights, possible_inflights);
159 *p = (struct sw_port){0}; /* zero entire structure */
163 snprintf(buf, sizeof(buf), "sw%d_%s", dev->data->dev_id,
165 p->rx_worker_ring = qe_ring_create(buf, MAX_SW_PROD_Q_DEPTH,
166 dev->data->socket_id);
167 if (p->rx_worker_ring == NULL) {
168 SW_LOG_ERR("Error creating RX worker ring for port %d\n",
173 p->inflight_max = conf->new_event_threshold;
175 snprintf(buf, sizeof(buf), "sw%d_%s", dev->data->dev_id,
177 p->cq_worker_ring = qe_ring_create(buf, conf->dequeue_depth,
178 dev->data->socket_id);
179 if (p->cq_worker_ring == NULL) {
180 qe_ring_destroy(p->rx_worker_ring);
181 SW_LOG_ERR("Error creating CQ worker ring for port %d\n",
185 sw->cq_ring_space[port_id] = conf->dequeue_depth;
187 /* set hist list contents to empty */
188 for (i = 0; i < SW_PORT_HIST_LIST; i++) {
189 p->hist_list[i].fid = -1;
190 p->hist_list[i].qid = -1;
192 dev->data->ports[port_id] = p;
200 sw_port_release(void *port)
202 struct sw_port *p = (void *)port;
206 qe_ring_destroy(p->rx_worker_ring);
207 qe_ring_destroy(p->cq_worker_ring);
208 memset(p, 0, sizeof(*p));
212 qid_init(struct sw_evdev *sw, unsigned int idx, int type,
213 const struct rte_event_queue_conf *queue_conf)
216 int dev_id = sw->data->dev_id;
217 int socket_id = sw->data->socket_id;
218 char buf[IQ_RING_NAMESIZE];
219 struct sw_qid *qid = &sw->qids[idx];
221 for (i = 0; i < SW_IQS_MAX; i++) {
222 snprintf(buf, sizeof(buf), "q_%u_iq_%d", idx, i);
223 qid->iq[i] = iq_ring_create(buf, socket_id);
225 SW_LOG_DBG("ring create failed");
230 /* Initialize the FID structures to no pinning (-1), and zero packets */
231 const struct sw_fid_t fid = {.cq = -1, .pcount = 0};
232 for (i = 0; i < RTE_DIM(qid->fids); i++)
237 qid->priority = queue_conf->priority;
239 if (qid->type == RTE_SCHED_TYPE_ORDERED) {
240 char ring_name[RTE_RING_NAMESIZE];
241 uint32_t window_size;
243 /* rte_ring and window_size_mask require require window_size to
246 window_size = rte_align32pow2(
247 queue_conf->nb_atomic_order_sequences);
249 qid->window_size = window_size - 1;
253 "invalid reorder_window_size for ordered queue\n"
258 snprintf(buf, sizeof(buf), "sw%d_iq_%d_rob", dev_id, i);
259 qid->reorder_buffer = rte_zmalloc_socket(buf,
260 window_size * sizeof(qid->reorder_buffer[0]),
262 if (!qid->reorder_buffer) {
263 SW_LOG_DBG("reorder_buffer malloc failed\n");
267 memset(&qid->reorder_buffer[0],
269 window_size * sizeof(qid->reorder_buffer[0]));
271 snprintf(ring_name, sizeof(ring_name), "sw%d_q%d_freelist",
274 /* lookup the ring, and if it already exists, free it */
275 struct rte_ring *cleanup = rte_ring_lookup(ring_name);
277 rte_ring_free(cleanup);
279 qid->reorder_buffer_freelist = rte_ring_create(ring_name,
282 RING_F_SP_ENQ | RING_F_SC_DEQ);
283 if (!qid->reorder_buffer_freelist) {
284 SW_LOG_DBG("freelist ring create failed");
288 /* Populate the freelist with reorder buffer entries. Enqueue
289 * 'window_size - 1' entries because the rte_ring holds only
292 for (i = 0; i < window_size - 1; i++) {
293 if (rte_ring_sp_enqueue(qid->reorder_buffer_freelist,
294 &qid->reorder_buffer[i]) < 0)
298 qid->reorder_buffer_index = 0;
302 qid->initialized = 1;
307 for (i = 0; i < SW_IQS_MAX; i++) {
309 iq_ring_destroy(qid->iq[i]);
312 if (qid->reorder_buffer) {
313 rte_free(qid->reorder_buffer);
314 qid->reorder_buffer = NULL;
317 if (qid->reorder_buffer_freelist) {
318 rte_ring_free(qid->reorder_buffer_freelist);
319 qid->reorder_buffer_freelist = NULL;
326 sw_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
327 const struct rte_event_queue_conf *conf)
331 /* SINGLE_LINK can be OR-ed with other types, so handle first */
332 if (RTE_EVENT_QUEUE_CFG_SINGLE_LINK & conf->event_queue_cfg) {
333 type = SW_SCHED_TYPE_DIRECT;
335 switch (conf->event_queue_cfg) {
336 case RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY:
337 type = RTE_SCHED_TYPE_ATOMIC;
339 case RTE_EVENT_QUEUE_CFG_ORDERED_ONLY:
340 type = RTE_SCHED_TYPE_ORDERED;
342 case RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY:
343 type = RTE_SCHED_TYPE_PARALLEL;
345 case RTE_EVENT_QUEUE_CFG_ALL_TYPES:
346 SW_LOG_ERR("QUEUE_CFG_ALL_TYPES not supported\n");
349 SW_LOG_ERR("Unknown queue type %d requested\n",
350 conf->event_queue_cfg);
355 struct sw_evdev *sw = sw_pmd_priv(dev);
356 return qid_init(sw, queue_id, type, conf);
360 sw_queue_release(struct rte_eventdev *dev, uint8_t id)
362 struct sw_evdev *sw = sw_pmd_priv(dev);
363 struct sw_qid *qid = &sw->qids[id];
366 for (i = 0; i < SW_IQS_MAX; i++)
367 iq_ring_destroy(qid->iq[i]);
369 if (qid->type == RTE_SCHED_TYPE_ORDERED) {
370 rte_free(qid->reorder_buffer);
371 rte_ring_free(qid->reorder_buffer_freelist);
373 memset(qid, 0, sizeof(*qid));
377 sw_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
378 struct rte_event_queue_conf *conf)
381 RTE_SET_USED(queue_id);
383 static const struct rte_event_queue_conf default_conf = {
384 .nb_atomic_flows = 4096,
385 .nb_atomic_order_sequences = 1,
386 .event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY,
387 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
390 *conf = default_conf;
394 sw_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
395 struct rte_event_port_conf *port_conf)
398 RTE_SET_USED(port_id);
400 port_conf->new_event_threshold = 1024;
401 port_conf->dequeue_depth = 16;
402 port_conf->enqueue_depth = 16;
406 sw_dev_configure(const struct rte_eventdev *dev)
408 struct sw_evdev *sw = sw_pmd_priv(dev);
409 const struct rte_eventdev_data *data = dev->data;
410 const struct rte_event_dev_config *conf = &data->dev_conf;
412 sw->qid_count = conf->nb_event_queues;
413 sw->port_count = conf->nb_event_ports;
414 sw->nb_events_limit = conf->nb_events_limit;
415 rte_atomic32_set(&sw->inflights, 0);
417 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
424 sw_info_get(struct rte_eventdev *dev, struct rte_event_dev_info *info)
428 static const struct rte_event_dev_info evdev_sw_info = {
429 .driver_name = SW_PMD_NAME,
430 .max_event_queues = RTE_EVENT_MAX_QUEUES_PER_DEV,
431 .max_event_queue_flows = SW_QID_NUM_FIDS,
432 .max_event_queue_priority_levels = SW_Q_PRIORITY_MAX,
433 .max_event_priority_levels = SW_IQS_MAX,
434 .max_event_ports = SW_PORTS_MAX,
435 .max_event_port_dequeue_depth = MAX_SW_CONS_Q_DEPTH,
436 .max_event_port_enqueue_depth = MAX_SW_PROD_Q_DEPTH,
437 .max_num_events = SW_INFLIGHT_EVENTS_TOTAL,
438 .event_dev_cap = (RTE_EVENT_DEV_CAP_QUEUE_QOS |
439 RTE_EVENT_DEV_CAP_EVENT_QOS),
442 *info = evdev_sw_info;
446 sw_dump(struct rte_eventdev *dev, FILE *f)
448 const struct sw_evdev *sw = sw_pmd_priv(dev);
450 static const char * const q_type_strings[] = {
451 "Ordered", "Atomic", "Parallel", "Directed"
454 fprintf(f, "EventDev %s: ports %d, qids %d\n", "todo-fix-name",
455 sw->port_count, sw->qid_count);
457 fprintf(f, "\trx %"PRIu64"\n\tdrop %"PRIu64"\n\ttx %"PRIu64"\n",
458 sw->stats.rx_pkts, sw->stats.rx_dropped, sw->stats.tx_pkts);
459 fprintf(f, "\tsched calls: %"PRIu64"\n", sw->sched_called);
460 fprintf(f, "\tsched cq/qid call: %"PRIu64"\n", sw->sched_cq_qid_called);
461 fprintf(f, "\tsched no IQ enq: %"PRIu64"\n", sw->sched_no_iq_enqueues);
462 fprintf(f, "\tsched no CQ enq: %"PRIu64"\n", sw->sched_no_cq_enqueues);
463 uint32_t inflights = rte_atomic32_read(&sw->inflights);
464 uint32_t credits = sw->nb_events_limit - inflights;
465 fprintf(f, "\tinflight %d, credits: %d\n", inflights, credits);
467 #define COL_RED "\x1b[31m"
468 #define COL_RESET "\x1b[0m"
470 for (i = 0; i < sw->port_count; i++) {
472 const struct sw_port *p = &sw->ports[i];
473 if (!p->initialized) {
474 fprintf(f, " %sPort %d not initialized.%s\n",
475 COL_RED, i, COL_RESET);
478 fprintf(f, " Port %d %s\n", i,
479 p->is_directed ? " (SingleCons)" : "");
480 fprintf(f, "\trx %"PRIu64"\tdrop %"PRIu64"\ttx %"PRIu64
481 "\t%sinflight %d%s\n", sw->ports[i].stats.rx_pkts,
482 sw->ports[i].stats.rx_dropped,
483 sw->ports[i].stats.tx_pkts,
484 (p->inflights == p->inflight_max) ?
486 sw->ports[i].inflights, COL_RESET);
488 fprintf(f, "\tMax New: %u"
489 "\tAvg cycles PP: %"PRIu64"\tCredits: %u\n",
490 sw->ports[i].inflight_max,
491 sw->ports[i].avg_pkt_ticks,
492 sw->ports[i].inflight_credits);
493 fprintf(f, "\tReceive burst distribution:\n");
494 float zp_percent = p->zero_polls * 100.0 / p->total_polls;
495 fprintf(f, zp_percent < 10 ? "\t\t0:%.02f%% " : "\t\t0:%.0f%% ",
497 for (max = (int)RTE_DIM(p->poll_buckets); max-- > 0;)
498 if (p->poll_buckets[max] != 0)
500 for (j = 0; j <= max; j++) {
501 if (p->poll_buckets[j] != 0) {
502 float poll_pc = p->poll_buckets[j] * 100.0 /
504 fprintf(f, "%u-%u:%.02f%% ",
505 ((j << SW_DEQ_STAT_BUCKET_SHIFT) + 1),
506 ((j+1) << SW_DEQ_STAT_BUCKET_SHIFT),
512 if (p->rx_worker_ring) {
513 uint64_t used = qe_ring_count(p->rx_worker_ring);
514 uint64_t space = qe_ring_free_count(p->rx_worker_ring);
515 const char *col = (space == 0) ? COL_RED : COL_RESET;
516 fprintf(f, "\t%srx ring used: %4"PRIu64"\tfree: %4"
517 PRIu64 COL_RESET"\n", col, used, space);
519 fprintf(f, "\trx ring not initialized.\n");
521 if (p->cq_worker_ring) {
522 uint64_t used = qe_ring_count(p->cq_worker_ring);
523 uint64_t space = qe_ring_free_count(p->cq_worker_ring);
524 const char *col = (space == 0) ? COL_RED : COL_RESET;
525 fprintf(f, "\t%scq ring used: %4"PRIu64"\tfree: %4"
526 PRIu64 COL_RESET"\n", col, used, space);
528 fprintf(f, "\tcq ring not initialized.\n");
531 for (i = 0; i < sw->qid_count; i++) {
532 const struct sw_qid *qid = &sw->qids[i];
533 if (!qid->initialized) {
534 fprintf(f, " %sQueue %d not initialized.%s\n",
535 COL_RED, i, COL_RESET);
538 int affinities_per_port[SW_PORTS_MAX] = {0};
539 uint32_t inflights = 0;
541 fprintf(f, " Queue %d (%s)\n", i, q_type_strings[qid->type]);
542 fprintf(f, "\trx %"PRIu64"\tdrop %"PRIu64"\ttx %"PRIu64"\n",
543 qid->stats.rx_pkts, qid->stats.rx_dropped,
545 if (qid->type == RTE_SCHED_TYPE_ORDERED) {
546 struct rte_ring *rob_buf_free =
547 qid->reorder_buffer_freelist;
549 fprintf(f, "\tReorder entries in use: %u\n",
550 rte_ring_free_count(rob_buf_free));
553 "\tReorder buffer not initialized\n");
557 for (flow = 0; flow < RTE_DIM(qid->fids); flow++)
558 if (qid->fids[flow].cq != -1) {
559 affinities_per_port[qid->fids[flow].cq]++;
560 inflights += qid->fids[flow].pcount;
564 fprintf(f, "\tPer Port Stats:\n");
565 for (port = 0; port < sw->port_count; port++) {
566 fprintf(f, "\t Port %d: Pkts: %"PRIu64, port,
568 fprintf(f, "\tFlows: %d\n", affinities_per_port[port]);
572 uint32_t iq_printed = 0;
573 for (iq = 0; iq < SW_IQS_MAX; iq++) {
575 fprintf(f, "\tiq %d is not initialized.\n", iq);
579 uint32_t used = iq_ring_count(qid->iq[iq]);
580 uint32_t free = iq_ring_free_count(qid->iq[iq]);
581 const char *col = (free == 0) ? COL_RED : COL_RESET;
583 fprintf(f, "\t%siq %d: Used %d\tFree %d"
584 COL_RESET"\n", col, iq, used, free);
589 fprintf(f, "\t-- iqs empty --\n");
594 sw_start(struct rte_eventdev *dev)
597 struct sw_evdev *sw = sw_pmd_priv(dev);
598 /* check all ports are set up */
599 for (i = 0; i < sw->port_count; i++)
600 if (sw->ports[i].rx_worker_ring == NULL) {
601 SW_LOG_ERR("Port %d not configured\n", i);
605 /* check all queues are configured and mapped to ports*/
606 for (i = 0; i < sw->qid_count; i++)
607 if (sw->qids[i].iq[0] == NULL ||
608 sw->qids[i].cq_num_mapped_cqs == 0) {
609 SW_LOG_ERR("Queue %d not configured\n", i);
613 /* build up our prioritized array of qids */
614 /* We don't use qsort here, as if all/multiple entries have the same
615 * priority, the result is non-deterministic. From "man 3 qsort":
616 * "If two members compare as equal, their order in the sorted
617 * array is undefined."
620 for (j = 0; j <= RTE_EVENT_DEV_PRIORITY_LOWEST; j++) {
621 for (i = 0; i < sw->qid_count; i++) {
622 if (sw->qids[i].priority == j) {
623 sw->qids_prioritized[qidx] = &sw->qids[i];
629 if (sw_xstats_init(sw) < 0)
639 sw_stop(struct rte_eventdev *dev)
641 struct sw_evdev *sw = sw_pmd_priv(dev);
642 sw_xstats_uninit(sw);
648 sw_close(struct rte_eventdev *dev)
650 struct sw_evdev *sw = sw_pmd_priv(dev);
653 for (i = 0; i < sw->qid_count; i++)
654 sw_queue_release(dev, i);
657 for (i = 0; i < sw->port_count; i++)
658 sw_port_release(&sw->ports[i]);
661 memset(&sw->stats, 0, sizeof(sw->stats));
662 sw->sched_called = 0;
663 sw->sched_no_iq_enqueues = 0;
664 sw->sched_no_cq_enqueues = 0;
665 sw->sched_cq_qid_called = 0;
671 assign_numa_node(const char *key __rte_unused, const char *value, void *opaque)
673 int *socket_id = opaque;
674 *socket_id = atoi(value);
675 if (*socket_id >= RTE_MAX_NUMA_NODES)
681 set_sched_quanta(const char *key __rte_unused, const char *value, void *opaque)
683 int *quanta = opaque;
684 *quanta = atoi(value);
685 if (*quanta < 0 || *quanta >= 4096)
691 set_credit_quanta(const char *key __rte_unused, const char *value, void *opaque)
693 int *credit = opaque;
694 *credit = atoi(value);
695 if (*credit < 0 || *credit >= 128)
701 sw_probe(struct rte_vdev_device *vdev)
703 static const struct rte_eventdev_ops evdev_sw_ops = {
704 .dev_configure = sw_dev_configure,
705 .dev_infos_get = sw_info_get,
706 .dev_close = sw_close,
707 .dev_start = sw_start,
711 .queue_def_conf = sw_queue_def_conf,
712 .queue_setup = sw_queue_setup,
713 .queue_release = sw_queue_release,
714 .port_def_conf = sw_port_def_conf,
715 .port_setup = sw_port_setup,
716 .port_release = sw_port_release,
717 .port_link = sw_port_link,
718 .port_unlink = sw_port_unlink,
720 .xstats_get = sw_xstats_get,
721 .xstats_get_names = sw_xstats_get_names,
722 .xstats_get_by_name = sw_xstats_get_by_name,
723 .xstats_reset = sw_xstats_reset,
726 static const char *const args[] = {
734 struct rte_eventdev *dev;
736 int socket_id = rte_socket_id();
737 int sched_quanta = SW_DEFAULT_SCHED_QUANTA;
738 int credit_quanta = SW_DEFAULT_CREDIT_QUANTA;
740 name = rte_vdev_device_name(vdev);
741 params = rte_vdev_device_args(vdev);
742 if (params != NULL && params[0] != '\0') {
743 struct rte_kvargs *kvlist = rte_kvargs_parse(params, args);
747 "Ignoring unsupported parameters when creating device '%s'\n",
750 int ret = rte_kvargs_process(kvlist, NUMA_NODE_ARG,
751 assign_numa_node, &socket_id);
754 "%s: Error parsing numa node parameter",
756 rte_kvargs_free(kvlist);
760 ret = rte_kvargs_process(kvlist, SCHED_QUANTA_ARG,
761 set_sched_quanta, &sched_quanta);
764 "%s: Error parsing sched quanta parameter",
766 rte_kvargs_free(kvlist);
770 ret = rte_kvargs_process(kvlist, CREDIT_QUANTA_ARG,
771 set_credit_quanta, &credit_quanta);
774 "%s: Error parsing credit quanta parameter",
776 rte_kvargs_free(kvlist);
780 rte_kvargs_free(kvlist);
785 "Creating eventdev sw device %s, numa_node=%d, sched_quanta=%d, credit_quanta=%d\n",
786 name, socket_id, sched_quanta, credit_quanta);
788 dev = rte_event_pmd_vdev_init(name,
789 sizeof(struct sw_evdev), socket_id);
791 SW_LOG_ERR("eventdev vdev init() failed");
794 dev->dev_ops = &evdev_sw_ops;
795 dev->enqueue = sw_event_enqueue;
796 dev->enqueue_burst = sw_event_enqueue_burst;
797 dev->dequeue = sw_event_dequeue;
798 dev->dequeue_burst = sw_event_dequeue_burst;
799 dev->schedule = sw_event_schedule;
801 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
804 sw = dev->data->dev_private;
805 sw->data = dev->data;
807 /* copy values passed from vdev command line to instance */
808 sw->credit_update_quanta = credit_quanta;
809 sw->sched_quanta = sched_quanta;
815 sw_remove(struct rte_vdev_device *vdev)
819 name = rte_vdev_device_name(vdev);
823 SW_LOG_INFO("Closing eventdev sw device %s\n", name);
825 return rte_event_pmd_vdev_uninit(name);
828 static struct rte_vdev_driver evdev_sw_pmd_drv = {
833 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_SW_PMD, evdev_sw_pmd_drv);
834 RTE_PMD_REGISTER_PARAM_STRING(event_sw, NUMA_NODE_ARG "=<int> "
835 SCHED_QUANTA_ARG "=<int>" CREDIT_QUANTA_ARG "=<int>");