1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include <rte_atomic.h>
6 #include <rte_bus_pci.h>
7 #include <rte_common.h>
8 #include <rte_devargs.h>
11 #include <rte_kvargs.h>
12 #include <rte_malloc.h>
13 #include <rte_mbuf_pool_ops.h>
18 #define CNXK_NPA_DEV_NAME RTE_STR(cnxk_npa_dev_)
19 #define CNXK_NPA_DEV_NAME_LEN (sizeof(CNXK_NPA_DEV_NAME) + PCI_PRI_STR_SIZE)
20 #define CNXK_NPA_MAX_POOLS_PARAM "max_pools"
22 static inline uint32_t
23 npa_aura_size_to_u32(uint8_t val)
25 if (val == NPA_AURA_SZ_0)
27 if (val >= NPA_AURA_SZ_MAX)
30 return 1 << (val + 6);
34 parse_max_pools_handler(const char *key, const char *value, void *extra_args)
39 val = rte_align32pow2(atoi(value));
40 if (val < npa_aura_size_to_u32(NPA_AURA_SZ_128))
42 if (val > npa_aura_size_to_u32(NPA_AURA_SZ_1M))
45 *(uint32_t *)extra_args = val;
49 static inline uint32_t
50 parse_max_pools(struct rte_devargs *devargs)
52 uint32_t max_pools = npa_aura_size_to_u32(NPA_AURA_SZ_128);
53 struct rte_kvargs *kvlist;
57 kvlist = rte_kvargs_parse(devargs->args, NULL);
61 rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM,
62 &parse_max_pools_handler, &max_pools);
63 rte_kvargs_free(kvlist);
69 npa_dev_to_name(struct rte_pci_device *pci_dev, char *name)
71 snprintf(name, CNXK_NPA_DEV_NAME_LEN, CNXK_NPA_DEV_NAME PCI_PRI_FMT,
72 pci_dev->addr.domain, pci_dev->addr.bus, pci_dev->addr.devid,
73 pci_dev->addr.function);
79 npa_init(struct rte_pci_device *pci_dev)
81 char name[CNXK_NPA_DEV_NAME_LEN];
82 const struct rte_memzone *mz;
86 mz = rte_memzone_reserve_aligned(npa_dev_to_name(pci_dev, name),
87 sizeof(*dev), SOCKET_ID_ANY, 0,
93 dev->pci_dev = pci_dev;
95 roc_idev_npa_maxpools_set(parse_max_pools(pci_dev->device.devargs));
96 rc = roc_npa_dev_init(dev);
103 rte_memzone_free(mz);
105 plt_err("failed to initialize npa device rc=%d", rc);
110 npa_fini(struct rte_pci_device *pci_dev)
112 char name[CNXK_NPA_DEV_NAME_LEN];
113 const struct rte_memzone *mz;
116 mz = rte_memzone_lookup(npa_dev_to_name(pci_dev, name));
120 rc = roc_npa_dev_fini(mz->addr);
123 plt_err("Failed to remove npa dev, rc=%d", rc);
126 rte_memzone_free(mz);
132 npa_remove(struct rte_pci_device *pci_dev)
134 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
137 return npa_fini(pci_dev);
141 npa_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
145 RTE_SET_USED(pci_drv);
151 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
154 return npa_init(pci_dev);
157 static const struct rte_pci_id npa_pci_map[] = {
159 .class_id = RTE_CLASS_ANY_ID,
160 .vendor_id = PCI_VENDOR_ID_CAVIUM,
161 .device_id = PCI_DEVID_CNXK_RVU_NPA_PF,
162 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
163 .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KA,
166 .class_id = RTE_CLASS_ANY_ID,
167 .vendor_id = PCI_VENDOR_ID_CAVIUM,
168 .device_id = PCI_DEVID_CNXK_RVU_NPA_PF,
169 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
170 .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KAS,
173 .class_id = RTE_CLASS_ANY_ID,
174 .vendor_id = PCI_VENDOR_ID_CAVIUM,
175 .device_id = PCI_DEVID_CNXK_RVU_NPA_PF,
176 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
177 .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CNF10KA,
180 .class_id = RTE_CLASS_ANY_ID,
181 .vendor_id = PCI_VENDOR_ID_CAVIUM,
182 .device_id = PCI_DEVID_CNXK_RVU_NPA_VF,
183 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
184 .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KA,
187 .class_id = RTE_CLASS_ANY_ID,
188 .vendor_id = PCI_VENDOR_ID_CAVIUM,
189 .device_id = PCI_DEVID_CNXK_RVU_NPA_VF,
190 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
191 .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KAS,
194 .class_id = RTE_CLASS_ANY_ID,
195 .vendor_id = PCI_VENDOR_ID_CAVIUM,
196 .device_id = PCI_DEVID_CNXK_RVU_NPA_VF,
197 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
198 .subsystem_device_id = PCI_SUBSYSTEM_DEVID_CNF10KA,
205 static struct rte_pci_driver npa_pci = {
206 .id_table = npa_pci_map,
207 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
209 .remove = npa_remove,
212 RTE_PMD_REGISTER_PCI(mempool_cnxk, npa_pci);
213 RTE_PMD_REGISTER_PCI_TABLE(mempool_cnxk, npa_pci_map);
214 RTE_PMD_REGISTER_KMOD_DEP(mempool_cnxk, "vfio-pci");
215 RTE_PMD_REGISTER_PARAM_STRING(mempool_cnxk,
216 CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>");