1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Cavium, Inc
14 #include <rte_atomic.h>
16 #include <rte_bus_pci.h>
17 #include <rte_errno.h>
18 #include <rte_memory.h>
19 #include <rte_malloc.h>
20 #include <rte_spinlock.h>
23 #include "octeontx_mbox.h"
24 #include "octeontx_fpavf.h"
26 /* FPA Mbox Message */
29 #define FPA_CONFIGSET 0x1
30 #define FPA_CONFIGGET 0x2
31 #define FPA_START_COUNT 0x3
32 #define FPA_STOP_COUNT 0x4
33 #define FPA_ATTACHAURA 0x5
34 #define FPA_DETACHAURA 0x6
35 #define FPA_SETAURALVL 0x7
36 #define FPA_GETAURALVL 0x8
38 #define FPA_COPROC 0x1
41 struct octeontx_mbox_fpa_cfg {
44 uint64_t pool_stack_base;
45 uint64_t pool_stack_end;
49 struct __rte_packed gen_req {
53 struct __rte_packed idn_req {
57 struct __rte_packed gen_resp {
62 struct __rte_packed dcfg_resp {
68 uint8_t net_port_count;
69 uint8_t virt_port_count;
72 #define FPA_MAX_POOL 32
73 #define FPA_PF_PAGE_SZ 4096
75 #define FPA_LN_SIZE 128
76 #define FPA_ROUND_UP(x, size) \
77 ((((unsigned long)(x)) + size-1) & (~(size-1)))
78 #define FPA_OBJSZ_2_CACHE_LINE(sz) (((sz) + RTE_CACHE_LINE_MASK) >> 7)
79 #define FPA_CACHE_LINE_2_OBJSZ(sz) ((sz) << 7)
81 #define POOL_ENA (0x1 << 0)
82 #define POOL_DIS (0x0 << 0)
83 #define POOL_SET_NAT_ALIGN (0x1 << 1)
84 #define POOL_DIS_NAT_ALIGN (0x0 << 1)
85 #define POOL_STYPE(x) (((x) & 0x1) << 2)
86 #define POOL_LTYPE(x) (((x) & 0x3) << 3)
87 #define POOL_BUF_OFFSET(x) (((x) & 0x7fffULL) << 16)
88 #define POOL_BUF_SIZE(x) (((x) & 0x7ffULL) << 32)
91 void *pool_stack_base;
93 uint64_t stack_ln_ptr;
95 uint16_t vf_id; /* gpool_id */
96 uint16_t sz128; /* Block size in cache lines */
100 struct octeontx_fpadev {
102 uint8_t total_gpool_cnt;
103 struct fpavf_res pool[FPA_VF_MAX];
106 static struct octeontx_fpadev fpadev;
108 RTE_LOG_REGISTER(octeontx_logtype_fpavf, pmd.mempool.octeontx, NOTICE);
110 /* lock is taken by caller */
112 octeontx_fpa_gpool_alloc(unsigned int object_size)
114 uint16_t global_domain = octeontx_get_global_domain();
115 struct fpavf_res *res = NULL;
119 sz128 = FPA_OBJSZ_2_CACHE_LINE(object_size);
121 for (i = 0; i < FPA_VF_MAX; i++) {
123 /* Skip VF that is not mapped Or _inuse */
124 if ((fpadev.pool[i].bar0 == NULL) ||
125 (fpadev.pool[i].is_inuse == true) ||
126 (fpadev.pool[i].domain_id != global_domain))
129 res = &fpadev.pool[i];
131 RTE_ASSERT(res->domain_id != (uint16_t)~0);
132 RTE_ASSERT(res->vf_id != (uint16_t)~0);
133 RTE_ASSERT(res->stack_ln_ptr != 0);
135 if (res->sz128 == 0) {
137 fpavf_log_dbg("gpool %d blk_sz %d\n", res->vf_id,
147 static __rte_always_inline struct fpavf_res *
148 octeontx_get_fpavf(uint16_t gpool)
150 uint16_t global_domain = octeontx_get_global_domain();
153 for (i = 0; i < FPA_VF_MAX; i++) {
154 if (fpadev.pool[i].domain_id != global_domain)
156 if (fpadev.pool[i].vf_id != gpool)
159 return &fpadev.pool[i];
165 /* lock is taken by caller */
166 static __rte_always_inline uintptr_t
167 octeontx_fpa_gpool2handle(uint16_t gpool)
169 struct fpavf_res *res = NULL;
171 RTE_ASSERT(gpool < FPA_VF_MAX);
172 res = octeontx_get_fpavf(gpool);
176 return (uintptr_t)res->bar0 | gpool;
179 static __rte_always_inline bool
180 octeontx_fpa_handle_valid(uintptr_t handle)
182 struct fpavf_res *res = NULL;
187 if (unlikely(!handle))
191 gpool = octeontx_fpa_bufpool_gpool(handle);
193 /* get the bar address */
194 handle &= ~(uint64_t)FPA_GPOOL_MASK;
195 for (i = 0; i < FPA_VF_MAX; i++) {
196 if ((uintptr_t)fpadev.pool[i].bar0 != handle)
200 if (gpool != fpadev.pool[i].vf_id)
203 res = &fpadev.pool[i];
205 if (res->sz128 == 0 || res->domain_id == (uint16_t)~0 ||
206 res->stack_ln_ptr == 0)
217 octeontx_fpapf_pool_setup(unsigned int gpool, unsigned int buf_size,
218 signed short buf_offset, unsigned int max_buf_count)
221 rte_iova_t phys_addr;
223 struct fpavf_res *fpa = NULL;
225 struct octeontx_mbox_hdr hdr;
226 struct dcfg_resp resp;
227 struct octeontx_mbox_fpa_cfg cfg;
230 fpa = octeontx_get_fpavf(gpool);
234 memsz = FPA_ROUND_UP(max_buf_count / fpa->stack_ln_ptr, FPA_LN_SIZE) *
237 /* Round-up to page size */
238 memsz = (memsz + FPA_PF_PAGE_SZ - 1) & ~(uintptr_t)(FPA_PF_PAGE_SZ-1);
239 memptr = rte_malloc(NULL, memsz, RTE_CACHE_LINE_SIZE);
240 if (memptr == NULL) {
245 /* Configure stack */
246 fpa->pool_stack_base = memptr;
247 phys_addr = rte_malloc_virt2iova(memptr);
249 buf_size /= FPA_LN_SIZE;
252 hdr.coproc = FPA_COPROC;
253 hdr.msg = FPA_CONFIGSET;
254 hdr.vfid = fpa->vf_id;
257 buf_offset /= FPA_LN_SIZE;
258 reg = POOL_BUF_SIZE(buf_size) | POOL_BUF_OFFSET(buf_offset) |
259 POOL_LTYPE(0x2) | POOL_STYPE(0) | POOL_SET_NAT_ALIGN |
262 cfg.aid = FPA_AURA_IDX(gpool);
264 cfg.pool_stack_base = phys_addr;
265 cfg.pool_stack_end = phys_addr + memsz;
266 cfg.aura_cfg = (1 << 9);
268 ret = octeontx_mbox_send(&hdr, &cfg,
269 sizeof(struct octeontx_mbox_fpa_cfg),
270 &resp, sizeof(resp));
276 fpavf_log_dbg(" vfid %d gpool %d aid %d pool_cfg 0x%x pool_stack_base %" PRIx64 " pool_stack_end %" PRIx64" aura_cfg %" PRIx64 "\n",
277 fpa->vf_id, gpool, cfg.aid, (unsigned int)cfg.pool_cfg,
278 cfg.pool_stack_base, cfg.pool_stack_end, cfg.aura_cfg);
280 /* Now pool is in_use */
281 fpa->is_inuse = true;
291 octeontx_fpapf_pool_destroy(unsigned int gpool_index)
293 struct octeontx_mbox_hdr hdr;
294 struct dcfg_resp resp;
295 struct octeontx_mbox_fpa_cfg cfg;
296 struct fpavf_res *fpa = NULL;
299 fpa = octeontx_get_fpavf(gpool_index);
303 hdr.coproc = FPA_COPROC;
304 hdr.msg = FPA_CONFIGSET;
305 hdr.vfid = fpa->vf_id;
308 /* reset and free the pool */
311 cfg.pool_stack_base = 0;
312 cfg.pool_stack_end = 0;
315 ret = octeontx_mbox_send(&hdr, &cfg,
316 sizeof(struct octeontx_mbox_fpa_cfg),
317 &resp, sizeof(resp));
325 /* anycase free pool stack memory */
326 rte_free(fpa->pool_stack_base);
327 fpa->pool_stack_base = NULL;
332 octeontx_fpapf_aura_attach(unsigned int gpool_index)
334 struct octeontx_mbox_hdr hdr;
335 struct dcfg_resp resp;
336 struct octeontx_mbox_fpa_cfg cfg;
339 if (gpool_index >= FPA_MAX_POOL) {
343 hdr.coproc = FPA_COPROC;
344 hdr.msg = FPA_ATTACHAURA;
345 hdr.vfid = gpool_index;
347 memset(&cfg, 0x0, sizeof(struct octeontx_mbox_fpa_cfg));
348 cfg.aid = FPA_AURA_IDX(gpool_index);
350 ret = octeontx_mbox_send(&hdr, &cfg,
351 sizeof(struct octeontx_mbox_fpa_cfg),
352 &resp, sizeof(resp));
354 fpavf_log_err("Could not attach fpa ");
355 fpavf_log_err("aura %d to pool %d. Err=%d. FuncErr=%d\n",
356 FPA_AURA_IDX(gpool_index), gpool_index, ret,
366 octeontx_fpapf_aura_detach(unsigned int gpool_index)
368 struct octeontx_mbox_fpa_cfg cfg = {0};
369 struct octeontx_mbox_hdr hdr = {0};
372 if (gpool_index >= FPA_MAX_POOL) {
377 cfg.aid = FPA_AURA_IDX(gpool_index);
378 hdr.coproc = FPA_COPROC;
379 hdr.msg = FPA_DETACHAURA;
380 hdr.vfid = gpool_index;
381 ret = octeontx_mbox_send(&hdr, &cfg, sizeof(cfg), NULL, 0);
383 fpavf_log_err("Couldn't detach FPA aura %d Err=%d FuncErr=%d\n",
384 FPA_AURA_IDX(gpool_index), ret,
394 octeontx_fpavf_pool_set_range(uintptr_t handle, unsigned long memsz,
395 void *memva, uint16_t gpool)
399 if (unlikely(!handle))
402 va_end = (uintptr_t)memva + memsz;
403 va_end &= ~RTE_CACHE_LINE_MASK;
406 fpavf_write64((uintptr_t)memva,
407 (void *)((uintptr_t)handle +
408 FPA_VF_VHPOOL_START_ADDR(gpool)));
409 fpavf_write64(va_end,
410 (void *)((uintptr_t)handle +
411 FPA_VF_VHPOOL_END_ADDR(gpool)));
416 octeontx_fpapf_start_count(uint16_t gpool_index)
419 struct octeontx_mbox_hdr hdr = {0};
421 if (gpool_index >= FPA_MAX_POOL) {
426 hdr.coproc = FPA_COPROC;
427 hdr.msg = FPA_START_COUNT;
428 hdr.vfid = gpool_index;
429 ret = octeontx_mbox_send(&hdr, NULL, 0, NULL, 0);
431 fpavf_log_err("Could not start buffer counting for ");
432 fpavf_log_err("FPA pool %d. Err=%d. FuncErr=%d\n",
433 gpool_index, ret, hdr.res_code);
442 static __rte_always_inline int
443 octeontx_fpavf_free(unsigned int gpool)
445 struct fpavf_res *res = octeontx_get_fpavf(gpool);
448 if (gpool >= FPA_MAX_POOL) {
455 res->is_inuse = false;
461 static __rte_always_inline int
462 octeontx_gpool_free(uint16_t gpool)
464 struct fpavf_res *res = octeontx_get_fpavf(gpool);
466 if (res && res->sz128 != 0) {
474 * Return buffer size for a given pool
477 octeontx_fpa_bufpool_block_size(uintptr_t handle)
479 struct fpavf_res *res = NULL;
482 if (unlikely(!octeontx_fpa_handle_valid(handle)))
486 gpool = octeontx_fpa_bufpool_gpool(handle);
487 res = octeontx_get_fpavf(gpool);
488 return res ? FPA_CACHE_LINE_2_OBJSZ(res->sz128) : 0;
492 octeontx_fpa_bufpool_free_count(uintptr_t handle)
494 uint64_t cnt, limit, avail;
499 if (unlikely(!octeontx_fpa_handle_valid(handle)))
503 gpool = octeontx_fpa_bufpool_gpool(handle);
505 gaura = octeontx_fpa_bufpool_gaura(handle);
507 /* Get pool bar address from handle */
508 pool_bar = handle & ~(uint64_t)FPA_GPOOL_MASK;
510 cnt = fpavf_read64((void *)((uintptr_t)pool_bar +
511 FPA_VF_VHAURA_CNT(gaura)));
512 limit = fpavf_read64((void *)((uintptr_t)pool_bar +
513 FPA_VF_VHAURA_CNT_LIMIT(gaura)));
515 avail = fpavf_read64((void *)((uintptr_t)pool_bar +
516 FPA_VF_VHPOOL_AVAILABLE(gpool)));
518 return RTE_MIN(avail, (limit - cnt));
522 octeontx_fpa_bufpool_create(unsigned int object_size, unsigned int object_count,
523 unsigned int buf_offset, int node_id)
527 uintptr_t gpool_handle;
531 RTE_SET_USED(node_id);
532 RTE_BUILD_BUG_ON(sizeof(struct rte_mbuf) > OCTEONTX_FPAVF_BUF_OFFSET);
534 octeontx_mbox_init();
535 object_size = RTE_CACHE_LINE_ROUNDUP(object_size);
536 if (object_size > FPA_MAX_OBJ_SIZE) {
541 rte_spinlock_lock(&fpadev.lock);
542 res = octeontx_fpa_gpool_alloc(object_size);
545 if (unlikely(res < 0)) {
553 /* get pool handle */
554 gpool_handle = octeontx_fpa_gpool2handle(gpool);
555 if (!octeontx_fpa_handle_valid(gpool_handle)) {
557 goto error_gpool_free;
560 /* Get pool bar address from handle */
561 pool_bar = gpool_handle & ~(uint64_t)FPA_GPOOL_MASK;
563 res = octeontx_fpapf_pool_setup(gpool, object_size, buf_offset,
567 goto error_gpool_free;
570 /* populate AURA fields */
571 res = octeontx_fpapf_aura_attach(gpool);
574 goto error_pool_destroy;
577 gaura = FPA_AURA_IDX(gpool);
580 rte_spinlock_unlock(&fpadev.lock);
582 /* populate AURA registers */
583 fpavf_write64(object_count, (void *)((uintptr_t)pool_bar +
584 FPA_VF_VHAURA_CNT(gaura)));
585 fpavf_write64(object_count, (void *)((uintptr_t)pool_bar +
586 FPA_VF_VHAURA_CNT_LIMIT(gaura)));
587 fpavf_write64(object_count + 1, (void *)((uintptr_t)pool_bar +
588 FPA_VF_VHAURA_CNT_THRESHOLD(gaura)));
590 octeontx_fpapf_start_count(gpool);
595 octeontx_fpavf_free(gpool);
596 octeontx_fpapf_pool_destroy(gpool);
598 octeontx_gpool_free(gpool);
600 rte_spinlock_unlock(&fpadev.lock);
602 return (uintptr_t)NULL;
606 * Destroy a buffer pool.
609 octeontx_fpa_bufpool_destroy(uintptr_t handle, int node_id)
611 void **node, **curr, *head = NULL;
619 RTE_SET_USED(node_id);
621 /* Wait for all outstanding writes to be committed */
624 if (unlikely(!octeontx_fpa_handle_valid(handle)))
628 gpool = octeontx_fpa_bufpool_gpool(handle);
630 gaura = octeontx_fpa_bufpool_gaura(handle);
632 /* Get pool bar address from handle */
633 pool_bar = handle & ~(uint64_t)FPA_GPOOL_MASK;
635 /* Check for no outstanding buffers */
636 cnt = fpavf_read64((void *)((uintptr_t)pool_bar +
637 FPA_VF_VHAURA_CNT(gaura)));
639 fpavf_log_dbg("buffer exist in pool cnt %" PRId64 "\n", cnt);
643 rte_spinlock_lock(&fpadev.lock);
645 avail = fpavf_read64((void *)((uintptr_t)pool_bar +
646 FPA_VF_VHPOOL_AVAILABLE(gpool)));
648 /* Prepare to empty the entire POOL */
649 fpavf_write64(avail, (void *)((uintptr_t)pool_bar +
650 FPA_VF_VHAURA_CNT_LIMIT(gaura)));
651 fpavf_write64(avail + 1, (void *)((uintptr_t)pool_bar +
652 FPA_VF_VHAURA_CNT_THRESHOLD(gaura)));
655 /* Invalidate the POOL */
656 octeontx_gpool_free(gpool);
658 /* Process all buffers in the pool */
661 /* Yank a buffer from the pool */
662 node = (void *)(uintptr_t)
663 fpavf_read64((void *)
664 (pool_bar + FPA_VF_VHAURA_OP_ALLOC(gaura)));
667 fpavf_log_err("GAURA[%u] missing %" PRIx64 " buf\n",
672 /* Imsert it into an ordered linked list */
673 for (curr = &head; curr[0] != NULL; curr = curr[0]) {
674 if ((uintptr_t)node <= (uintptr_t)curr[0])
681 /* Verify the linked list to be a perfect series */
682 sz = octeontx_fpa_bufpool_block_size(handle) << 7;
683 for (curr = head; curr != NULL && curr[0] != NULL;
685 if (curr == curr[0] ||
686 ((uintptr_t)curr != ((uintptr_t)curr[0] - sz))) {
687 fpavf_log_err("POOL# %u buf sequence err (%p vs. %p)\n",
688 gpool, curr, curr[0]);
692 /* Disable pool operation */
693 fpavf_write64(~0ul, (void *)((uintptr_t)pool_bar +
694 FPA_VF_VHPOOL_START_ADDR(gpool)));
695 fpavf_write64(~0ul, (void *)((uintptr_t)pool_bar +
696 FPA_VF_VHPOOL_END_ADDR(gpool)));
698 (void)octeontx_fpapf_pool_destroy(gpool);
700 /* Deactivate the AURA */
701 fpavf_write64(0, (void *)((uintptr_t)pool_bar +
702 FPA_VF_VHAURA_CNT_LIMIT(gaura)));
703 fpavf_write64(0, (void *)((uintptr_t)pool_bar +
704 FPA_VF_VHAURA_CNT_THRESHOLD(gaura)));
706 ret = octeontx_fpapf_aura_detach(gpool);
708 fpavf_log_err("Failed to dettach gaura %u. error code=%d\n",
713 (void)octeontx_fpavf_free(gpool);
715 rte_spinlock_unlock(&fpadev.lock);
720 octeontx_fpavf_setup(void)
723 static bool init_once;
726 rte_spinlock_init(&fpadev.lock);
727 fpadev.total_gpool_cnt = 0;
729 for (i = 0; i < FPA_VF_MAX; i++) {
731 fpadev.pool[i].domain_id = ~0;
732 fpadev.pool[i].stack_ln_ptr = 0;
733 fpadev.pool[i].sz128 = 0;
734 fpadev.pool[i].bar0 = NULL;
735 fpadev.pool[i].pool_stack_base = NULL;
736 fpadev.pool[i].is_inuse = false;
743 octeontx_fpavf_identify(void *bar0)
748 uint64_t stack_ln_ptr;
749 static uint16_t vf_idx;
751 val = fpavf_read64((void *)((uintptr_t)bar0 +
752 FPA_VF_VHAURA_CNT_THRESHOLD(0)));
754 domain_id = (val >> 8) & 0xffff;
755 vf_id = (val >> 24) & 0xffff;
757 stack_ln_ptr = fpavf_read64((void *)((uintptr_t)bar0 +
758 FPA_VF_VHPOOL_THRESHOLD(0)));
759 if (vf_idx >= FPA_VF_MAX) {
760 fpavf_log_err("vf_id(%d) greater than max vf (32)\n", vf_id);
764 fpadev.pool[vf_idx].domain_id = domain_id;
765 fpadev.pool[vf_idx].vf_id = vf_id;
766 fpadev.pool[vf_idx].bar0 = bar0;
767 fpadev.pool[vf_idx].stack_ln_ptr = stack_ln_ptr;
773 /* FPAVF pcie device aka mempool probe */
775 fpavf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
779 struct fpavf_res *fpa = NULL;
781 RTE_SET_USED(pci_drv);
784 /* For secondary processes, the primary has done all the work */
785 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
788 if (pci_dev->mem_resource[0].addr == NULL) {
789 fpavf_log_err("Empty bars %p ", pci_dev->mem_resource[0].addr);
792 idreg = pci_dev->mem_resource[0].addr;
794 octeontx_fpavf_setup();
796 res = octeontx_fpavf_identify(idreg);
800 fpa = &fpadev.pool[res];
801 fpadev.total_gpool_cnt++;
804 fpavf_log_dbg("total_fpavfs %d bar0 %p domain %d vf %d stk_ln_ptr 0x%x",
805 fpadev.total_gpool_cnt, fpa->bar0, fpa->domain_id,
806 fpa->vf_id, (unsigned int)fpa->stack_ln_ptr);
811 static const struct rte_pci_id pci_fpavf_map[] = {
813 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
814 PCI_DEVICE_ID_OCTEONTX_FPA_VF)
821 static struct rte_pci_driver pci_fpavf = {
822 .id_table = pci_fpavf_map,
823 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
824 .probe = fpavf_probe,
827 RTE_PMD_REGISTER_PCI(octeontx_fpavf, pci_fpavf);