1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Cavium, Inc
14 #include <rte_atomic.h>
16 #include <rte_bus_pci.h>
17 #include <rte_errno.h>
18 #include <rte_memory.h>
19 #include <rte_malloc.h>
20 #include <rte_spinlock.h>
23 #include "octeontx_mbox.h"
24 #include "octeontx_fpavf.h"
26 /* FPA Mbox Message */
29 #define FPA_CONFIGSET 0x1
30 #define FPA_CONFIGGET 0x2
31 #define FPA_START_COUNT 0x3
32 #define FPA_STOP_COUNT 0x4
33 #define FPA_ATTACHAURA 0x5
34 #define FPA_DETACHAURA 0x6
35 #define FPA_SETAURALVL 0x7
36 #define FPA_GETAURALVL 0x8
38 #define FPA_COPROC 0x1
41 struct octeontx_mbox_fpa_cfg {
44 uint64_t pool_stack_base;
45 uint64_t pool_stack_end;
49 struct __attribute__((__packed__)) gen_req {
53 struct __attribute__((__packed__)) idn_req {
57 struct __attribute__((__packed__)) gen_resp {
62 struct __attribute__((__packed__)) dcfg_resp {
68 uint8_t net_port_count;
69 uint8_t virt_port_count;
72 #define FPA_MAX_POOL 32
73 #define FPA_PF_PAGE_SZ 4096
75 #define FPA_LN_SIZE 128
76 #define FPA_ROUND_UP(x, size) \
77 ((((unsigned long)(x)) + size-1) & (~(size-1)))
78 #define FPA_OBJSZ_2_CACHE_LINE(sz) (((sz) + RTE_CACHE_LINE_MASK) >> 7)
79 #define FPA_CACHE_LINE_2_OBJSZ(sz) ((sz) << 7)
81 #define POOL_ENA (0x1 << 0)
82 #define POOL_DIS (0x0 << 0)
83 #define POOL_SET_NAT_ALIGN (0x1 << 1)
84 #define POOL_DIS_NAT_ALIGN (0x0 << 1)
85 #define POOL_STYPE(x) (((x) & 0x1) << 2)
86 #define POOL_LTYPE(x) (((x) & 0x3) << 3)
87 #define POOL_BUF_OFFSET(x) (((x) & 0x7fffULL) << 16)
88 #define POOL_BUF_SIZE(x) (((x) & 0x7ffULL) << 32)
91 void *pool_stack_base;
93 uint64_t stack_ln_ptr;
95 uint16_t vf_id; /* gpool_id */
96 uint16_t sz128; /* Block size in cache lines */
100 struct octeontx_fpadev {
102 uint8_t total_gpool_cnt;
103 struct fpavf_res pool[FPA_VF_MAX];
106 static struct octeontx_fpadev fpadev;
108 /* lock is taken by caller */
110 octeontx_fpa_gpool_alloc(unsigned int object_size)
112 struct fpavf_res *res = NULL;
116 sz128 = FPA_OBJSZ_2_CACHE_LINE(object_size);
118 for (gpool = 0; gpool < FPA_VF_MAX; gpool++) {
120 /* Skip VF that is not mapped Or _inuse */
121 if ((fpadev.pool[gpool].bar0 == NULL) ||
122 (fpadev.pool[gpool].is_inuse == true))
125 res = &fpadev.pool[gpool];
127 RTE_ASSERT(res->domain_id != (uint16_t)~0);
128 RTE_ASSERT(res->vf_id != (uint16_t)~0);
129 RTE_ASSERT(res->stack_ln_ptr != 0);
131 if (res->sz128 == 0) {
134 fpavf_log_dbg("gpool %d blk_sz %d\n", gpool, sz128);
142 /* lock is taken by caller */
143 static __rte_always_inline uintptr_t
144 octeontx_fpa_gpool2handle(uint16_t gpool)
146 struct fpavf_res *res = NULL;
148 RTE_ASSERT(gpool < FPA_VF_MAX);
150 res = &fpadev.pool[gpool];
151 return (uintptr_t)res->bar0 | gpool;
154 static __rte_always_inline bool
155 octeontx_fpa_handle_valid(uintptr_t handle)
157 struct fpavf_res *res = NULL;
162 if (unlikely(!handle))
166 gpool = octeontx_fpa_bufpool_gpool(handle);
168 /* get the bar address */
169 handle &= ~(uint64_t)FPA_GPOOL_MASK;
170 for (i = 0; i < FPA_VF_MAX; i++) {
171 if ((uintptr_t)fpadev.pool[i].bar0 != handle)
178 res = &fpadev.pool[i];
180 if (res->sz128 == 0 || res->domain_id == (uint16_t)~0 ||
181 res->stack_ln_ptr == 0)
192 octeontx_fpapf_pool_setup(unsigned int gpool, unsigned int buf_size,
193 signed short buf_offset, unsigned int max_buf_count)
196 rte_iova_t phys_addr;
198 struct fpavf_res *fpa = NULL;
200 struct octeontx_mbox_hdr hdr;
201 struct dcfg_resp resp;
202 struct octeontx_mbox_fpa_cfg cfg;
205 fpa = &fpadev.pool[gpool];
206 memsz = FPA_ROUND_UP(max_buf_count / fpa->stack_ln_ptr, FPA_LN_SIZE) *
209 /* Round-up to page size */
210 memsz = (memsz + FPA_PF_PAGE_SZ - 1) & ~(uintptr_t)(FPA_PF_PAGE_SZ-1);
211 memptr = rte_malloc(NULL, memsz, RTE_CACHE_LINE_SIZE);
212 if (memptr == NULL) {
217 /* Configure stack */
218 fpa->pool_stack_base = memptr;
219 phys_addr = rte_malloc_virt2iova(memptr);
221 buf_size /= FPA_LN_SIZE;
224 hdr.coproc = FPA_COPROC;
225 hdr.msg = FPA_CONFIGSET;
226 hdr.vfid = fpa->vf_id;
229 buf_offset /= FPA_LN_SIZE;
230 reg = POOL_BUF_SIZE(buf_size) | POOL_BUF_OFFSET(buf_offset) |
231 POOL_LTYPE(0x2) | POOL_STYPE(0) | POOL_SET_NAT_ALIGN |
236 cfg.pool_stack_base = phys_addr;
237 cfg.pool_stack_end = phys_addr + memsz;
238 cfg.aura_cfg = (1 << 9);
240 ret = octeontx_ssovf_mbox_send(&hdr, &cfg,
241 sizeof(struct octeontx_mbox_fpa_cfg),
242 &resp, sizeof(resp));
248 fpavf_log_dbg(" vfid %d gpool %d aid %d pool_cfg 0x%x pool_stack_base %" PRIx64 " pool_stack_end %" PRIx64" aura_cfg %" PRIx64 "\n",
249 fpa->vf_id, gpool, cfg.aid, (unsigned int)cfg.pool_cfg,
250 cfg.pool_stack_base, cfg.pool_stack_end, cfg.aura_cfg);
252 /* Now pool is in_use */
253 fpa->is_inuse = true;
263 octeontx_fpapf_pool_destroy(unsigned int gpool_index)
265 struct octeontx_mbox_hdr hdr;
266 struct dcfg_resp resp;
267 struct octeontx_mbox_fpa_cfg cfg;
268 struct fpavf_res *fpa = NULL;
271 fpa = &fpadev.pool[gpool_index];
273 hdr.coproc = FPA_COPROC;
274 hdr.msg = FPA_CONFIGSET;
275 hdr.vfid = fpa->vf_id;
278 /* reset and free the pool */
281 cfg.pool_stack_base = 0;
282 cfg.pool_stack_end = 0;
285 ret = octeontx_ssovf_mbox_send(&hdr, &cfg,
286 sizeof(struct octeontx_mbox_fpa_cfg),
287 &resp, sizeof(resp));
295 /* anycase free pool stack memory */
296 rte_free(fpa->pool_stack_base);
297 fpa->pool_stack_base = NULL;
302 octeontx_fpapf_aura_attach(unsigned int gpool_index)
304 struct octeontx_mbox_hdr hdr;
305 struct dcfg_resp resp;
306 struct octeontx_mbox_fpa_cfg cfg;
309 if (gpool_index >= FPA_MAX_POOL) {
313 hdr.coproc = FPA_COPROC;
314 hdr.msg = FPA_ATTACHAURA;
315 hdr.vfid = gpool_index;
317 memset(&cfg, 0x0, sizeof(struct octeontx_mbox_fpa_cfg));
318 cfg.aid = gpool_index; /* gpool is guara */
320 ret = octeontx_ssovf_mbox_send(&hdr, &cfg,
321 sizeof(struct octeontx_mbox_fpa_cfg),
322 &resp, sizeof(resp));
324 fpavf_log_err("Could not attach fpa ");
325 fpavf_log_err("aura %d to pool %d. Err=%d. FuncErr=%d\n",
326 gpool_index, gpool_index, ret, hdr.res_code);
335 octeontx_fpapf_aura_detach(unsigned int gpool_index)
337 struct octeontx_mbox_fpa_cfg cfg = {0};
338 struct octeontx_mbox_hdr hdr = {0};
341 if (gpool_index >= FPA_MAX_POOL) {
346 cfg.aid = gpool_index; /* gpool is gaura */
347 hdr.coproc = FPA_COPROC;
348 hdr.msg = FPA_DETACHAURA;
349 hdr.vfid = gpool_index;
350 ret = octeontx_ssovf_mbox_send(&hdr, &cfg, sizeof(cfg), NULL, 0);
352 fpavf_log_err("Couldn't detach FPA aura %d Err=%d FuncErr=%d\n",
353 gpool_index, ret, hdr.res_code);
362 octeontx_fpavf_pool_set_range(uintptr_t handle, unsigned long memsz,
363 void *memva, uint16_t gpool)
367 if (unlikely(!handle))
370 va_end = (uintptr_t)memva + memsz;
371 va_end &= ~RTE_CACHE_LINE_MASK;
374 fpavf_write64((uintptr_t)memva,
375 (void *)((uintptr_t)handle +
376 FPA_VF_VHPOOL_START_ADDR(gpool)));
377 fpavf_write64(va_end,
378 (void *)((uintptr_t)handle +
379 FPA_VF_VHPOOL_END_ADDR(gpool)));
384 octeontx_fpapf_start_count(uint16_t gpool_index)
387 struct octeontx_mbox_hdr hdr = {0};
389 if (gpool_index >= FPA_MAX_POOL) {
394 hdr.coproc = FPA_COPROC;
395 hdr.msg = FPA_START_COUNT;
396 hdr.vfid = gpool_index;
397 ret = octeontx_ssovf_mbox_send(&hdr, NULL, 0, NULL, 0);
399 fpavf_log_err("Could not start buffer counting for ");
400 fpavf_log_err("FPA pool %d. Err=%d. FuncErr=%d\n",
401 gpool_index, ret, hdr.res_code);
410 static __rte_always_inline int
411 octeontx_fpavf_free(unsigned int gpool)
415 if (gpool >= FPA_MAX_POOL) {
421 fpadev.pool[gpool].is_inuse = false;
427 static __rte_always_inline int
428 octeontx_gpool_free(uint16_t gpool)
430 if (fpadev.pool[gpool].sz128 != 0) {
431 fpadev.pool[gpool].sz128 = 0;
438 * Return buffer size for a given pool
441 octeontx_fpa_bufpool_block_size(uintptr_t handle)
443 struct fpavf_res *res = NULL;
446 if (unlikely(!octeontx_fpa_handle_valid(handle)))
450 gpool = octeontx_fpa_bufpool_gpool(handle);
451 res = &fpadev.pool[gpool];
452 return FPA_CACHE_LINE_2_OBJSZ(res->sz128);
456 octeontx_fpa_bufpool_free_count(uintptr_t handle)
458 uint64_t cnt, limit, avail;
462 if (unlikely(!octeontx_fpa_handle_valid(handle)))
466 gpool = octeontx_fpa_bufpool_gpool(handle);
468 /* Get pool bar address from handle */
469 pool_bar = handle & ~(uint64_t)FPA_GPOOL_MASK;
471 cnt = fpavf_read64((void *)((uintptr_t)pool_bar +
472 FPA_VF_VHAURA_CNT(gpool)));
473 limit = fpavf_read64((void *)((uintptr_t)pool_bar +
474 FPA_VF_VHAURA_CNT_LIMIT(gpool)));
476 avail = fpavf_read64((void *)((uintptr_t)pool_bar +
477 FPA_VF_VHPOOL_AVAILABLE(gpool)));
479 return RTE_MIN(avail, (limit - cnt));
483 octeontx_fpa_bufpool_create(unsigned int object_size, unsigned int object_count,
484 unsigned int buf_offset, int node_id)
487 uintptr_t gpool_handle;
491 RTE_SET_USED(node_id);
492 RTE_BUILD_BUG_ON(sizeof(struct rte_mbuf) > OCTEONTX_FPAVF_BUF_OFFSET);
494 object_size = RTE_CACHE_LINE_ROUNDUP(object_size);
495 if (object_size > FPA_MAX_OBJ_SIZE) {
500 rte_spinlock_lock(&fpadev.lock);
501 res = octeontx_fpa_gpool_alloc(object_size);
504 if (unlikely(res < 0)) {
512 /* get pool handle */
513 gpool_handle = octeontx_fpa_gpool2handle(gpool);
514 if (!octeontx_fpa_handle_valid(gpool_handle)) {
516 goto error_gpool_free;
519 /* Get pool bar address from handle */
520 pool_bar = gpool_handle & ~(uint64_t)FPA_GPOOL_MASK;
522 res = octeontx_fpapf_pool_setup(gpool, object_size, buf_offset,
526 goto error_gpool_free;
529 /* populate AURA fields */
530 res = octeontx_fpapf_aura_attach(gpool);
533 goto error_pool_destroy;
537 rte_spinlock_unlock(&fpadev.lock);
539 /* populate AURA registers */
540 fpavf_write64(object_count, (void *)((uintptr_t)pool_bar +
541 FPA_VF_VHAURA_CNT(gpool)));
542 fpavf_write64(object_count, (void *)((uintptr_t)pool_bar +
543 FPA_VF_VHAURA_CNT_LIMIT(gpool)));
544 fpavf_write64(object_count + 1, (void *)((uintptr_t)pool_bar +
545 FPA_VF_VHAURA_CNT_THRESHOLD(gpool)));
547 octeontx_fpapf_start_count(gpool);
552 octeontx_fpavf_free(gpool);
553 octeontx_fpapf_pool_destroy(gpool);
555 octeontx_gpool_free(gpool);
557 rte_spinlock_unlock(&fpadev.lock);
559 return (uintptr_t)NULL;
563 * Destroy a buffer pool.
566 octeontx_fpa_bufpool_destroy(uintptr_t handle, int node_id)
568 void **node, **curr, *head = NULL;
575 RTE_SET_USED(node_id);
577 /* Wait for all outstanding writes to be committed */
580 if (unlikely(!octeontx_fpa_handle_valid(handle)))
584 gpool = octeontx_fpa_bufpool_gpool(handle);
586 /* Get pool bar address from handle */
587 pool_bar = handle & ~(uint64_t)FPA_GPOOL_MASK;
589 /* Check for no outstanding buffers */
590 cnt = fpavf_read64((void *)((uintptr_t)pool_bar +
591 FPA_VF_VHAURA_CNT(gpool)));
593 fpavf_log_dbg("buffer exist in pool cnt %" PRId64 "\n", cnt);
597 rte_spinlock_lock(&fpadev.lock);
599 avail = fpavf_read64((void *)((uintptr_t)pool_bar +
600 FPA_VF_VHPOOL_AVAILABLE(gpool)));
602 /* Prepare to empty the entire POOL */
603 fpavf_write64(avail, (void *)((uintptr_t)pool_bar +
604 FPA_VF_VHAURA_CNT_LIMIT(gpool)));
605 fpavf_write64(avail + 1, (void *)((uintptr_t)pool_bar +
606 FPA_VF_VHAURA_CNT_THRESHOLD(gpool)));
609 /* Invalidate the POOL */
610 octeontx_gpool_free(gpool);
612 /* Process all buffers in the pool */
615 /* Yank a buffer from the pool */
616 node = (void *)(uintptr_t)
617 fpavf_read64((void *)
618 (pool_bar + FPA_VF_VHAURA_OP_ALLOC(gpool)));
621 fpavf_log_err("GAURA[%u] missing %" PRIx64 " buf\n",
626 /* Imsert it into an ordered linked list */
627 for (curr = &head; curr[0] != NULL; curr = curr[0]) {
628 if ((uintptr_t)node <= (uintptr_t)curr[0])
635 /* Verify the linked list to be a perfect series */
636 sz = octeontx_fpa_bufpool_block_size(handle) << 7;
637 for (curr = head; curr != NULL && curr[0] != NULL;
639 if (curr == curr[0] ||
640 ((uintptr_t)curr != ((uintptr_t)curr[0] - sz))) {
641 fpavf_log_err("POOL# %u buf sequence err (%p vs. %p)\n",
642 gpool, curr, curr[0]);
646 /* Disable pool operation */
647 fpavf_write64(~0ul, (void *)((uintptr_t)pool_bar +
648 FPA_VF_VHPOOL_START_ADDR(gpool)));
649 fpavf_write64(~0ul, (void *)((uintptr_t)pool_bar +
650 FPA_VF_VHPOOL_END_ADDR(gpool)));
652 (void)octeontx_fpapf_pool_destroy(gpool);
654 /* Deactivate the AURA */
655 fpavf_write64(0, (void *)((uintptr_t)pool_bar +
656 FPA_VF_VHAURA_CNT_LIMIT(gpool)));
657 fpavf_write64(0, (void *)((uintptr_t)pool_bar +
658 FPA_VF_VHAURA_CNT_THRESHOLD(gpool)));
660 ret = octeontx_fpapf_aura_detach(gpool);
662 fpavf_log_err("Failed to dettach gaura %u. error code=%d\n",
667 (void)octeontx_fpavf_free(gpool);
669 rte_spinlock_unlock(&fpadev.lock);
674 octeontx_fpavf_setup(void)
677 static bool init_once;
680 rte_spinlock_init(&fpadev.lock);
681 fpadev.total_gpool_cnt = 0;
683 for (i = 0; i < FPA_VF_MAX; i++) {
685 fpadev.pool[i].domain_id = ~0;
686 fpadev.pool[i].stack_ln_ptr = 0;
687 fpadev.pool[i].sz128 = 0;
688 fpadev.pool[i].bar0 = NULL;
689 fpadev.pool[i].pool_stack_base = NULL;
690 fpadev.pool[i].is_inuse = false;
697 octeontx_fpavf_identify(void *bar0)
702 uint64_t stack_ln_ptr;
704 val = fpavf_read64((void *)((uintptr_t)bar0 +
705 FPA_VF_VHAURA_CNT_THRESHOLD(0)));
707 domain_id = (val >> 8) & 0xffff;
708 vf_id = (val >> 24) & 0xffff;
710 stack_ln_ptr = fpavf_read64((void *)((uintptr_t)bar0 +
711 FPA_VF_VHPOOL_THRESHOLD(0)));
712 if (vf_id >= FPA_VF_MAX) {
713 fpavf_log_err("vf_id(%d) greater than max vf (32)\n", vf_id);
717 if (fpadev.pool[vf_id].is_inuse) {
718 fpavf_log_err("vf_id %d is_inuse\n", vf_id);
722 fpadev.pool[vf_id].domain_id = domain_id;
723 fpadev.pool[vf_id].vf_id = vf_id;
724 fpadev.pool[vf_id].bar0 = bar0;
725 fpadev.pool[vf_id].stack_ln_ptr = stack_ln_ptr;
731 /* FPAVF pcie device aka mempool probe */
733 fpavf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
737 struct fpavf_res *fpa = NULL;
739 RTE_SET_USED(pci_drv);
742 /* For secondary processes, the primary has done all the work */
743 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
746 if (pci_dev->mem_resource[0].addr == NULL) {
747 fpavf_log_err("Empty bars %p ", pci_dev->mem_resource[0].addr);
750 idreg = pci_dev->mem_resource[0].addr;
752 octeontx_fpavf_setup();
754 res = octeontx_fpavf_identify(idreg);
758 fpa = &fpadev.pool[res];
759 fpadev.total_gpool_cnt++;
762 fpavf_log_dbg("total_fpavfs %d bar0 %p domain %d vf %d stk_ln_ptr 0x%x",
763 fpadev.total_gpool_cnt, fpa->bar0, fpa->domain_id,
764 fpa->vf_id, (unsigned int)fpa->stack_ln_ptr);
769 static const struct rte_pci_id pci_fpavf_map[] = {
771 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
772 PCI_DEVICE_ID_OCTEONTX_FPA_VF)
779 static struct rte_pci_driver pci_fpavf = {
780 .id_table = pci_fpavf_map,
781 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
782 .probe = fpavf_probe,
785 RTE_PMD_REGISTER_PCI(octeontx_fpavf, pci_fpavf);