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33 #ifndef __OCTEONTX_FPAVF_H__
34 #define __OCTEONTX_FPAVF_H__
36 /* fpa pool Vendor ID and Device ID */
37 #define PCI_VENDOR_ID_CAVIUM 0x177D
38 #define PCI_DEVICE_ID_OCTEONTX_FPA_VF 0xA053
42 /* FPA VF register offsets */
43 #define FPA_VF_INT(x) (0x200ULL | ((x) << 22))
44 #define FPA_VF_INT_W1S(x) (0x210ULL | ((x) << 22))
45 #define FPA_VF_INT_ENA_W1S(x) (0x220ULL | ((x) << 22))
46 #define FPA_VF_INT_ENA_W1C(x) (0x230ULL | ((x) << 22))
48 #define FPA_VF_VHPOOL_AVAILABLE(vhpool) (0x04150 | ((vhpool)&0x0))
49 #define FPA_VF_VHPOOL_THRESHOLD(vhpool) (0x04160 | ((vhpool)&0x0))
50 #define FPA_VF_VHPOOL_START_ADDR(vhpool) (0x04200 | ((vhpool)&0x0))
51 #define FPA_VF_VHPOOL_END_ADDR(vhpool) (0x04210 | ((vhpool)&0x0))
53 #define FPA_VF_VHAURA_CNT(vaura) (0x20120 | ((vaura)&0xf)<<18)
54 #define FPA_VF_VHAURA_CNT_ADD(vaura) (0x20128 | ((vaura)&0xf)<<18)
55 #define FPA_VF_VHAURA_CNT_LIMIT(vaura) (0x20130 | ((vaura)&0xf)<<18)
56 #define FPA_VF_VHAURA_CNT_THRESHOLD(vaura) (0x20140 | ((vaura)&0xf)<<18)
57 #define FPA_VF_VHAURA_OP_ALLOC(vaura) (0x30000 | ((vaura)&0xf)<<18)
58 #define FPA_VF_VHAURA_OP_FREE(vaura) (0x38000 | ((vaura)&0xf)<<18)
60 #define FPA_VF_FREE_ADDRS_S(x, y, z) \
61 ((x) | (((y) & 0x1ff) << 3) | ((((z) & 1)) << 14))
63 /* FPA VF register offsets from VF_BAR4, size 2 MByte */
64 #define FPA_VF_MSIX_VEC_ADDR 0x00000
65 #define FPA_VF_MSIX_VEC_CTL 0x00008
66 #define FPA_VF_MSIX_PBA 0xF0000
68 #define FPA_VF0_APERTURE_SHIFT 22
69 #define FPA_AURA_SET_SIZE 16
71 #endif /* __OCTEONTX_FPAVF_H__ */