4 * Copyright (C) Cavium, Inc. 2017.
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14 * the documentation and/or other materials provided with the
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33 #include <rte_atomic.h>
34 #include <rte_common.h>
38 #include <rte_bus_pci.h>
40 #include "octeontx_mbox.h"
41 #include "octeontx_pool_logs.h"
43 #define PCI_VENDOR_ID_CAVIUM 0x177D
44 #define PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF 0xA04B
45 #define PCI_DEVICE_ID_OCTEONTX_SSOWS_VF 0xA04D
47 #define SSO_MAX_VHGRP (64)
48 #define SSO_MAX_VHWS (32)
50 #define SSO_VHGRP_AQ_THR (0x1E0ULL)
67 struct ssowvf_identify {
74 uint8_t total_ssowvfs;
75 struct ssovf_res grp[SSO_MAX_VHGRP];
76 struct ssowvf_res hws[SSO_MAX_VHWS];
79 static struct ssodev sdev;
81 /* Interface functions */
83 octeontx_ssovf_info(struct octeontx_ssovf_info *info)
88 if (rte_eal_process_type() != RTE_PROC_PRIMARY || info == NULL)
91 if (sdev.total_ssovfs == 0 || sdev.total_ssowvfs == 0)
94 domain = sdev.grp[0].domain;
95 for (i = 0; i < sdev.total_ssovfs; i++) {
96 /* Check vfid's are contiguous and belong to same domain */
97 if (sdev.grp[i].vfid != i ||
98 sdev.grp[i].bar0 == NULL ||
99 sdev.grp[i].domain != domain) {
100 mbox_log_err("GRP error, vfid=%d/%d domain=%d/%d %p",
102 domain, sdev.grp[i].domain,
108 for (i = 0; i < sdev.total_ssowvfs; i++) {
109 /* Check vfid's are contiguous and belong to same domain */
110 if (sdev.hws[i].vfid != i ||
111 sdev.hws[i].bar0 == NULL ||
112 sdev.hws[i].domain != domain) {
113 mbox_log_err("HWS error, vfid=%d/%d domain=%d/%d %p",
115 domain, sdev.hws[i].domain,
121 info->domain = domain;
122 info->total_ssovfs = sdev.total_ssovfs;
123 info->total_ssowvfs = sdev.total_ssowvfs;
128 octeontx_ssovf_bar(enum octeontx_ssovf_type type, uint8_t id, uint8_t bar)
130 if (rte_eal_process_type() != RTE_PROC_PRIMARY ||
131 type > OCTEONTX_SSO_HWS)
134 if (type == OCTEONTX_SSO_GROUP) {
135 if (id >= sdev.total_ssovfs)
138 if (id >= sdev.total_ssowvfs)
142 if (type == OCTEONTX_SSO_GROUP) {
145 return sdev.grp[id].bar0;
147 return sdev.grp[id].bar2;
154 return sdev.hws[id].bar0;
156 return sdev.hws[id].bar2;
158 return sdev.hws[id].bar4;
165 /* SSOWVF pcie device aka event port probe */
168 ssowvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
171 struct ssowvf_res *res;
172 struct ssowvf_identify *id;
174 RTE_SET_USED(pci_drv);
176 /* For secondary processes, the primary has done all the work */
177 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
180 if (pci_dev->mem_resource[0].addr == NULL ||
181 pci_dev->mem_resource[2].addr == NULL ||
182 pci_dev->mem_resource[4].addr == NULL) {
183 mbox_log_err("Empty bars %p %p %p",
184 pci_dev->mem_resource[0].addr,
185 pci_dev->mem_resource[2].addr,
186 pci_dev->mem_resource[4].addr);
190 if (pci_dev->mem_resource[4].len != SSOW_BAR4_LEN) {
191 mbox_log_err("Bar4 len mismatch %d != %d",
192 SSOW_BAR4_LEN, (int)pci_dev->mem_resource[4].len);
196 id = pci_dev->mem_resource[4].addr;
198 if (vfid >= SSO_MAX_VHWS) {
199 mbox_log_err("Invalid vfid(%d/%d)", vfid, SSO_MAX_VHWS);
203 res = &sdev.hws[vfid];
205 res->bar0 = pci_dev->mem_resource[0].addr;
206 res->bar2 = pci_dev->mem_resource[2].addr;
207 res->bar4 = pci_dev->mem_resource[4].addr;
208 res->domain = id->domain;
210 sdev.total_ssowvfs++;
212 mbox_log_dbg("Domain=%d hws=%d total_ssowvfs=%d", res->domain,
213 res->vfid, sdev.total_ssowvfs);
217 static const struct rte_pci_id pci_ssowvf_map[] = {
219 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
220 PCI_DEVICE_ID_OCTEONTX_SSOWS_VF)
227 static struct rte_pci_driver pci_ssowvf = {
228 .id_table = pci_ssowvf_map,
229 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
230 .probe = ssowvf_probe,
233 RTE_PMD_REGISTER_PCI(octeontx_ssowvf, pci_ssowvf);
235 /* SSOVF pcie device aka event queue probe */
238 ssovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
243 struct ssovf_res *res;
245 RTE_SET_USED(pci_drv);
247 /* For secondary processes, the primary has done all the work */
248 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
251 if (pci_dev->mem_resource[0].addr == NULL ||
252 pci_dev->mem_resource[2].addr == NULL) {
253 mbox_log_err("Empty bars %p %p",
254 pci_dev->mem_resource[0].addr,
255 pci_dev->mem_resource[2].addr);
258 idreg = pci_dev->mem_resource[0].addr;
259 idreg += SSO_VHGRP_AQ_THR;
260 val = rte_read64(idreg);
262 /* Write back the default value of aq_thr */
263 rte_write64((1ULL << 33) - 1, idreg);
264 vfid = (val >> 16) & 0xffff;
265 if (vfid >= SSO_MAX_VHGRP) {
266 mbox_log_err("Invalid vfid (%d/%d)", vfid, SSO_MAX_VHGRP);
270 res = &sdev.grp[vfid];
272 res->bar0 = pci_dev->mem_resource[0].addr;
273 res->bar2 = pci_dev->mem_resource[2].addr;
274 res->domain = val & 0xffff;
278 mbox_log_dbg("Domain=%d group=%d total_ssovfs=%d", res->domain,
279 res->vfid, sdev.total_ssovfs);
283 static const struct rte_pci_id pci_ssovf_map[] = {
285 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
286 PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF)
293 static struct rte_pci_driver pci_ssovf = {
294 .id_table = pci_ssovf_map,
295 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
296 .probe = ssovf_probe,
299 RTE_PMD_REGISTER_PCI(octeontx_ssovf, pci_ssovf);