1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Cavium, Inc
5 #include <rte_atomic.h>
6 #include <rte_common.h>
10 #include <rte_bus_pci.h>
12 #include "octeontx_mbox.h"
13 #include "octeontx_pool_logs.h"
15 #define PCI_VENDOR_ID_CAVIUM 0x177D
16 #define PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF 0xA04B
17 #define PCI_DEVICE_ID_OCTEONTX_SSOWS_VF 0xA04D
19 #define SSO_MAX_VHGRP (64)
20 #define SSO_MAX_VHWS (32)
22 #define SSO_VHGRP_AQ_THR (0x1E0ULL)
39 struct ssowvf_identify {
46 uint8_t total_ssowvfs;
47 struct ssovf_res grp[SSO_MAX_VHGRP];
48 struct ssowvf_res hws[SSO_MAX_VHWS];
51 static struct ssodev sdev;
53 /* Interface functions */
55 octeontx_ssovf_info(struct octeontx_ssovf_info *info)
60 if (rte_eal_process_type() != RTE_PROC_PRIMARY || info == NULL)
63 if (sdev.total_ssovfs == 0 || sdev.total_ssowvfs == 0)
66 domain = sdev.grp[0].domain;
67 for (i = 0; i < sdev.total_ssovfs; i++) {
68 /* Check vfid's are contiguous and belong to same domain */
69 if (sdev.grp[i].vfid != i ||
70 sdev.grp[i].bar0 == NULL ||
71 sdev.grp[i].domain != domain) {
72 mbox_log_err("GRP error, vfid=%d/%d domain=%d/%d %p",
74 domain, sdev.grp[i].domain,
80 for (i = 0; i < sdev.total_ssowvfs; i++) {
81 /* Check vfid's are contiguous and belong to same domain */
82 if (sdev.hws[i].vfid != i ||
83 sdev.hws[i].bar0 == NULL ||
84 sdev.hws[i].domain != domain) {
85 mbox_log_err("HWS error, vfid=%d/%d domain=%d/%d %p",
87 domain, sdev.hws[i].domain,
93 info->domain = domain;
94 info->total_ssovfs = sdev.total_ssovfs;
95 info->total_ssowvfs = sdev.total_ssowvfs;
100 octeontx_ssovf_bar(enum octeontx_ssovf_type type, uint8_t id, uint8_t bar)
102 if (rte_eal_process_type() != RTE_PROC_PRIMARY ||
103 type > OCTEONTX_SSO_HWS)
106 if (type == OCTEONTX_SSO_GROUP) {
107 if (id >= sdev.total_ssovfs)
110 if (id >= sdev.total_ssowvfs)
114 if (type == OCTEONTX_SSO_GROUP) {
117 return sdev.grp[id].bar0;
119 return sdev.grp[id].bar2;
126 return sdev.hws[id].bar0;
128 return sdev.hws[id].bar2;
130 return sdev.hws[id].bar4;
137 /* SSOWVF pcie device aka event port probe */
140 ssowvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
143 struct ssowvf_res *res;
144 struct ssowvf_identify *id;
146 RTE_SET_USED(pci_drv);
148 /* For secondary processes, the primary has done all the work */
149 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
152 if (pci_dev->mem_resource[0].addr == NULL ||
153 pci_dev->mem_resource[2].addr == NULL ||
154 pci_dev->mem_resource[4].addr == NULL) {
155 mbox_log_err("Empty bars %p %p %p",
156 pci_dev->mem_resource[0].addr,
157 pci_dev->mem_resource[2].addr,
158 pci_dev->mem_resource[4].addr);
162 if (pci_dev->mem_resource[4].len != SSOW_BAR4_LEN) {
163 mbox_log_err("Bar4 len mismatch %d != %d",
164 SSOW_BAR4_LEN, (int)pci_dev->mem_resource[4].len);
168 id = pci_dev->mem_resource[4].addr;
170 if (vfid >= SSO_MAX_VHWS) {
171 mbox_log_err("Invalid vfid(%d/%d)", vfid, SSO_MAX_VHWS);
175 res = &sdev.hws[vfid];
177 res->bar0 = pci_dev->mem_resource[0].addr;
178 res->bar2 = pci_dev->mem_resource[2].addr;
179 res->bar4 = pci_dev->mem_resource[4].addr;
180 res->domain = id->domain;
182 sdev.total_ssowvfs++;
184 mbox_log_dbg("Domain=%d hws=%d total_ssowvfs=%d", res->domain,
185 res->vfid, sdev.total_ssowvfs);
189 static const struct rte_pci_id pci_ssowvf_map[] = {
191 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
192 PCI_DEVICE_ID_OCTEONTX_SSOWS_VF)
199 static struct rte_pci_driver pci_ssowvf = {
200 .id_table = pci_ssowvf_map,
201 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
202 .probe = ssowvf_probe,
205 RTE_PMD_REGISTER_PCI(octeontx_ssowvf, pci_ssowvf);
207 /* SSOVF pcie device aka event queue probe */
210 ssovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
215 struct ssovf_res *res;
217 RTE_SET_USED(pci_drv);
219 /* For secondary processes, the primary has done all the work */
220 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
223 if (pci_dev->mem_resource[0].addr == NULL ||
224 pci_dev->mem_resource[2].addr == NULL) {
225 mbox_log_err("Empty bars %p %p",
226 pci_dev->mem_resource[0].addr,
227 pci_dev->mem_resource[2].addr);
230 idreg = pci_dev->mem_resource[0].addr;
231 idreg += SSO_VHGRP_AQ_THR;
232 val = rte_read64(idreg);
234 /* Write back the default value of aq_thr */
235 rte_write64((1ULL << 33) - 1, idreg);
236 vfid = (val >> 16) & 0xffff;
237 if (vfid >= SSO_MAX_VHGRP) {
238 mbox_log_err("Invalid vfid (%d/%d)", vfid, SSO_MAX_VHGRP);
242 res = &sdev.grp[vfid];
244 res->bar0 = pci_dev->mem_resource[0].addr;
245 res->bar2 = pci_dev->mem_resource[2].addr;
246 res->domain = val & 0xffff;
250 mbox_log_dbg("Domain=%d group=%d total_ssovfs=%d", res->domain,
251 res->vfid, sdev.total_ssovfs);
255 static const struct rte_pci_id pci_ssovf_map[] = {
257 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
258 PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF)
265 static struct rte_pci_driver pci_ssovf = {
266 .id_table = pci_ssovf_map,
267 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
268 .probe = ssovf_probe,
271 RTE_PMD_REGISTER_PCI(octeontx_ssovf, pci_ssovf);