4 * Copyright (C) Cavium, Inc. 2017.
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7 * modification, are permitted provided that the following conditions
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33 #include <rte_atomic.h>
34 #include <rte_common.h>
39 #include "octeontx_mbox.h"
40 #include "octeontx_pool_logs.h"
42 #define PCI_VENDOR_ID_CAVIUM 0x177D
43 #define PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF 0xA04B
44 #define PCI_DEVICE_ID_OCTEONTX_SSOWS_VF 0xA04D
46 #define SSO_MAX_VHGRP (64)
47 #define SSO_MAX_VHWS (32)
49 #define SSO_VHGRP_AQ_THR (0x1E0ULL)
66 struct ssowvf_identify {
73 uint8_t total_ssowvfs;
74 struct ssovf_res grp[SSO_MAX_VHGRP];
75 struct ssowvf_res hws[SSO_MAX_VHWS];
78 static struct ssodev sdev;
80 /* Interface functions */
82 octeontx_ssovf_info(struct octeontx_ssovf_info *info)
87 if (rte_eal_process_type() != RTE_PROC_PRIMARY || info == NULL)
90 if (sdev.total_ssovfs == 0 || sdev.total_ssowvfs == 0)
93 domain = sdev.grp[0].domain;
94 for (i = 0; i < sdev.total_ssovfs; i++) {
95 /* Check vfid's are contiguous and belong to same domain */
96 if (sdev.grp[i].vfid != i ||
97 sdev.grp[i].bar0 == NULL ||
98 sdev.grp[i].domain != domain) {
99 mbox_log_err("GRP error, vfid=%d/%d domain=%d/%d %p",
101 domain, sdev.grp[i].domain,
107 for (i = 0; i < sdev.total_ssowvfs; i++) {
108 /* Check vfid's are contiguous and belong to same domain */
109 if (sdev.hws[i].vfid != i ||
110 sdev.hws[i].bar0 == NULL ||
111 sdev.hws[i].domain != domain) {
112 mbox_log_err("HWS error, vfid=%d/%d domain=%d/%d %p",
114 domain, sdev.hws[i].domain,
120 info->domain = domain;
121 info->total_ssovfs = sdev.total_ssovfs;
122 info->total_ssowvfs = sdev.total_ssowvfs;
127 octeontx_ssovf_bar(enum octeontx_ssovf_type type, uint8_t id, uint8_t bar)
129 if (rte_eal_process_type() != RTE_PROC_PRIMARY ||
130 type > OCTEONTX_SSO_HWS)
133 if (type == OCTEONTX_SSO_GROUP) {
134 if (id >= sdev.total_ssovfs)
137 if (id >= sdev.total_ssowvfs)
141 if (type == OCTEONTX_SSO_GROUP) {
144 return sdev.grp[id].bar0;
146 return sdev.grp[id].bar2;
153 return sdev.hws[id].bar0;
155 return sdev.hws[id].bar2;
157 return sdev.hws[id].bar4;
164 /* SSOWVF pcie device aka event port probe */
167 ssowvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
170 struct ssowvf_res *res;
171 struct ssowvf_identify *id;
173 RTE_SET_USED(pci_drv);
175 /* For secondary processes, the primary has done all the work */
176 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
179 if (pci_dev->mem_resource[0].addr == NULL ||
180 pci_dev->mem_resource[2].addr == NULL ||
181 pci_dev->mem_resource[4].addr == NULL) {
182 mbox_log_err("Empty bars %p %p %p",
183 pci_dev->mem_resource[0].addr,
184 pci_dev->mem_resource[2].addr,
185 pci_dev->mem_resource[4].addr);
189 if (pci_dev->mem_resource[4].len != SSOW_BAR4_LEN) {
190 mbox_log_err("Bar4 len mismatch %d != %d",
191 SSOW_BAR4_LEN, (int)pci_dev->mem_resource[4].len);
195 id = pci_dev->mem_resource[4].addr;
197 if (vfid >= SSO_MAX_VHWS) {
198 mbox_log_err("Invalid vfid(%d/%d)", vfid, SSO_MAX_VHWS);
202 res = &sdev.hws[vfid];
204 res->bar0 = pci_dev->mem_resource[0].addr;
205 res->bar2 = pci_dev->mem_resource[2].addr;
206 res->bar4 = pci_dev->mem_resource[4].addr;
207 res->domain = id->domain;
209 sdev.total_ssowvfs++;
211 mbox_log_dbg("Domain=%d hws=%d total_ssowvfs=%d", res->domain,
212 res->vfid, sdev.total_ssowvfs);
216 static const struct rte_pci_id pci_ssowvf_map[] = {
218 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
219 PCI_DEVICE_ID_OCTEONTX_SSOWS_VF)
226 static struct rte_pci_driver pci_ssowvf = {
227 .id_table = pci_ssowvf_map,
228 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
229 .probe = ssowvf_probe,
232 RTE_PMD_REGISTER_PCI(octeontx_ssowvf, pci_ssowvf);
234 /* SSOVF pcie device aka event queue probe */
237 ssovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
242 struct ssovf_res *res;
244 RTE_SET_USED(pci_drv);
246 /* For secondary processes, the primary has done all the work */
247 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
250 if (pci_dev->mem_resource[0].addr == NULL ||
251 pci_dev->mem_resource[2].addr == NULL) {
252 mbox_log_err("Empty bars %p %p",
253 pci_dev->mem_resource[0].addr,
254 pci_dev->mem_resource[2].addr);
257 idreg = pci_dev->mem_resource[0].addr;
258 idreg += SSO_VHGRP_AQ_THR;
259 val = rte_read64(idreg);
261 /* Write back the default value of aq_thr */
262 rte_write64((1ULL << 33) - 1, idreg);
263 vfid = (val >> 16) & 0xffff;
264 if (vfid >= SSO_MAX_VHGRP) {
265 mbox_log_err("Invalid vfid (%d/%d)", vfid, SSO_MAX_VHGRP);
269 res = &sdev.grp[vfid];
271 res->bar0 = pci_dev->mem_resource[0].addr;
272 res->bar2 = pci_dev->mem_resource[2].addr;
273 res->domain = val & 0xffff;
277 mbox_log_dbg("Domain=%d group=%d total_ssovfs=%d", res->domain,
278 res->vfid, sdev.total_ssovfs);
282 static const struct rte_pci_id pci_ssovf_map[] = {
284 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
285 PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF)
292 static struct rte_pci_driver pci_ssovf = {
293 .id_table = pci_ssovf_map,
294 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
295 .probe = ssovf_probe,
298 RTE_PMD_REGISTER_PCI(octeontx_ssovf, pci_ssovf);