1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_atomic.h>
6 #include <rte_bus_pci.h>
7 #include <rte_common.h>
10 #include <rte_kvargs.h>
11 #include <rte_malloc.h>
12 #include <rte_mbuf_pool_ops.h>
15 #include "otx2_common.h"
17 #include "otx2_mempool.h"
19 #define OTX2_NPA_DEV_NAME RTE_STR(otx2_npa_dev_)
20 #define OTX2_NPA_DEV_NAME_LEN (sizeof(OTX2_NPA_DEV_NAME) + PCI_PRI_STR_SIZE)
23 npa_lf_alloc(struct otx2_npa_lf *lf)
25 struct otx2_mbox *mbox = lf->mbox;
26 struct npa_lf_alloc_req *req;
27 struct npa_lf_alloc_rsp *rsp;
30 req = otx2_mbox_alloc_msg_npa_lf_alloc(mbox);
31 req->aura_sz = lf->aura_sz;
32 req->nr_pools = lf->nr_pools;
34 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
36 return NPA_LF_ERR_ALLOC;
38 lf->stack_pg_ptrs = rsp->stack_pg_ptrs;
39 lf->stack_pg_bytes = rsp->stack_pg_bytes;
40 lf->qints = rsp->qints;
46 npa_lf_free(struct otx2_mbox *mbox)
48 otx2_mbox_alloc_msg_npa_lf_free(mbox);
50 return otx2_mbox_process(mbox);
54 npa_lf_init(struct otx2_npa_lf *lf, uintptr_t base, uint8_t aura_sz,
55 uint32_t nr_pools, struct otx2_mbox *mbox)
61 if (!lf || !base || !mbox || !nr_pools)
62 return NPA_LF_ERR_PARAM;
64 if (base & AURA_ID_MASK)
65 return NPA_LF_ERR_BASE_INVALID;
67 if (aura_sz == NPA_AURA_SZ_0 || aura_sz >= NPA_AURA_SZ_MAX)
68 return NPA_LF_ERR_PARAM;
70 memset(lf, 0x0, sizeof(*lf));
72 lf->aura_sz = aura_sz;
73 lf->nr_pools = nr_pools;
76 rc = npa_lf_alloc(lf);
80 bmp_sz = rte_bitmap_get_memory_footprint(nr_pools);
82 /* Allocate memory for bitmap */
83 lf->npa_bmp_mem = rte_zmalloc("npa_bmp_mem", bmp_sz,
85 if (lf->npa_bmp_mem == NULL) {
90 /* Initialize pool resource bitmap array */
91 lf->npa_bmp = rte_bitmap_init(nr_pools, lf->npa_bmp_mem, bmp_sz);
92 if (lf->npa_bmp == NULL) {
97 /* Mark all pools available */
98 for (i = 0; i < nr_pools; i++)
99 rte_bitmap_set(lf->npa_bmp, i);
101 /* Allocate memory for qint context */
102 lf->npa_qint_mem = rte_zmalloc("npa_qint_mem",
103 sizeof(struct otx2_npa_qint) * nr_pools, 0);
104 if (lf->npa_qint_mem == NULL) {
109 /* Allocate memory for nap_aura_lim memory */
110 lf->aura_lim = rte_zmalloc("npa_aura_lim_mem",
111 sizeof(struct npa_aura_lim) * nr_pools, 0);
112 if (lf->aura_lim == NULL) {
117 /* Init aura start & end limits */
118 for (i = 0; i < nr_pools; i++) {
119 lf->aura_lim[i].ptr_start = UINT64_MAX;
120 lf->aura_lim[i].ptr_end = 0x0ull;
126 rte_free(lf->npa_qint_mem);
128 rte_bitmap_free(lf->npa_bmp);
130 rte_free(lf->npa_bmp_mem);
132 npa_lf_free(lf->mbox);
138 npa_lf_fini(struct otx2_npa_lf *lf)
141 return NPA_LF_ERR_PARAM;
143 rte_free(lf->aura_lim);
144 rte_free(lf->npa_qint_mem);
145 rte_bitmap_free(lf->npa_bmp);
146 rte_free(lf->npa_bmp_mem);
148 return npa_lf_free(lf->mbox);
152 static inline uint32_t
153 otx2_aura_size_to_u32(uint8_t val)
155 if (val == NPA_AURA_SZ_0)
157 if (val >= NPA_AURA_SZ_MAX)
160 return 1 << (val + 6);
164 parse_max_pools(const char *key, const char *value, void *extra_args)
170 if (val < otx2_aura_size_to_u32(NPA_AURA_SZ_128))
172 if (val > otx2_aura_size_to_u32(NPA_AURA_SZ_1M))
175 *(uint8_t *)extra_args = rte_log2_u32(val) - 6;
179 #define OTX2_MAX_POOLS "max_pools"
182 otx2_parse_aura_size(struct rte_devargs *devargs)
184 uint8_t aura_sz = NPA_AURA_SZ_128;
185 struct rte_kvargs *kvlist;
189 kvlist = rte_kvargs_parse(devargs->args, NULL);
193 rte_kvargs_process(kvlist, OTX2_MAX_POOLS, &parse_max_pools, &aura_sz);
194 otx2_parse_common_devargs(kvlist);
195 rte_kvargs_free(kvlist);
201 npa_lf_attach(struct otx2_mbox *mbox)
203 struct rsrc_attach_req *req;
205 req = otx2_mbox_alloc_msg_attach_resources(mbox);
208 return otx2_mbox_process(mbox);
212 npa_lf_detach(struct otx2_mbox *mbox)
214 struct rsrc_detach_req *req;
216 req = otx2_mbox_alloc_msg_detach_resources(mbox);
219 return otx2_mbox_process(mbox);
223 npa_lf_get_msix_offset(struct otx2_mbox *mbox, uint16_t *npa_msixoff)
225 struct msix_offset_rsp *msix_rsp;
228 /* Get NPA and NIX MSIX vector offsets */
229 otx2_mbox_alloc_msg_msix_offset(mbox);
231 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
233 *npa_msixoff = msix_rsp->npa_msixoff;
243 otx2_npa_lf_fini(void)
245 struct otx2_idev_cfg *idev;
248 idev = otx2_intra_dev_get_cfg();
252 if (rte_atomic16_add_return(&idev->npa_refcnt, -1) == 0) {
253 otx2_npa_unregister_irqs(idev->npa_lf);
254 rc |= npa_lf_fini(idev->npa_lf);
255 rc |= npa_lf_detach(idev->npa_lf->mbox);
256 otx2_npa_set_defaults(idev);
267 otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev)
269 struct otx2_dev *dev = otx2_dev;
270 struct otx2_idev_cfg *idev;
271 struct otx2_npa_lf *lf;
272 uint16_t npa_msixoff;
277 idev = otx2_intra_dev_get_cfg();
281 /* Is NPA LF initialized by any another driver? */
282 if (rte_atomic16_add_return(&idev->npa_refcnt, 1) == 1) {
284 rc = npa_lf_attach(dev->mbox);
288 rc = npa_lf_get_msix_offset(dev->mbox, &npa_msixoff);
292 aura_sz = otx2_parse_aura_size(pci_dev->device.devargs);
293 nr_pools = otx2_aura_size_to_u32(aura_sz);
296 rc = npa_lf_init(lf, dev->bar2 + (RVU_BLOCK_ADDR_NPA << 20),
297 aura_sz, nr_pools, dev->mbox);
302 lf->pf_func = dev->pf_func;
303 lf->npa_msixoff = npa_msixoff;
304 lf->intr_handle = &pci_dev->intr_handle;
305 lf->pci_dev = pci_dev;
307 idev->npa_pf_func = dev->pf_func;
310 rc = otx2_npa_register_irqs(lf);
314 rte_mbuf_set_platform_mempool_ops("octeontx2_npa");
315 otx2_npa_dbg("npa_lf=%p pools=%d sz=%d pf_func=0x%x msix=0x%x",
316 lf, nr_pools, aura_sz, lf->pf_func, npa_msixoff);
322 npa_lf_fini(idev->npa_lf);
324 npa_lf_detach(dev->mbox);
326 rte_atomic16_dec(&idev->npa_refcnt);
331 otx2_npa_dev_to_name(struct rte_pci_device *pci_dev, char *name)
333 snprintf(name, OTX2_NPA_DEV_NAME_LEN,
334 OTX2_NPA_DEV_NAME PCI_PRI_FMT,
335 pci_dev->addr.domain, pci_dev->addr.bus,
336 pci_dev->addr.devid, pci_dev->addr.function);
342 otx2_npa_init(struct rte_pci_device *pci_dev)
344 char name[OTX2_NPA_DEV_NAME_LEN];
345 const struct rte_memzone *mz;
346 struct otx2_dev *dev;
349 mz = rte_memzone_reserve_aligned(otx2_npa_dev_to_name(pci_dev, name),
350 sizeof(*dev), SOCKET_ID_ANY,
357 /* Initialize the base otx2_dev object */
358 rc = otx2_dev_init(pci_dev, dev);
362 /* Grab the NPA LF if required */
363 rc = otx2_npa_lf_init(pci_dev, dev);
367 dev->drv_inited = true;
372 otx2_dev_fini(pci_dev, dev);
374 rte_memzone_free(mz);
376 otx2_err("Failed to initialize npa device rc=%d", rc);
381 otx2_npa_fini(struct rte_pci_device *pci_dev)
383 char name[OTX2_NPA_DEV_NAME_LEN];
384 const struct rte_memzone *mz;
385 struct otx2_dev *dev;
387 mz = rte_memzone_lookup(otx2_npa_dev_to_name(pci_dev, name));
392 if (!dev->drv_inited)
395 dev->drv_inited = false;
399 if (otx2_npa_lf_active(dev)) {
400 otx2_info("%s: common resource in use by other devices",
405 otx2_dev_fini(pci_dev, dev);
406 rte_memzone_free(mz);
412 npa_remove(struct rte_pci_device *pci_dev)
414 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
417 return otx2_npa_fini(pci_dev);
421 npa_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
423 RTE_SET_USED(pci_drv);
425 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
428 return otx2_npa_init(pci_dev);
431 static const struct rte_pci_id pci_npa_map[] = {
433 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
434 PCI_DEVID_OCTEONTX2_RVU_NPA_PF)
437 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
438 PCI_DEVID_OCTEONTX2_RVU_NPA_VF)
445 static struct rte_pci_driver pci_npa = {
446 .id_table = pci_npa_map,
447 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
449 .remove = npa_remove,
452 RTE_PMD_REGISTER_PCI(mempool_octeontx2, pci_npa);
453 RTE_PMD_REGISTER_PCI_TABLE(mempool_octeontx2, pci_npa_map);
454 RTE_PMD_REGISTER_KMOD_DEP(mempool_octeontx2, "vfio-pci");
455 RTE_PMD_REGISTER_PARAM_STRING(mempool_octeontx2,
456 OTX2_MAX_POOLS "=<128-1048576>"
457 OTX2_NPA_LOCK_MASK "=<1-65535>");