1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_atomic.h>
6 #include <rte_bus_pci.h>
7 #include <rte_common.h>
10 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
14 #include "otx2_common.h"
16 #include "otx2_mempool.h"
18 #define OTX2_NPA_DEV_NAME RTE_STR(otx2_npa_dev_)
19 #define OTX2_NPA_DEV_NAME_LEN (sizeof(OTX2_NPA_DEV_NAME) + PCI_PRI_STR_SIZE)
22 npa_lf_alloc(struct otx2_npa_lf *lf)
24 struct otx2_mbox *mbox = lf->mbox;
25 struct npa_lf_alloc_req *req;
26 struct npa_lf_alloc_rsp *rsp;
29 req = otx2_mbox_alloc_msg_npa_lf_alloc(mbox);
30 req->aura_sz = lf->aura_sz;
31 req->nr_pools = lf->nr_pools;
33 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
35 return NPA_LF_ERR_ALLOC;
37 lf->stack_pg_ptrs = rsp->stack_pg_ptrs;
38 lf->stack_pg_bytes = rsp->stack_pg_bytes;
39 lf->qints = rsp->qints;
45 npa_lf_free(struct otx2_mbox *mbox)
47 otx2_mbox_alloc_msg_npa_lf_free(mbox);
49 return otx2_mbox_process(mbox);
53 npa_lf_init(struct otx2_npa_lf *lf, uintptr_t base, uint8_t aura_sz,
54 uint32_t nr_pools, struct otx2_mbox *mbox)
60 if (!lf || !base || !mbox || !nr_pools)
61 return NPA_LF_ERR_PARAM;
63 if (base & AURA_ID_MASK)
64 return NPA_LF_ERR_BASE_INVALID;
66 if (aura_sz == NPA_AURA_SZ_0 || aura_sz >= NPA_AURA_SZ_MAX)
67 return NPA_LF_ERR_PARAM;
69 memset(lf, 0x0, sizeof(*lf));
71 lf->aura_sz = aura_sz;
72 lf->nr_pools = nr_pools;
75 rc = npa_lf_alloc(lf);
79 bmp_sz = rte_bitmap_get_memory_footprint(nr_pools);
81 /* Allocate memory for bitmap */
82 lf->npa_bmp_mem = rte_zmalloc("npa_bmp_mem", bmp_sz,
84 if (lf->npa_bmp_mem == NULL) {
89 /* Initialize pool resource bitmap array */
90 lf->npa_bmp = rte_bitmap_init(nr_pools, lf->npa_bmp_mem, bmp_sz);
91 if (lf->npa_bmp == NULL) {
96 /* Mark all pools available */
97 for (i = 0; i < nr_pools; i++)
98 rte_bitmap_set(lf->npa_bmp, i);
100 /* Allocate memory for qint context */
101 lf->npa_qint_mem = rte_zmalloc("npa_qint_mem",
102 sizeof(struct otx2_npa_qint) * nr_pools, 0);
103 if (lf->npa_qint_mem == NULL) {
111 rte_bitmap_free(lf->npa_bmp);
113 rte_free(lf->npa_bmp_mem);
115 npa_lf_free(lf->mbox);
121 npa_lf_fini(struct otx2_npa_lf *lf)
124 return NPA_LF_ERR_PARAM;
126 rte_free(lf->npa_qint_mem);
127 rte_bitmap_free(lf->npa_bmp);
128 rte_free(lf->npa_bmp_mem);
130 return npa_lf_free(lf->mbox);
134 static inline uint32_t
135 otx2_aura_size_to_u32(uint8_t val)
137 if (val == NPA_AURA_SZ_0)
139 if (val >= NPA_AURA_SZ_MAX)
142 return 1 << (val + 6);
146 npa_lf_attach(struct otx2_mbox *mbox)
148 struct rsrc_attach_req *req;
150 req = otx2_mbox_alloc_msg_attach_resources(mbox);
153 return otx2_mbox_process(mbox);
157 npa_lf_detach(struct otx2_mbox *mbox)
159 struct rsrc_detach_req *req;
161 req = otx2_mbox_alloc_msg_detach_resources(mbox);
164 return otx2_mbox_process(mbox);
168 npa_lf_get_msix_offset(struct otx2_mbox *mbox, uint16_t *npa_msixoff)
170 struct msix_offset_rsp *msix_rsp;
173 /* Get NPA and NIX MSIX vector offsets */
174 otx2_mbox_alloc_msg_msix_offset(mbox);
176 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
178 *npa_msixoff = msix_rsp->npa_msixoff;
188 otx2_npa_lf_fini(void)
190 struct otx2_idev_cfg *idev;
193 idev = otx2_intra_dev_get_cfg();
197 if (rte_atomic16_add_return(&idev->npa_refcnt, -1) == 0) {
198 rc |= npa_lf_fini(idev->npa_lf);
199 rc |= npa_lf_detach(idev->npa_lf->mbox);
200 otx2_npa_set_defaults(idev);
211 otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev)
213 struct otx2_dev *dev = otx2_dev;
214 struct otx2_idev_cfg *idev;
215 struct otx2_npa_lf *lf;
216 uint16_t npa_msixoff;
221 idev = otx2_intra_dev_get_cfg();
225 /* Is NPA LF initialized by any another driver? */
226 if (rte_atomic16_add_return(&idev->npa_refcnt, 1) == 1) {
228 rc = npa_lf_attach(dev->mbox);
232 rc = npa_lf_get_msix_offset(dev->mbox, &npa_msixoff);
236 aura_sz = NPA_AURA_SZ_128;
237 nr_pools = otx2_aura_size_to_u32(aura_sz);
240 rc = npa_lf_init(lf, dev->bar2 + (RVU_BLOCK_ADDR_NPA << 20),
241 aura_sz, nr_pools, dev->mbox);
246 lf->pf_func = dev->pf_func;
247 lf->npa_msixoff = npa_msixoff;
248 lf->intr_handle = &pci_dev->intr_handle;
249 lf->pci_dev = pci_dev;
251 idev->npa_pf_func = dev->pf_func;
255 rte_mbuf_set_platform_mempool_ops("octeontx2_npa");
256 otx2_npa_dbg("npa_lf=%p pools=%d sz=%d pf_func=0x%x msix=0x%x",
257 lf, nr_pools, aura_sz, lf->pf_func, npa_msixoff);
263 npa_lf_detach(dev->mbox);
265 rte_atomic16_dec(&idev->npa_refcnt);
270 otx2_npa_dev_to_name(struct rte_pci_device *pci_dev, char *name)
272 snprintf(name, OTX2_NPA_DEV_NAME_LEN,
273 OTX2_NPA_DEV_NAME PCI_PRI_FMT,
274 pci_dev->addr.domain, pci_dev->addr.bus,
275 pci_dev->addr.devid, pci_dev->addr.function);
281 otx2_npa_init(struct rte_pci_device *pci_dev)
283 char name[OTX2_NPA_DEV_NAME_LEN];
284 const struct rte_memzone *mz;
285 struct otx2_dev *dev;
288 mz = rte_memzone_reserve_aligned(otx2_npa_dev_to_name(pci_dev, name),
289 sizeof(*dev), SOCKET_ID_ANY,
296 /* Initialize the base otx2_dev object */
297 rc = otx2_dev_init(pci_dev, dev);
301 /* Grab the NPA LF if required */
302 rc = otx2_npa_lf_init(pci_dev, dev);
306 dev->drv_inited = true;
311 otx2_dev_fini(pci_dev, dev);
313 rte_memzone_free(mz);
315 otx2_err("Failed to initialize npa device rc=%d", rc);
320 otx2_npa_fini(struct rte_pci_device *pci_dev)
322 char name[OTX2_NPA_DEV_NAME_LEN];
323 const struct rte_memzone *mz;
324 struct otx2_dev *dev;
326 mz = rte_memzone_lookup(otx2_npa_dev_to_name(pci_dev, name));
331 if (!dev->drv_inited)
334 dev->drv_inited = false;
338 if (otx2_npa_lf_active(dev)) {
339 otx2_info("%s: common resource in use by other devices",
344 otx2_dev_fini(pci_dev, dev);
345 rte_memzone_free(mz);
351 npa_remove(struct rte_pci_device *pci_dev)
353 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
356 return otx2_npa_fini(pci_dev);
360 npa_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
362 RTE_SET_USED(pci_drv);
364 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
367 return otx2_npa_init(pci_dev);
370 static const struct rte_pci_id pci_npa_map[] = {
372 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
373 PCI_DEVID_OCTEONTX2_RVU_NPA_PF)
376 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
377 PCI_DEVID_OCTEONTX2_RVU_NPA_VF)
384 static struct rte_pci_driver pci_npa = {
385 .id_table = pci_npa_map,
386 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
388 .remove = npa_remove,
391 RTE_PMD_REGISTER_PCI(mempool_octeontx2, pci_npa);
392 RTE_PMD_REGISTER_PCI_TABLE(mempool_octeontx2, pci_npa_map);
393 RTE_PMD_REGISTER_KMOD_DEP(mempool_octeontx2, "vfio-pci");