1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2018 Atomic Rules LLC
7 #include "ark_ethdev_tx.h"
8 #include "ark_global.h"
13 #define ARK_TX_META_SIZE 32
14 #define ARK_TX_META_OFFSET (RTE_PKTMBUF_HEADROOM - ARK_TX_META_SIZE)
15 #define ARK_TX_MAX_NOCHAIN (RTE_MBUF_DEFAULT_DATAROOM)
17 #ifndef RTE_LIBRTE_ARK_MIN_TX_PKTLEN
18 #define ARK_MIN_TX_PKTLEN 0
20 #define ARK_MIN_TX_PKTLEN RTE_LIBRTE_ARK_MIN_TX_PKTLEN
23 /* ************************************************************************* */
25 struct ark_tx_meta *meta_q;
26 struct rte_mbuf **bufs;
28 /* handles for hw objects */
29 struct ark_mpu_t *mpu;
30 struct ark_ddm_t *ddm;
32 /* Stats HW tracks bytes and packets, need to count send errors */
38 /* 3 indexes to the paired data rings. */
39 uint32_t prod_index; /* where to put the next one */
40 uint32_t free_index; /* mbuf has been freed */
42 /* The queue Id is used to identify the HW Q */
44 /* The queue Index within the dpdk device structures */
49 /* second cache line - fields only used in slow path */
50 RTE_MARKER cacheline1 __rte_cache_min_aligned;
51 uint32_t cons_index; /* hw is done, can be freed */
52 } __rte_cache_aligned;
54 /* Forward declarations */
55 static uint32_t eth_ark_tx_jumbo(struct ark_tx_queue *queue,
56 struct rte_mbuf *mbuf);
57 static int eth_ark_tx_hw_queue_config(struct ark_tx_queue *queue);
58 static void free_completed_tx(struct ark_tx_queue *queue);
61 ark_tx_hw_queue_stop(struct ark_tx_queue *queue)
63 ark_mpu_stop(queue->mpu);
66 /* ************************************************************************* */
68 eth_ark_tx_meta_from_mbuf(struct ark_tx_meta *meta,
69 const struct rte_mbuf *mbuf,
72 meta->physaddr = rte_mbuf_data_iova(mbuf);
73 meta->user1 = (uint32_t)mbuf->udata64;
74 meta->data_len = rte_pktmbuf_data_len(mbuf);
78 /* ************************************************************************* */
80 eth_ark_xmit_pkts_noop(void *vtxq __rte_unused,
81 struct rte_mbuf **tx_pkts __rte_unused,
82 uint16_t nb_pkts __rte_unused)
87 /* ************************************************************************* */
89 eth_ark_xmit_pkts(void *vtxq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
91 struct ark_tx_queue *queue;
92 struct rte_mbuf *mbuf;
93 struct ark_tx_meta *meta;
96 uint32_t prod_index_limit;
99 const uint32_t min_pkt_len = ARK_MIN_TX_PKTLEN;
101 queue = (struct ark_tx_queue *)vtxq;
103 /* free any packets after the HW is done with them */
104 free_completed_tx(queue);
106 prod_index_limit = queue->queue_size + queue->free_index;
109 (nb < nb_pkts) && (queue->prod_index != prod_index_limit);
114 unlikely(rte_pktmbuf_pkt_len(mbuf) < min_pkt_len)) {
115 /* this packet even if it is small can be split,
116 * be sure to add to the end mbuf
118 uint16_t to_add = min_pkt_len -
119 rte_pktmbuf_pkt_len(mbuf);
121 rte_pktmbuf_append(mbuf, to_add);
124 /* This packet is in error,
125 * we cannot send it so just
126 * count it and delete it.
128 queue->tx_errors += 1;
129 rte_pktmbuf_free(mbuf);
132 memset(appended, 0, to_add);
135 if (unlikely(mbuf->nb_segs != 1)) {
136 stat = eth_ark_tx_jumbo(queue, mbuf);
137 if (unlikely(stat != 0))
138 break; /* Queue is full */
140 idx = queue->prod_index & queue->queue_mask;
141 queue->bufs[idx] = mbuf;
142 meta = &queue->meta_q[idx];
143 eth_ark_tx_meta_from_mbuf(meta,
151 if (ARK_DEBUG_CORE && nb != nb_pkts) {
152 ARK_PMD_LOG(DEBUG, "TX: Failure to send:"
157 " free: %" PRIU32 "\n",
162 ark_mpu_dump(queue->mpu,
167 /* let FPGA know producer index. */
169 ark_mpu_set_producer(queue->mpu, queue->prod_index);
174 /* ************************************************************************* */
176 eth_ark_tx_jumbo(struct ark_tx_queue *queue, struct rte_mbuf *mbuf)
178 struct rte_mbuf *next;
179 struct ark_tx_meta *meta;
180 uint32_t free_queue_space;
182 uint8_t flags = ARK_DDM_SOP;
184 free_queue_space = queue->queue_mask -
185 (queue->prod_index - queue->free_index);
186 if (unlikely(free_queue_space < mbuf->nb_segs))
189 while (mbuf != NULL) {
192 idx = queue->prod_index & queue->queue_mask;
193 queue->bufs[idx] = mbuf;
194 meta = &queue->meta_q[idx];
196 flags |= (next == NULL) ? ARK_DDM_EOP : 0;
197 eth_ark_tx_meta_from_mbuf(meta, mbuf, flags);
200 flags &= ~ARK_DDM_SOP; /* drop SOP flags */
207 /* ************************************************************************* */
209 eth_ark_tx_queue_setup(struct rte_eth_dev *dev,
212 unsigned int socket_id,
213 const struct rte_eth_txconf *tx_conf __rte_unused)
215 struct ark_adapter *ark = dev->data->dev_private;
216 struct ark_tx_queue *queue;
219 int qidx = queue_idx;
221 if (!rte_is_power_of_2(nb_desc)) {
223 "DPDK Arkville configuration queue size"
224 " must be power of two %u (%s)\n",
229 /* Allocate queue struct */
230 queue = rte_zmalloc_socket("Ark_txqueue",
231 sizeof(struct ark_tx_queue),
235 ARK_PMD_LOG(ERR, "Failed to allocate tx "
236 "queue memory in %s\n",
241 /* we use zmalloc no need to initialize fields */
242 queue->queue_size = nb_desc;
243 queue->queue_mask = nb_desc - 1;
244 queue->phys_qid = qidx;
245 queue->queue_index = queue_idx;
246 dev->data->tx_queues[queue_idx] = queue;
249 rte_zmalloc_socket("Ark_txqueue meta",
250 nb_desc * sizeof(struct ark_tx_meta),
254 rte_zmalloc_socket("Ark_txqueue bufs",
255 nb_desc * sizeof(struct rte_mbuf *),
259 if (queue->meta_q == 0 || queue->bufs == 0) {
260 ARK_PMD_LOG(ERR, "Failed to allocate "
261 "queue memory in %s\n", __func__);
262 rte_free(queue->meta_q);
263 rte_free(queue->bufs);
268 queue->ddm = RTE_PTR_ADD(ark->ddm.v, qidx * ARK_DDM_QOFFSET);
269 queue->mpu = RTE_PTR_ADD(ark->mputx.v, qidx * ARK_MPU_QOFFSET);
271 status = eth_ark_tx_hw_queue_config(queue);
273 if (unlikely(status != 0)) {
274 rte_free(queue->meta_q);
275 rte_free(queue->bufs);
277 return -1; /* ERROR CODE */
283 /* ************************************************************************* */
285 eth_ark_tx_hw_queue_config(struct ark_tx_queue *queue)
287 rte_iova_t queue_base, ring_base, cons_index_addr;
288 uint32_t write_interval_ns;
290 /* Verify HW -- MPU */
291 if (ark_mpu_verify(queue->mpu, sizeof(struct ark_tx_meta)))
294 queue_base = rte_malloc_virt2iova(queue);
295 ring_base = rte_malloc_virt2iova(queue->meta_q);
297 queue_base + offsetof(struct ark_tx_queue, cons_index);
299 ark_mpu_stop(queue->mpu);
300 ark_mpu_reset(queue->mpu);
302 /* Stop and Reset and configure MPU */
303 ark_mpu_configure(queue->mpu, ring_base, queue->queue_size, 1);
306 * Adjust the write interval based on queue size --
307 * increase pcie traffic when low mbuf count
308 * Queue sizes less than 128 are not allowed
310 switch (queue->queue_size) {
312 write_interval_ns = 500;
315 write_interval_ns = 500;
318 write_interval_ns = 1000;
321 write_interval_ns = 2000;
325 /* Completion address in UDM */
326 ark_ddm_setup(queue->ddm, cons_index_addr, write_interval_ns);
331 /* ************************************************************************* */
333 eth_ark_tx_queue_release(void *vtx_queue)
335 struct ark_tx_queue *queue;
337 queue = (struct ark_tx_queue *)vtx_queue;
339 ark_tx_hw_queue_stop(queue);
341 queue->cons_index = queue->prod_index;
342 free_completed_tx(queue);
344 rte_free(queue->meta_q);
345 rte_free(queue->bufs);
349 /* ************************************************************************* */
351 eth_ark_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
353 struct ark_tx_queue *queue;
356 queue = dev->data->tx_queues[queue_id];
358 /* Wait for DDM to send out all packets. */
359 while (queue->cons_index != queue->prod_index) {
365 ark_mpu_stop(queue->mpu);
366 free_completed_tx(queue);
368 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
374 eth_ark_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
376 struct ark_tx_queue *queue;
378 queue = dev->data->tx_queues[queue_id];
379 if (dev->data->tx_queue_state[queue_id] == RTE_ETH_QUEUE_STATE_STARTED)
382 ark_mpu_start(queue->mpu);
383 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
388 /* ************************************************************************* */
390 free_completed_tx(struct ark_tx_queue *queue)
392 struct rte_mbuf *mbuf;
393 struct ark_tx_meta *meta;
396 top_index = queue->cons_index; /* read once */
397 while (queue->free_index != top_index) {
398 meta = &queue->meta_q[queue->free_index & queue->queue_mask];
399 mbuf = queue->bufs[queue->free_index & queue->queue_mask];
401 if (likely((meta->flags & ARK_DDM_SOP) != 0)) {
402 /* ref count of the mbuf is checked in this call. */
403 rte_pktmbuf_free(mbuf);
409 /* ************************************************************************* */
411 eth_tx_queue_stats_get(void *vqueue, struct rte_eth_stats *stats)
413 struct ark_tx_queue *queue;
414 struct ark_ddm_t *ddm;
415 uint64_t bytes, pkts;
420 bytes = ark_ddm_queue_byte_count(ddm);
421 pkts = ark_ddm_queue_pkt_count(ddm);
423 stats->q_opackets[queue->queue_index] = pkts;
424 stats->q_obytes[queue->queue_index] = bytes;
425 stats->opackets += pkts;
426 stats->obytes += bytes;
427 stats->oerrors += queue->tx_errors;
431 eth_tx_queue_stats_reset(void *vqueue)
433 struct ark_tx_queue *queue;
434 struct ark_ddm_t *ddm;
439 ark_ddm_queue_reset_stats(ddm);
440 queue->tx_errors = 0;