1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2018 Atomic Rules LLC
10 static_assert(sizeof(struct ark_rx_meta) == 32, "Unexpected struct size ark_rx_meta");
13 ark_udm_verify(struct ark_udm_t *udm)
15 if (sizeof(struct ark_udm_t) != ARK_UDM_EXPECT_SIZE) {
17 "ARK: UDM structure looks incorrect %d vs %zd\n",
18 ARK_UDM_EXPECT_SIZE, sizeof(struct ark_udm_t));
22 if (udm->setup.const0 != ARK_UDM_CONST) {
24 "ARK: UDM module not found as expected 0x%08x\n",
32 ark_udm_stop(struct ark_udm_t *udm, const int wait)
39 while (wait && (udm->cfg.stop_flushed & 0x01) == 0) {
49 ark_udm_reset(struct ark_udm_t *udm)
53 status = ark_udm_stop(udm, 1);
55 ARK_PMD_LOG(NOTICE, "%s stop failed doing forced reset\n",
60 status = ark_udm_stop(udm, 0);
61 ARK_PMD_LOG(INFO, "%s stop status %d post failure"
62 " and forced reset\n",
72 ark_udm_start(struct ark_udm_t *udm)
78 ark_udm_stats_reset(struct ark_udm_t *udm)
80 udm->pcibp.pci_clear = 1;
81 udm->tlp_ps.tlp_clear = 1;
85 ark_udm_configure(struct ark_udm_t *udm,
88 uint32_t write_interval_ns)
90 /* headroom and data room are in DWords in the UDM */
91 udm->cfg.dataroom = dataroom / 4;
92 udm->cfg.headroom = headroom / 4;
95 udm->rt_cfg.write_interval = write_interval_ns / 4;
99 ark_udm_write_addr(struct ark_udm_t *udm, rte_iova_t addr)
101 udm->rt_cfg.hw_prod_addr = addr;
105 ark_udm_is_flushed(struct ark_udm_t *udm)
107 return (udm->cfg.stop_flushed & 0x01) != 0;
111 ark_udm_dropped(struct ark_udm_t *udm)
113 return udm->qstats.q_pkt_drop;
117 ark_udm_bytes(struct ark_udm_t *udm)
119 return udm->qstats.q_byte_count;
123 ark_udm_packets(struct ark_udm_t *udm)
125 return udm->qstats.q_ff_packet_count;
129 ark_udm_dump_stats(struct ark_udm_t *udm, const char *msg)
131 ARK_PMD_LOG(INFO, "UDM Stats: %s"
132 ARK_SU64 ARK_SU64 ARK_SU64 ARK_SU64 ARK_SU64 "\n",
134 "Pkts Received", udm->stats.rx_packet_count,
135 "Pkts Finalized", udm->stats.rx_sent_packets,
136 "Pkts Dropped", udm->tlp.pkt_drop,
137 "Bytes Count", udm->stats.rx_byte_count,
138 "MBuf Count", udm->stats.rx_mbuf_count);
142 ark_udm_dump_queue_stats(struct ark_udm_t *udm, const char *msg, uint16_t qid)
144 ARK_PMD_LOG(INFO, "UDM Queue %3u Stats: %s"
149 "Pkts Received", udm->qstats.q_packet_count,
150 "Pkts Finalized", udm->qstats.q_ff_packet_count,
151 "Pkts Dropped", udm->qstats.q_pkt_drop,
152 "Bytes Count", udm->qstats.q_byte_count,
153 "MBuf Count", udm->qstats.q_mbuf_count);
157 ark_udm_dump(struct ark_udm_t *udm, const char *msg)
159 ARK_PMD_LOG(DEBUG, "UDM Dump: %s Stopped: %d\n", msg,
160 udm->cfg.stop_flushed);
164 ark_udm_dump_setup(struct ark_udm_t *udm, uint16_t q_id)
166 ARK_PMD_LOG(DEBUG, "UDM Setup Q: %u"
167 ARK_SU64X ARK_SU32 "\n",
169 "hw_prod_addr", udm->rt_cfg.hw_prod_addr,
170 "prod_idx", udm->rt_cfg.prod_idx);
174 ark_udm_dump_perf(struct ark_udm_t *udm, const char *msg)
176 struct ark_udm_pcibp_t *bp = &udm->pcibp;
178 ARK_PMD_LOG(INFO, "UDM Performance %s"
179 ARK_SU32 ARK_SU32 ARK_SU32 ARK_SU32 ARK_SU32 ARK_SU32
182 "PCI Empty", bp->pci_empty,
183 "PCI Q1", bp->pci_q1,
184 "PCI Q2", bp->pci_q2,
185 "PCI Q3", bp->pci_q3,
186 "PCI Q4", bp->pci_q4,
187 "PCI Full", bp->pci_full);
191 ark_udm_queue_stats_reset(struct ark_udm_t *udm)
193 udm->qstats.q_byte_count = 1;
197 ark_udm_queue_enable(struct ark_udm_t *udm, int enable)
199 udm->qstats.q_enable = enable ? 1 : 0;