1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Aquantia Corporation
5 #include <rte_malloc.h>
6 #include <ethdev_driver.h>
9 #include "atl_ethdev.h"
10 #include "atl_hw_regs.h"
13 #include "hw_atl/hw_atl_llh.h"
14 #include "hw_atl/hw_atl_b0.h"
15 #include "hw_atl/hw_atl_b0_internal.h"
17 #define ATL_TX_CKSUM_OFFLOAD_MASK ( \
18 RTE_MBUF_F_TX_IP_CKSUM | \
19 RTE_MBUF_F_TX_L4_MASK | \
20 RTE_MBUF_F_TX_TCP_SEG)
22 #define ATL_TX_OFFLOAD_MASK ( \
23 RTE_MBUF_F_TX_VLAN | \
24 RTE_MBUF_F_TX_IPV6 | \
25 RTE_MBUF_F_TX_IPV4 | \
26 RTE_MBUF_F_TX_IP_CKSUM | \
27 RTE_MBUF_F_TX_L4_MASK | \
28 RTE_MBUF_F_TX_TCP_SEG)
30 #define ATL_TX_OFFLOAD_NOTSUP_MASK \
31 (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ATL_TX_OFFLOAD_MASK)
34 * Structure associated with each descriptor of the RX ring of a RX queue.
37 struct rte_mbuf *mbuf;
41 * Structure associated with each descriptor of the TX ring of a TX queue.
44 struct rte_mbuf *mbuf;
50 * Structure associated with each RX queue.
53 struct rte_mempool *mb_pool;
54 struct hw_atl_rxd_s *hw_ring;
55 uint64_t hw_ring_phys_addr;
56 struct atl_rx_entry *sw_ring;
60 uint16_t rx_free_thresh;
69 * Structure associated with each TX queue.
72 struct hw_atl_txd_s *hw_ring;
73 uint64_t hw_ring_phys_addr;
74 struct atl_tx_entry *sw_ring;
80 uint16_t tx_free_thresh;
85 atl_reset_rx_queue(struct atl_rx_queue *rxq)
87 struct hw_atl_rxd_s *rxd = NULL;
90 PMD_INIT_FUNC_TRACE();
92 for (i = 0; i < rxq->nb_rx_desc; i++) {
93 rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[i];
102 atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
103 uint16_t nb_rx_desc, unsigned int socket_id,
104 const struct rte_eth_rxconf *rx_conf,
105 struct rte_mempool *mb_pool)
107 struct atl_rx_queue *rxq;
108 const struct rte_memzone *mz;
110 PMD_INIT_FUNC_TRACE();
112 /* make sure a valid number of descriptors have been requested */
113 if (nb_rx_desc < AQ_HW_MIN_RX_RING_SIZE ||
114 nb_rx_desc > AQ_HW_MAX_RX_RING_SIZE) {
115 PMD_INIT_LOG(ERR, "Number of Rx descriptors must be "
116 "less than or equal to %d, "
117 "greater than or equal to %d", AQ_HW_MAX_RX_RING_SIZE,
118 AQ_HW_MIN_RX_RING_SIZE);
123 * if this queue existed already, free the associated memory. The
124 * queue cannot be reused in case we need to allocate memory on
125 * different socket than was previously used.
127 if (dev->data->rx_queues[rx_queue_id] != NULL) {
128 atl_rx_queue_release(dev, rx_queue_id);
129 dev->data->rx_queues[rx_queue_id] = NULL;
132 /* allocate memory for the queue structure */
133 rxq = rte_zmalloc_socket("atlantic Rx queue", sizeof(*rxq),
134 RTE_CACHE_LINE_SIZE, socket_id);
136 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
141 rxq->mb_pool = mb_pool;
142 rxq->nb_rx_desc = nb_rx_desc;
143 rxq->port_id = dev->data->port_id;
144 rxq->queue_id = rx_queue_id;
145 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
147 rxq->l3_csum_enabled = dev->data->dev_conf.rxmode.offloads &
148 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM;
149 rxq->l4_csum_enabled = dev->data->dev_conf.rxmode.offloads &
150 (RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM);
151 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
152 PMD_DRV_LOG(ERR, "PMD does not support KEEP_CRC offload");
154 /* allocate memory for the software ring */
155 rxq->sw_ring = rte_zmalloc_socket("atlantic sw rx ring",
156 nb_rx_desc * sizeof(struct atl_rx_entry),
157 RTE_CACHE_LINE_SIZE, socket_id);
158 if (rxq->sw_ring == NULL) {
160 "Port %d: Cannot allocate software ring for queue %d",
161 rxq->port_id, rxq->queue_id);
167 * allocate memory for the hardware descriptor ring. A memzone large
168 * enough to hold the maximum ring size is requested to allow for
169 * resizing in later calls to the queue setup function.
171 mz = rte_eth_dma_zone_reserve(dev, "rx hw_ring", rx_queue_id,
173 sizeof(struct hw_atl_rxd_s),
177 "Port %d: Cannot allocate hardware ring for queue %d",
178 rxq->port_id, rxq->queue_id);
179 rte_free(rxq->sw_ring);
183 rxq->hw_ring = mz->addr;
184 rxq->hw_ring_phys_addr = mz->iova;
186 atl_reset_rx_queue(rxq);
188 dev->data->rx_queues[rx_queue_id] = rxq;
193 atl_reset_tx_queue(struct atl_tx_queue *txq)
195 struct atl_tx_entry *tx_entry;
196 union hw_atl_txc_s *txc;
199 PMD_INIT_FUNC_TRACE();
202 PMD_DRV_LOG(ERR, "Pointer to txq is NULL");
206 tx_entry = txq->sw_ring;
208 for (i = 0; i < txq->nb_tx_desc; i++) {
209 txc = (union hw_atl_txc_s *)&txq->hw_ring[i];
214 for (i = 0; i < txq->nb_tx_desc; i++) {
215 txq->hw_ring[i].dd = 1;
216 tx_entry[i].mbuf = NULL;
221 txq->tx_free = txq->nb_tx_desc - 1;
225 atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
226 uint16_t nb_tx_desc, unsigned int socket_id,
227 const struct rte_eth_txconf *tx_conf)
229 struct atl_tx_queue *txq;
230 const struct rte_memzone *mz;
232 PMD_INIT_FUNC_TRACE();
234 /* make sure a valid number of descriptors have been requested */
235 if (nb_tx_desc < AQ_HW_MIN_TX_RING_SIZE ||
236 nb_tx_desc > AQ_HW_MAX_TX_RING_SIZE) {
237 PMD_INIT_LOG(ERR, "Number of Tx descriptors must be "
238 "less than or equal to %d, "
239 "greater than or equal to %d", AQ_HW_MAX_TX_RING_SIZE,
240 AQ_HW_MIN_TX_RING_SIZE);
245 * if this queue existed already, free the associated memory. The
246 * queue cannot be reused in case we need to allocate memory on
247 * different socket than was previously used.
249 if (dev->data->tx_queues[tx_queue_id] != NULL) {
250 atl_tx_queue_release(dev, tx_queue_id);
251 dev->data->tx_queues[tx_queue_id] = NULL;
254 /* allocate memory for the queue structure */
255 txq = rte_zmalloc_socket("atlantic Tx queue", sizeof(*txq),
256 RTE_CACHE_LINE_SIZE, socket_id);
258 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
263 txq->nb_tx_desc = nb_tx_desc;
264 txq->port_id = dev->data->port_id;
265 txq->queue_id = tx_queue_id;
266 txq->tx_free_thresh = tx_conf->tx_free_thresh;
269 /* allocate memory for the software ring */
270 txq->sw_ring = rte_zmalloc_socket("atlantic sw tx ring",
271 nb_tx_desc * sizeof(struct atl_tx_entry),
272 RTE_CACHE_LINE_SIZE, socket_id);
273 if (txq->sw_ring == NULL) {
275 "Port %d: Cannot allocate software ring for queue %d",
276 txq->port_id, txq->queue_id);
282 * allocate memory for the hardware descriptor ring. A memzone large
283 * enough to hold the maximum ring size is requested to allow for
284 * resizing in later calls to the queue setup function.
286 mz = rte_eth_dma_zone_reserve(dev, "tx hw_ring", tx_queue_id,
287 HW_ATL_B0_MAX_TXD * sizeof(struct hw_atl_txd_s),
291 "Port %d: Cannot allocate hardware ring for queue %d",
292 txq->port_id, txq->queue_id);
293 rte_free(txq->sw_ring);
297 txq->hw_ring = mz->addr;
298 txq->hw_ring_phys_addr = mz->iova;
300 atl_reset_tx_queue(txq);
302 dev->data->tx_queues[tx_queue_id] = txq;
307 atl_tx_init(struct rte_eth_dev *eth_dev)
309 struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
310 struct atl_tx_queue *txq;
311 uint64_t base_addr = 0;
315 PMD_INIT_FUNC_TRACE();
317 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
318 txq = eth_dev->data->tx_queues[i];
319 base_addr = txq->hw_ring_phys_addr;
321 err = hw_atl_b0_hw_ring_tx_init(hw, base_addr,
328 "Port %d: Cannot init TX queue %d",
329 txq->port_id, txq->queue_id);
338 atl_rx_init(struct rte_eth_dev *eth_dev)
340 struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
341 struct aq_rss_parameters *rss_params = &hw->aq_nic_cfg->aq_rss;
342 struct atl_rx_queue *rxq;
343 uint64_t base_addr = 0;
347 PMD_INIT_FUNC_TRACE();
349 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
350 rxq = eth_dev->data->rx_queues[i];
351 base_addr = rxq->hw_ring_phys_addr;
353 /* Take requested pool mbuf size and adapt
354 * descriptor buffer to best fit
356 int buff_size = rte_pktmbuf_data_room_size(rxq->mb_pool) -
357 RTE_PKTMBUF_HEADROOM;
359 buff_size = RTE_ALIGN_FLOOR(buff_size, 1024);
360 if (buff_size > HW_ATL_B0_RXD_BUF_SIZE_MAX) {
361 PMD_INIT_LOG(WARNING,
362 "Port %d queue %d: mem pool buff size is too big\n",
363 rxq->port_id, rxq->queue_id);
364 buff_size = HW_ATL_B0_RXD_BUF_SIZE_MAX;
366 if (buff_size < 1024) {
368 "Port %d queue %d: mem pool buff size is too small\n",
369 rxq->port_id, rxq->queue_id);
372 rxq->buff_size = buff_size;
374 err = hw_atl_b0_hw_ring_rx_init(hw, base_addr, rxq->queue_id,
375 rxq->nb_rx_desc, buff_size, 0,
379 PMD_INIT_LOG(ERR, "Port %d: Cannot init RX queue %d",
380 rxq->port_id, rxq->queue_id);
385 for (i = rss_params->indirection_table_size; i--;)
386 rss_params->indirection_table[i] = i &
387 (eth_dev->data->nb_rx_queues - 1);
388 hw_atl_b0_hw_rss_set(hw, rss_params);
393 atl_alloc_rx_queue_mbufs(struct atl_rx_queue *rxq)
395 struct atl_rx_entry *rx_entry = rxq->sw_ring;
396 struct hw_atl_rxd_s *rxd;
397 uint64_t dma_addr = 0;
400 PMD_INIT_FUNC_TRACE();
403 for (i = 0; i < rxq->nb_rx_desc; i++) {
404 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
408 "Port %d: mbuf alloc failed for rx queue %d",
409 rxq->port_id, rxq->queue_id);
413 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
414 mbuf->port = rxq->port_id;
416 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
417 rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[i];
418 rxd->buf_addr = dma_addr;
420 rx_entry[i].mbuf = mbuf;
427 atl_rx_queue_release_mbufs(struct atl_rx_queue *rxq)
431 PMD_INIT_FUNC_TRACE();
433 if (rxq->sw_ring != NULL) {
434 for (i = 0; i < rxq->nb_rx_desc; i++) {
435 if (rxq->sw_ring[i].mbuf != NULL) {
436 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
437 rxq->sw_ring[i].mbuf = NULL;
444 atl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
446 struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);
447 struct atl_rx_queue *rxq = NULL;
449 PMD_INIT_FUNC_TRACE();
451 if (rx_queue_id < dev->data->nb_rx_queues) {
452 rxq = dev->data->rx_queues[rx_queue_id];
454 if (atl_alloc_rx_queue_mbufs(rxq) != 0) {
456 "Port %d: Allocate mbufs for queue %d failed",
457 rxq->port_id, rxq->queue_id);
461 hw_atl_b0_hw_ring_rx_start(hw, rx_queue_id);
464 hw_atl_reg_rx_dma_desc_tail_ptr_set(hw, rxq->nb_rx_desc - 1,
466 dev->data->rx_queue_state[rx_queue_id] =
467 RTE_ETH_QUEUE_STATE_STARTED;
476 atl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
478 struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);
479 struct atl_rx_queue *rxq = NULL;
481 PMD_INIT_FUNC_TRACE();
483 if (rx_queue_id < dev->data->nb_rx_queues) {
484 rxq = dev->data->rx_queues[rx_queue_id];
486 hw_atl_b0_hw_ring_rx_stop(hw, rx_queue_id);
488 atl_rx_queue_release_mbufs(rxq);
489 atl_reset_rx_queue(rxq);
491 dev->data->rx_queue_state[rx_queue_id] =
492 RTE_ETH_QUEUE_STATE_STOPPED;
501 atl_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id)
503 struct atl_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
505 PMD_INIT_FUNC_TRACE();
508 atl_rx_queue_release_mbufs(rxq);
509 rte_free(rxq->sw_ring);
515 atl_tx_queue_release_mbufs(struct atl_tx_queue *txq)
519 PMD_INIT_FUNC_TRACE();
521 if (txq->sw_ring != NULL) {
522 for (i = 0; i < txq->nb_tx_desc; i++) {
523 if (txq->sw_ring[i].mbuf != NULL) {
524 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
525 txq->sw_ring[i].mbuf = NULL;
532 atl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
534 struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);
536 PMD_INIT_FUNC_TRACE();
538 if (tx_queue_id < dev->data->nb_tx_queues) {
539 hw_atl_b0_hw_ring_tx_start(hw, tx_queue_id);
542 hw_atl_b0_hw_tx_ring_tail_update(hw, 0, tx_queue_id);
543 dev->data->tx_queue_state[tx_queue_id] =
544 RTE_ETH_QUEUE_STATE_STARTED;
553 atl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
555 struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);
556 struct atl_tx_queue *txq;
558 PMD_INIT_FUNC_TRACE();
560 txq = dev->data->tx_queues[tx_queue_id];
562 hw_atl_b0_hw_ring_tx_stop(hw, tx_queue_id);
564 atl_tx_queue_release_mbufs(txq);
565 atl_reset_tx_queue(txq);
566 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
572 atl_tx_queue_release(struct rte_eth_dev *dev, uint16_t tx_queue_id)
574 struct atl_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
576 PMD_INIT_FUNC_TRACE();
579 atl_tx_queue_release_mbufs(txq);
580 rte_free(txq->sw_ring);
586 atl_free_queues(struct rte_eth_dev *dev)
590 PMD_INIT_FUNC_TRACE();
592 for (i = 0; i < dev->data->nb_rx_queues; i++) {
593 atl_rx_queue_release(dev, i);
594 dev->data->rx_queues[i] = 0;
596 dev->data->nb_rx_queues = 0;
598 for (i = 0; i < dev->data->nb_tx_queues; i++) {
599 atl_tx_queue_release(dev, i);
600 dev->data->tx_queues[i] = 0;
602 dev->data->nb_tx_queues = 0;
606 atl_start_queues(struct rte_eth_dev *dev)
610 PMD_INIT_FUNC_TRACE();
612 for (i = 0; i < dev->data->nb_tx_queues; i++) {
613 if (atl_tx_queue_start(dev, i) != 0) {
615 "Port %d: Start Tx queue %d failed",
616 dev->data->port_id, i);
621 for (i = 0; i < dev->data->nb_rx_queues; i++) {
622 if (atl_rx_queue_start(dev, i) != 0) {
624 "Port %d: Start Rx queue %d failed",
625 dev->data->port_id, i);
634 atl_stop_queues(struct rte_eth_dev *dev)
638 PMD_INIT_FUNC_TRACE();
640 for (i = 0; i < dev->data->nb_tx_queues; i++) {
641 if (atl_tx_queue_stop(dev, i) != 0) {
643 "Port %d: Stop Tx queue %d failed",
644 dev->data->port_id, i);
649 for (i = 0; i < dev->data->nb_rx_queues; i++) {
650 if (atl_rx_queue_stop(dev, i) != 0) {
652 "Port %d: Stop Rx queue %d failed",
653 dev->data->port_id, i);
662 atl_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
663 struct rte_eth_rxq_info *qinfo)
665 struct atl_rx_queue *rxq;
667 PMD_INIT_FUNC_TRACE();
669 rxq = dev->data->rx_queues[queue_id];
671 qinfo->mp = rxq->mb_pool;
672 qinfo->scattered_rx = dev->data->scattered_rx;
673 qinfo->nb_desc = rxq->nb_rx_desc;
677 atl_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
678 struct rte_eth_txq_info *qinfo)
680 struct atl_tx_queue *txq;
682 PMD_INIT_FUNC_TRACE();
684 txq = dev->data->tx_queues[queue_id];
686 qinfo->nb_desc = txq->nb_tx_desc;
689 /* Return Rx queue avail count */
692 atl_rx_queue_count(void *rx_queue)
694 struct atl_rx_queue *rxq;
696 PMD_INIT_FUNC_TRACE();
703 return rxq->nb_rx_desc - rxq->nb_rx_hold;
707 atl_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
709 struct atl_rx_queue *rxq = rx_queue;
710 struct hw_atl_rxd_wb_s *rxd;
713 PMD_INIT_FUNC_TRACE();
715 if (unlikely(offset >= rxq->nb_rx_desc))
718 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
719 return RTE_ETH_RX_DESC_UNAVAIL;
721 idx = rxq->rx_tail + offset;
723 if (idx >= rxq->nb_rx_desc)
724 idx -= rxq->nb_rx_desc;
726 rxd = (struct hw_atl_rxd_wb_s *)&rxq->hw_ring[idx];
729 return RTE_ETH_RX_DESC_DONE;
731 return RTE_ETH_RX_DESC_AVAIL;
735 atl_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
737 struct atl_tx_queue *txq = tx_queue;
738 struct hw_atl_txd_s *txd;
741 PMD_INIT_FUNC_TRACE();
743 if (unlikely(offset >= txq->nb_tx_desc))
746 idx = txq->tx_tail + offset;
748 if (idx >= txq->nb_tx_desc)
749 idx -= txq->nb_tx_desc;
751 txd = &txq->hw_ring[idx];
754 return RTE_ETH_TX_DESC_DONE;
756 return RTE_ETH_TX_DESC_FULL;
760 atl_rx_enable_intr(struct rte_eth_dev *dev, uint16_t queue_id, bool enable)
762 struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);
763 struct atl_rx_queue *rxq;
765 PMD_INIT_FUNC_TRACE();
767 if (queue_id >= dev->data->nb_rx_queues) {
768 PMD_DRV_LOG(ERR, "Invalid RX queue id=%d", queue_id);
772 rxq = dev->data->rx_queues[queue_id];
777 /* Mapping interrupt vector */
778 hw_atl_itr_irq_map_en_rx_set(hw, enable, queue_id);
784 atl_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t queue_id)
786 return atl_rx_enable_intr(eth_dev, queue_id, true);
790 atl_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, uint16_t queue_id)
792 return atl_rx_enable_intr(eth_dev, queue_id, false);
796 atl_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
803 PMD_INIT_FUNC_TRACE();
805 for (i = 0; i < nb_pkts; i++) {
807 ol_flags = m->ol_flags;
809 if (m->nb_segs > AQ_HW_MAX_SEGS_SIZE) {
814 if (ol_flags & ATL_TX_OFFLOAD_NOTSUP_MASK) {
819 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
820 ret = rte_validate_tx_offload(m);
826 ret = rte_net_intel_cksum_prepare(m);
837 atl_desc_to_offload_flags(struct atl_rx_queue *rxq,
838 struct hw_atl_rxd_wb_s *rxd_wb)
840 uint64_t mbuf_flags = 0;
842 PMD_INIT_FUNC_TRACE();
845 if (rxq->l3_csum_enabled && ((rxd_wb->pkt_type & 0x3) == 0)) {
846 /* IPv4 csum error ? */
847 if (rxd_wb->rx_stat & BIT(1))
848 mbuf_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
850 mbuf_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
852 mbuf_flags |= RTE_MBUF_F_RX_IP_CKSUM_UNKNOWN;
855 /* CSUM calculated ? */
856 if (rxq->l4_csum_enabled && (rxd_wb->rx_stat & BIT(3))) {
857 if (rxd_wb->rx_stat & BIT(2))
858 mbuf_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
860 mbuf_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
862 mbuf_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
869 atl_desc_to_pkt_type(struct hw_atl_rxd_wb_s *rxd_wb)
871 uint32_t type = RTE_PTYPE_UNKNOWN;
872 uint16_t l2_l3_type = rxd_wb->pkt_type & 0x3;
873 uint16_t l4_type = (rxd_wb->pkt_type & 0x1C) >> 2;
875 switch (l2_l3_type) {
877 type = RTE_PTYPE_L3_IPV4;
880 type = RTE_PTYPE_L3_IPV6;
883 type = RTE_PTYPE_L2_ETHER;
886 type = RTE_PTYPE_L2_ETHER_ARP;
892 type |= RTE_PTYPE_L4_TCP;
895 type |= RTE_PTYPE_L4_UDP;
898 type |= RTE_PTYPE_L4_SCTP;
901 type |= RTE_PTYPE_L4_ICMP;
905 if (rxd_wb->pkt_type & BIT(5))
906 type |= RTE_PTYPE_L2_ETHER_VLAN;
912 atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
914 struct atl_rx_queue *rxq = (struct atl_rx_queue *)rx_queue;
915 struct rte_eth_dev *dev = &rte_eth_devices[rxq->port_id];
916 struct atl_adapter *adapter =
917 ATL_DEV_TO_ADAPTER(&rte_eth_devices[rxq->port_id]);
918 struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(adapter);
919 struct aq_hw_cfg_s *cfg =
920 ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private);
921 struct atl_rx_entry *sw_ring = rxq->sw_ring;
923 struct rte_mbuf *new_mbuf;
924 struct rte_mbuf *rx_mbuf, *rx_mbuf_prev, *rx_mbuf_first;
925 struct atl_rx_entry *rx_entry;
927 uint16_t nb_hold = 0;
928 struct hw_atl_rxd_wb_s rxd_wb;
929 struct hw_atl_rxd_s *rxd = NULL;
930 uint16_t tail = rxq->rx_tail;
932 uint16_t pkt_len = 0;
934 while (nb_rx < nb_pkts) {
935 uint16_t eop_tail = tail;
937 rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[tail];
938 rxd_wb = *(struct hw_atl_rxd_wb_s *)rxd;
940 if (!rxd_wb.dd) { /* RxD is not done */
944 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u tail=%u "
945 "eop=0x%x pkt_len=%u hash=0x%x hash_type=0x%x",
946 (unsigned int)rxq->port_id,
947 (unsigned int)rxq->queue_id,
948 (unsigned int)tail, (unsigned int)rxd_wb.eop,
949 (unsigned int)rte_le_to_cpu_16(rxd_wb.pkt_len),
950 rxd_wb.rss_hash, rxd_wb.rss_type);
952 /* RxD is not done */
955 struct hw_atl_rxd_wb_s *eop_rxwbd;
957 eop_tail = (eop_tail + 1) % rxq->nb_rx_desc;
958 eop_rxwbd = (struct hw_atl_rxd_wb_s *)
959 &rxq->hw_ring[eop_tail];
960 if (!eop_rxwbd->dd) {
961 /* no EOP received yet */
965 if (eop_rxwbd->dd && eop_rxwbd->eop)
969 if (eop_tail == tail)
973 rx_mbuf_first = NULL;
975 /* Run through packet segments */
977 new_mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
978 if (new_mbuf == NULL) {
980 "RX mbuf alloc failed port_id=%u "
981 "queue_id=%u", (unsigned int)rxq->port_id,
982 (unsigned int)rxq->queue_id);
983 dev->data->rx_mbuf_alloc_failed++;
984 adapter->sw_stats.rx_nombuf++;
989 rx_entry = &sw_ring[tail];
991 rx_mbuf = rx_entry->mbuf;
992 rx_entry->mbuf = new_mbuf;
993 dma_addr = rte_cpu_to_le_64(
994 rte_mbuf_data_iova_default(new_mbuf));
996 /* setup RX descriptor */
998 rxd->buf_addr = dma_addr;
1001 * Initialize the returned mbuf.
1002 * 1) setup generic mbuf fields:
1003 * - number of segments,
1006 * - RX port identifier.
1007 * 2) integrate hardware offload data, if any:
1008 * < - RSS flag & hash,
1009 * - IP checksum flag,
1010 * - VLAN TCI, if any,
1013 pkt_len = (uint16_t)rte_le_to_cpu_16(rxd_wb.pkt_len);
1014 rx_mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1015 rte_prefetch1((char *)rx_mbuf->buf_addr +
1017 rx_mbuf->nb_segs = 0;
1018 rx_mbuf->next = NULL;
1019 rx_mbuf->pkt_len = pkt_len;
1020 rx_mbuf->data_len = pkt_len;
1022 u16 remainder_len = pkt_len % rxq->buff_size;
1024 remainder_len = rxq->buff_size;
1025 rx_mbuf->data_len = remainder_len;
1027 rx_mbuf->data_len = pkt_len > rxq->buff_size ?
1028 rxq->buff_size : pkt_len;
1030 rx_mbuf->port = rxq->port_id;
1032 rx_mbuf->hash.rss = rxd_wb.rss_hash;
1034 rx_mbuf->vlan_tci = rxd_wb.vlan;
1037 atl_desc_to_offload_flags(rxq, &rxd_wb);
1039 rx_mbuf->packet_type = atl_desc_to_pkt_type(&rxd_wb);
1041 if (rx_mbuf->packet_type & RTE_PTYPE_L2_ETHER_VLAN) {
1042 rx_mbuf->ol_flags |= RTE_MBUF_F_RX_VLAN;
1043 rx_mbuf->vlan_tci = rxd_wb.vlan;
1045 if (cfg->vlan_strip)
1046 rx_mbuf->ol_flags |=
1047 RTE_MBUF_F_RX_VLAN_STRIPPED;
1051 rx_mbuf_first = rx_mbuf;
1052 rx_mbuf_first->nb_segs++;
1055 rx_mbuf_prev->next = rx_mbuf;
1056 rx_mbuf_prev = rx_mbuf;
1058 tail = (tail + 1) % rxq->nb_rx_desc;
1059 /* Prefetch next mbufs */
1060 rte_prefetch0(sw_ring[tail].mbuf);
1061 if ((tail & 0x3) == 0) {
1062 rte_prefetch0(&sw_ring[tail]);
1063 rte_prefetch0(&sw_ring[tail]);
1066 /* filled mbuf_first */
1069 rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[tail];
1070 rxd_wb = *(struct hw_atl_rxd_wb_s *)rxd;
1074 * Store the mbuf address into the next entry of the array
1075 * of returned packets.
1077 rx_pkts[nb_rx++] = rx_mbuf_first;
1078 adapter->sw_stats.q_ipackets[rxq->queue_id]++;
1079 adapter->sw_stats.q_ibytes[rxq->queue_id] +=
1080 rx_mbuf_first->pkt_len;
1082 PMD_RX_LOG(DEBUG, "add mbuf segs=%d pkt_len=%d",
1083 rx_mbuf_first->nb_segs,
1084 rx_mbuf_first->pkt_len);
1089 rxq->rx_tail = tail;
1092 * If the number of free RX descriptors is greater than the RX free
1093 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1095 * Update the RDT with the value of the last processed RX descriptor
1096 * minus 1, to guarantee that the RDT register is never equal to the
1097 * RDH register, which creates a "full" ring situtation from the
1098 * hardware point of view...
1100 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1101 if (nb_hold > rxq->rx_free_thresh) {
1102 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1103 "nb_hold=%u nb_rx=%u",
1104 (unsigned int)rxq->port_id, (unsigned int)rxq->queue_id,
1105 (unsigned int)tail, (unsigned int)nb_hold,
1106 (unsigned int)nb_rx);
1107 tail = (uint16_t)((tail == 0) ?
1108 (rxq->nb_rx_desc - 1) : (tail - 1));
1110 hw_atl_reg_rx_dma_desc_tail_ptr_set(hw, tail, rxq->queue_id);
1115 rxq->nb_rx_hold = nb_hold;
1121 atl_xmit_cleanup(struct atl_tx_queue *txq)
1123 struct atl_tx_entry *sw_ring;
1124 struct hw_atl_txd_s *txd;
1128 sw_ring = txq->sw_ring;
1129 int head = txq->tx_head;
1133 for (i = 0, cnt = head; ; i++) {
1134 txd = &txq->hw_ring[cnt];
1139 cnt = (cnt + 1) % txq->nb_tx_desc;
1140 if (cnt == txq->tx_tail)
1148 txd = &txq->hw_ring[head];
1150 struct atl_tx_entry *rx_entry = &sw_ring[head];
1152 if (rx_entry->mbuf) {
1153 rte_pktmbuf_free_seg(rx_entry->mbuf);
1154 rx_entry->mbuf = NULL;
1163 head = (head + 1) % txq->nb_tx_desc;
1167 txq->tx_head = head;
1172 atl_tso_setup(struct rte_mbuf *tx_pkt, union hw_atl_txc_s *txc)
1174 uint32_t tx_cmd = 0;
1175 uint64_t ol_flags = tx_pkt->ol_flags;
1177 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
1178 tx_cmd |= tx_desc_cmd_lso | tx_desc_cmd_l4cs;
1182 if (ol_flags & RTE_MBUF_F_TX_IPV6)
1185 txc->l2_len = tx_pkt->l2_len;
1186 txc->l3_len = tx_pkt->l3_len;
1187 txc->l4_len = tx_pkt->l4_len;
1189 txc->mss_len = tx_pkt->tso_segsz;
1192 if (ol_flags & RTE_MBUF_F_TX_VLAN) {
1193 tx_cmd |= tx_desc_cmd_vlan;
1194 txc->vlan_tag = tx_pkt->vlan_tci;
1198 txc->type = tx_desc_type_ctx;
1206 atl_setup_csum_offload(struct rte_mbuf *mbuf, struct hw_atl_txd_s *txd,
1209 txd->cmd |= tx_desc_cmd_fcs;
1210 txd->cmd |= (mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) ? tx_desc_cmd_ipv4 : 0;
1211 /* L4 csum requested */
1212 txd->cmd |= (mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) ? tx_desc_cmd_l4cs : 0;
1217 atl_xmit_pkt(struct aq_hw_s *hw, struct atl_tx_queue *txq,
1218 struct rte_mbuf *tx_pkt)
1220 struct atl_adapter *adapter =
1221 ATL_DEV_TO_ADAPTER(&rte_eth_devices[txq->port_id]);
1222 uint32_t pay_len = 0;
1224 struct atl_tx_entry *tx_entry;
1225 uint64_t buf_dma_addr;
1226 struct rte_mbuf *m_seg;
1227 union hw_atl_txc_s *txc = NULL;
1228 struct hw_atl_txd_s *txd = NULL;
1232 tail = txq->tx_tail;
1234 txc = (union hw_atl_txc_s *)&txq->hw_ring[tail];
1239 tx_cmd = atl_tso_setup(tx_pkt, txc);
1242 /* We've consumed the first desc, adjust counters */
1243 tail = (tail + 1) % txq->nb_tx_desc;
1244 txq->tx_tail = tail;
1247 txd = &txq->hw_ring[tail];
1250 txd = (struct hw_atl_txd_s *)txc;
1253 txd->ct_en = !!tx_cmd;
1255 txd->type = tx_desc_type_desc;
1257 atl_setup_csum_offload(tx_pkt, txd, tx_cmd);
1262 pay_len = tx_pkt->pkt_len;
1264 txd->pay_len = pay_len;
1266 for (m_seg = tx_pkt; m_seg; m_seg = m_seg->next) {
1267 if (desc_count > 0) {
1268 txd = &txq->hw_ring[tail];
1272 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1273 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
1275 txd->type = tx_desc_type_desc;
1276 txd->len = m_seg->data_len;
1277 txd->pay_len = pay_len;
1279 /* Store mbuf for freeing later */
1280 tx_entry = &txq->sw_ring[tail];
1283 rte_pktmbuf_free_seg(tx_entry->mbuf);
1284 tx_entry->mbuf = m_seg;
1286 tail = (tail + 1) % txq->nb_tx_desc;
1291 // Last descriptor requires EOP and WB
1293 txd->cmd |= tx_desc_cmd_wb;
1295 hw_atl_b0_hw_tx_ring_tail_update(hw, tail, txq->queue_id);
1297 txq->tx_tail = tail;
1299 txq->tx_free -= desc_count;
1301 adapter->sw_stats.q_opackets[txq->queue_id]++;
1302 adapter->sw_stats.q_obytes[txq->queue_id] += pay_len;
1306 atl_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1308 struct rte_eth_dev *dev = NULL;
1309 struct aq_hw_s *hw = NULL;
1310 struct atl_tx_queue *txq = tx_queue;
1311 struct rte_mbuf *tx_pkt;
1314 dev = &rte_eth_devices[txq->port_id];
1315 hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1318 "port %d txq %d pkts: %d tx_free=%d tx_tail=%d tx_head=%d",
1319 txq->port_id, txq->queue_id, nb_pkts, txq->tx_free,
1320 txq->tx_tail, txq->tx_head);
1322 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1323 tx_pkt = *tx_pkts++;
1325 /* Clean Tx queue if needed */
1326 if (txq->tx_free < txq->tx_free_thresh)
1327 atl_xmit_cleanup(txq);
1329 /* Check if we have enough free descriptors */
1330 if (txq->tx_free < tx_pkt->nb_segs)
1333 /* check mbuf is valid */
1334 if ((tx_pkt->nb_segs == 0) ||
1335 ((tx_pkt->nb_segs > 1) && (tx_pkt->next == NULL)))
1338 /* Send the packet */
1339 atl_xmit_pkt(hw, txq, tx_pkt);
1342 PMD_TX_LOG(DEBUG, "atl_xmit_pkts %d transmitted", nb_tx);