1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 /* Copyright (C) 2014-2017 aQuantia Corporation. */
4 /* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
6 #include "../atl_types.h"
9 #include "../atl_hw_regs.h"
10 #include "hw_atl_utils.h"
11 #include "hw_atl_llh.h"
12 #include "hw_atl_b0_internal.h"
13 #include "hw_atl_llh_internal.h"
14 #include "../atl_logs.h"
16 int hw_atl_b0_hw_reset(struct aq_hw_s *self)
20 err = hw_atl_utils_soft_reset(self);
24 self->aq_fw_ops->set_state(self, MPI_RESET);
29 static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
33 unsigned int i_priority = 0U;
34 bool is_rx_flow_control = false;
36 /* TPS Descriptor rate init */
37 hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
38 hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
41 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
43 /* TPS TC credits init */
44 hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
45 hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
47 hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
48 hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
49 hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
50 hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
53 buff_size = HW_ATL_B0_TXBUF_MAX;
55 hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
56 hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
60 hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
65 /* QoS Rx buf size per TC */
67 is_rx_flow_control = 0;
68 buff_size = HW_ATL_B0_RXBUF_MAX;
70 hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
71 hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
73 (1024U / 32U) * 66U) /
75 hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
77 (1024U / 32U) * 50U) /
79 hw_atl_rpb_rx_xoff_en_per_tc_set(self,
80 is_rx_flow_control ? 1U : 0U,
83 /* QoS 802.1p priority -> TC mapping */
84 for (i_priority = 8U; i_priority--;)
85 hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
87 return aq_hw_err_from_flags(self);
90 /* calc hash only in IPv4 header, regardless of presence of TCP */
91 #define pif_rpf_rss_ipv4_hdr_only_i (1 << 4)
92 /* calc hash only if TCP header and IPv4 */
93 #define pif_rpf_rss_ipv4_tcp_hdr_only_i (1 << 3)
94 /* calc hash only in IPv6 header, regardless of presence of TCP */
95 #define pif_rpf_rss_ipv6_hdr_only_i (1 << 2)
96 /* calc hash only if TCP header and IPv4 */
97 #define pif_rpf_rss_ipv6_tcp_hdr_only_i (1 << 1)
98 /* bug 5124 - rss hashing types - FIXME */
99 #define pif_rpf_rss_dont_use_udp_i (1 << 0)
101 static int hw_atl_b0_hw_rss_hash_type_set(struct aq_hw_s *self)
104 unsigned int control_reg_val =
105 IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U;
107 /* RSS hash type set for IP/TCP */
108 control_reg_val |= pif_rpf_rss_ipv4_hdr_only_i;//0x1EU;
110 aq_hw_write_reg(self, 0x5040U, control_reg_val);
112 return aq_hw_err_from_flags(self);
115 int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
116 struct aq_rss_parameters *rss_params)
118 struct aq_hw_cfg_s *cfg = self->aq_nic_cfg;
121 unsigned int addr = 0U;
123 for (i = 10, addr = 0U; i--; ++addr) {
124 u32 key_data = cfg->is_rss ?
125 htonl(rss_params->hash_secret_key[i]) : 0U;
126 hw_atl_rpf_rss_key_wr_data_set(self, key_data);
127 hw_atl_rpf_rss_key_addr_set(self, addr);
128 hw_atl_rpf_rss_key_wr_en_set(self, 1U);
129 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
135 /* RSS Ring selection */
136 hw_atl_reg_rx_flr_rss_control1set(self,
137 cfg->is_rss ? 0xB3333333U : 0x00000000U);
138 hw_atl_b0_hw_rss_hash_type_set(self);
140 err = aq_hw_err_from_flags(self);
147 int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
148 struct aq_rss_parameters *rss_params)
150 u8 *indirection_table = rss_params->indirection_table;
151 u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
158 for (i = 0; i < HW_ATL_B0_RSS_REDIRECTION_MAX; i++) {
159 val |= (u32)(indirection_table[i] % num_rss_queues) << shift;
165 hw_atl_rpf_rss_redir_tbl_wr_data_set(self, val & 0xffff);
166 hw_atl_rpf_rss_redir_tbl_addr_set(self, addr);
168 hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
169 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
184 static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self)
185 /*struct aq_nic_cfg_s *aq_nic_cfg)*/
189 /* TX checksums offloads*/
190 hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);
191 hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
193 /* RX checksums offloads*/
194 hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);
195 hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);
198 hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
202 unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :
203 ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :
204 ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));
206 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)
207 hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i);
209 hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU);
210 hw_atl_rpo_lro_inactive_interval_set(self, 0);
211 hw_atl_rpo_lro_max_coalescing_interval_set(self, 2);
213 hw_atl_rpo_lro_qsessions_lim_set(self, 1U);
215 hw_atl_rpo_lro_total_desc_lim_set(self, 2U);
217 hw_atl_rpo_lro_patch_optimization_en_set(self, 0U);
219 hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U);
221 hw_atl_rpo_lro_pkt_lim_set(self, 1U);
223 hw_atl_rpo_lro_en_set(self,
224 self->aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
226 return aq_hw_err_from_flags(self);
230 int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
232 /* Tx TC/RSS number config */
233 hw_atl_rpb_tps_tx_tc_mode_set(self, 1U);
235 hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
236 hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
237 hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
240 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
243 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
244 0x00010000U : 0x00000000U);
245 hw_atl_tdm_tx_dca_en_set(self, 0U);
246 hw_atl_tdm_tx_dca_mode_set(self, 0U);
248 hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
250 return aq_hw_err_from_flags(self);
254 int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
256 struct aq_hw_cfg_s *cfg = self->aq_nic_cfg;
259 /* Rx TC/RSS number config */
260 hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U); /* 1: 4TC/8Queues */
262 /* Rx flow control */
263 hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
265 /* RSS Ring selection */
266 hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
267 0xB3333333U : 0x00000000U);
269 /* Multicast filters */
270 for (i = HW_ATL_B0_MAC_MAX; i--;) {
271 hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
272 hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
275 hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
276 hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
279 hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
280 hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
282 /* VLAN proimisc bu defauld */
283 hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
286 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
288 hw_atl_b0_hw_rss_hash_type_set(self);
290 hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
291 hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
293 hw_atl_rdm_rx_dca_en_set(self, 0U);
294 hw_atl_rdm_rx_dca_mode_set(self, 0U);
296 return aq_hw_err_from_flags(self);
299 static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
309 h = (mac_addr[0] << 8) | (mac_addr[1]);
310 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
311 (mac_addr[4] << 8) | mac_addr[5];
313 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
314 hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
315 hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
316 hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
318 err = aq_hw_err_from_flags(self);
324 int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
326 static u32 aq_hw_atl_igcr_table_[4][2] = {
327 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_INVALID */
328 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
329 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
330 { 0x200000A2U, 0x200000A6U } /* AQ_IRQ_MSIX */
336 struct aq_hw_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
338 hw_atl_b0_hw_init_tx_path(self);
339 hw_atl_b0_hw_init_rx_path(self);
341 hw_atl_b0_hw_mac_addr_set(self, mac_addr);
343 self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);
344 self->aq_fw_ops->set_state(self, MPI_INIT);
346 hw_atl_b0_hw_qos_set(self);
347 hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
348 hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
350 /* Force limit MRRS on RDM/TDM to 2K */
351 val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR);
352 aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR,
353 (val & ~0x707) | 0x404);
355 /* TX DMA total request limit. B0 hardware is not capable to
356 * handle more than (8K-MRRS) incoming DMA data.
357 * Value 24 in 256byte units
359 aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24);
361 /* Reset link status and read out initial hardware counters */
362 self->aq_link_status.mbps = 0;
363 self->aq_fw_ops->update_stats(self);
365 err = aq_hw_err_from_flags(self);
370 hw_atl_reg_irq_glb_ctl_set(self,
371 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
372 [(aq_nic_cfg->vecs > 1U) ?
375 hw_atl_itr_irq_auto_masklsw_set(self, 0xffffffff);
378 hw_atl_reg_gen_irq_map_set(self, 0, 0);
379 hw_atl_reg_gen_irq_map_set(self, 0x80 | ATL_IRQ_CAUSE_LINK, 3);
381 hw_atl_b0_hw_offload_set(self);
387 int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, int index)
389 hw_atl_tdm_tx_desc_en_set(self, 1, index);
390 return aq_hw_err_from_flags(self);
393 int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, int index)
395 hw_atl_rdm_rx_desc_en_set(self, 1, index);
396 return aq_hw_err_from_flags(self);
399 int hw_atl_b0_hw_start(struct aq_hw_s *self)
401 hw_atl_tpb_tx_buff_en_set(self, 1);
402 hw_atl_rpb_rx_buff_en_set(self, 1);
403 return aq_hw_err_from_flags(self);
406 int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, int tail, int index)
408 hw_atl_reg_tx_dma_desc_tail_ptr_set(self, tail, index);
412 int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, uint64_t base_addr,
413 int index, int size, int buff_size, int cpu, int vec)
415 u32 dma_desc_addr_lsw = (u32)base_addr;
416 u32 dma_desc_addr_msw = (u32)(base_addr >> 32);
418 hw_atl_rdm_rx_desc_en_set(self, false, index);
420 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, index);
422 hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
425 hw_atl_reg_rx_dma_desc_base_addressmswset(self, dma_desc_addr_msw,
428 hw_atl_rdm_rx_desc_len_set(self, size / 8U, index);
430 hw_atl_rdm_rx_desc_data_buff_size_set(self, buff_size / 1024U, index);
432 hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, index);
433 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, index);
434 hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, index);
436 /* Rx ring set mode */
438 /* Mapping interrupt vector */
439 hw_atl_itr_irq_map_rx_set(self, vec, index);
440 hw_atl_itr_irq_map_en_rx_set(self, true, index);
442 hw_atl_rdm_cpu_id_set(self, cpu, index);
443 hw_atl_rdm_rx_desc_dca_en_set(self, 0U, index);
444 hw_atl_rdm_rx_head_dca_en_set(self, 0U, index);
445 hw_atl_rdm_rx_pld_dca_en_set(self, 0U, index);
447 return aq_hw_err_from_flags(self);
450 int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, uint64_t base_addr,
451 int index, int size, int cpu, int vec)
453 u32 dma_desc_lsw_addr = (u32)base_addr;
454 u32 dma_desc_msw_addr = (u32)(base_addr >> 32);
456 hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
459 hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
462 hw_atl_tdm_tx_desc_len_set(self, size / 8U, index);
464 hw_atl_b0_hw_tx_ring_tail_update(self, 0, index);
466 /* Set Tx threshold */
467 hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, index);
469 /* Mapping interrupt vector */
470 hw_atl_itr_irq_map_tx_set(self, vec, index);
471 hw_atl_itr_irq_map_en_tx_set(self, true, index);
473 hw_atl_tdm_cpu_id_set(self, cpu, index);
474 hw_atl_tdm_tx_desc_dca_en_set(self, 0U, index);
476 return aq_hw_err_from_flags(self);
479 int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
481 hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask));
482 return aq_hw_err_from_flags(self);
485 int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
487 hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
488 hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
490 return aq_hw_err_from_flags(self);
493 int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
495 *mask = hw_atl_itr_irq_statuslsw_get(self);
496 return aq_hw_err_from_flags(self);
499 int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, int index)
501 hw_atl_tdm_tx_desc_en_set(self, 0U, index);
502 return aq_hw_err_from_flags(self);
505 int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, int index)
507 hw_atl_rdm_rx_desc_en_set(self, 0U, index);
508 return aq_hw_err_from_flags(self);