1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */
2 /* Copyright (C) 2014-2017 aQuantia Corporation. */
4 /* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific
8 #ifndef HW_ATL_B0_INTERNAL_H
9 #define HW_ATL_B0_INTERNAL_H
12 #define HW_ATL_B0_MTU_JUMBO 16352U
13 #define HW_ATL_B0_MTU 1514U
15 #define HW_ATL_B0_TX_RINGS 4U
16 #define HW_ATL_B0_RX_RINGS 4U
18 #define HW_ATL_B0_RINGS_MAX 32U
19 #define HW_ATL_B0_TXD_SIZE (16U)
20 #define HW_ATL_B0_RXD_SIZE (16U)
22 #define HW_ATL_B0_MAC 0U
23 #define HW_ATL_B0_MAC_MIN 1U
24 #define HW_ATL_B0_MAC_MAX 33U
26 /* Maximum supported VLAN filters */
27 #define HW_ATL_B0_MAX_VLAN_IDS 16
29 /* UCAST/MCAST filters */
30 #define HW_ATL_B0_UCAST_FILTERS_MAX 38
31 #define HW_ATL_B0_MCAST_FILTERS_MAX 8
34 #define HW_ATL_B0_ERR_INT 8U
35 #define HW_ATL_B0_INT_MASK (0xFFFFFFFFU)
37 #define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000)
38 #define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000)
39 #define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000)
41 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001)
42 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002)
43 #define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0)
44 #define HW_ATL_B0_TXD_CTL_DD (0x00100000)
45 #define HW_ATL_B0_TXD_CTL_EOP (0x00200000)
47 #define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000)
49 #define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22)
50 #define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23)
51 #define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24)
52 #define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25)
53 #define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26)
54 #define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27)
55 #define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28)
57 #define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21)
58 #define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22)
60 #define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U
61 #define HW_ATL_B0_MPI_STATE_ADR 0x036CU
63 #define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU
64 #define HW_ATL_B0_MPI_SPEED_SHIFT 16U
66 #define HW_ATL_B0_TXBUF_MAX 160U
67 #define HW_ATL_B0_RXBUF_MAX 320U
69 #define HW_ATL_B0_RXD_BUF_SIZE_MAX (16 * 1024)
71 #define HW_ATL_B0_RSS_REDIRECTION_MAX 64U
72 #define HW_ATL_B0_RSS_REDIRECTION_BITS 3U
73 #define HW_ATL_B0_RSS_HASHKEY_BITS 320U
75 #define HW_ATL_B0_TCRSS_4_8 1
76 #define HW_ATL_B0_TC_MAX 1U
77 #define HW_ATL_B0_RSS_MAX 8U
79 #define HW_ATL_B0_LRO_RXD_MAX 2U
80 #define HW_ATL_B0_RS_SLIP_ENABLED 0U
82 /* (256k -1(max pay_len) - 54(header)) */
83 #define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U
85 /* (256k -1(max pay_len) - 74(header)) */
86 #define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U
88 #define HW_ATL_B0_CHIP_REVISION_B0 0xA0U
89 #define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU
91 #define HW_ATL_B0_FW_SEMA_RAM 0x2U
93 #define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00)
94 #define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000)
96 #define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007)
97 #define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008)
98 #define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0)
99 #define HW_ATL_B0_TXC_CTL_CMD (0x00F00000)
100 #define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000)
102 #define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000) /* L3LEN lsb */
103 #define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF) /* L3LE upper bits */
104 #define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00)
105 #define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000)
107 #define HW_ATL_B0_RXD_DD (0x1)
108 #define HW_ATL_B0_RXD_NCEA0 (0x1)
110 #define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F)
111 #define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0)
112 #define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000)
113 #define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000)
114 #define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000)
116 #define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001)
117 #define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002)
118 #define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C)
119 #define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004)
120 #define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008)
121 #define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010)
122 #define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0)
123 #define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000)
125 #define L2_FILTER_ACTION_DISCARD (0x0)
126 #define L2_FILTER_ACTION_HOST (0x1)
128 #define HW_ATL_B0_UCP_0X370_REG (0x370)
130 #define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10)
132 #define HW_ATL_INTR_MODER_MAX 0x1FF
133 #define HW_ATL_INTR_MODER_MIN 0xFF
135 #define HW_ATL_B0_MIN_RXD \
136 (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE))
137 #define HW_ATL_B0_MIN_TXD \
138 (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE))
140 #define HW_ATL_B0_MAX_RXD 8184U
141 #define HW_ATL_B0_MAX_TXD 8184U
143 /* HW layer capabilities */
145 #endif /* HW_ATL_B0_INTERNAL_H */