5f3f70847310f25cc0966d1ce753ceab26a298aa
[dpdk.git] / drivers / net / atlantic / hw_atl / hw_atl_utils.h
1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */
2 /* Copyright (C) 2014-2017 aQuantia Corporation. */
3
4 /* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware
5  * abstraction layer.
6  */
7
8 #ifndef HW_ATL_UTILS_H
9 #define HW_ATL_UTILS_H
10
11 #define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
12
13 /* Hardware tx descriptor */
14 struct hw_atl_txd_s {
15         u64 buf_addr;
16
17         union {
18                 struct {
19                         u32 type:3;
20                         u32:1;
21                         u32 len:16;
22                         u32 dd:1;
23                         u32 eop:1;
24                         u32 cmd:8;
25                         u32:14;
26                         u32 ct_idx:1;
27                         u32 ct_en:1;
28                         u32 pay_len:18;
29                 } __attribute__((__packed__));
30                 u64 flags;
31         };
32 } __attribute__((__packed__));
33
34 /* Hardware tx context descriptor */
35 union hw_atl_txc_s {
36         struct {
37                 u64 flags1;
38                 u64 flags2;
39         };
40
41         struct {
42                 u64:40;
43                 u32 tun_len:8;
44                 u32 out_len:16;
45                 u32 type:3;
46                 u32 idx:1;
47                 u32 vlan_tag:16;
48                 u32 cmd:4;
49                 u32 l2_len:7;
50                 u32 l3_len:9;
51                 u32 l4_len:8;
52                 u32 mss_len:16;
53         } __attribute__((__packed__));
54 } __attribute__((__packed__));
55
56 enum aq_tx_desc_type {
57         tx_desc_type_desc = 1,
58         tx_desc_type_ctx = 2,
59 };
60
61 enum aq_tx_desc_cmd {
62         tx_desc_cmd_vlan = 1,
63         tx_desc_cmd_fcs = 2,
64         tx_desc_cmd_ipv4 = 4,
65         tx_desc_cmd_l4cs = 8,
66         tx_desc_cmd_lso = 0x10,
67         tx_desc_cmd_wb = 0x20,
68 };
69
70
71 /* Hardware rx descriptor */
72 struct hw_atl_rxd_s {
73         u64 buf_addr;
74         u64 hdr_addr;
75 } __attribute__((__packed__));
76
77 /* Hardware rx descriptor writeback */
78 struct hw_atl_rxd_wb_s {
79         u32 rss_type:4;
80         u32 pkt_type:8;
81         u32 type:20;
82         u32 rss_hash;
83         u16 dd:1;
84         u16 eop:1;
85         u16 rx_stat:4;
86         u16 rx_estat:6;
87         u16 rsc_cnt:4;
88         u16 pkt_len;
89         u16 next_desc_ptr;
90         u16 vlan;
91 } __attribute__((__packed__));
92
93 struct hw_atl_stats_s {
94         u32 uprc;
95         u32 mprc;
96         u32 bprc;
97         u32 erpt;
98         u32 uptc;
99         u32 mptc;
100         u32 bptc;
101         u32 erpr;
102         u32 mbtc;
103         u32 bbtc;
104         u32 mbrc;
105         u32 bbrc;
106         u32 ubrc;
107         u32 ubtc;
108         u32 dpc;
109 } __attribute__((__packed__));
110
111 union ip_addr {
112         struct {
113                 u8 addr[16];
114         } v6;
115         struct {
116                 u8 padding[12];
117                 u8 addr[4];
118         } v4;
119 } __attribute__((__packed__));
120
121 struct hw_aq_atl_utils_fw_rpc {
122         u32 msg_id;
123
124         union {
125                 struct {
126                         u32 pong;
127                 } msg_ping;
128
129                 struct {
130                         u8 mac_addr[6];
131                         u32 ip_addr_cnt;
132
133                         struct {
134                                 union ip_addr addr;
135                                 union ip_addr mask;
136                         } ip[1];
137                 } msg_arp;
138
139                 struct {
140                         u32 len;
141                         u8 packet[1514U];
142                 } msg_inject;
143
144                 struct {
145                         u32 priority;
146                         u32 wol_packet_type;
147                         u32 pattern_id;
148                         u32 next_wol_pattern_offset;
149                         union {
150                                 struct {
151                                         u32 flags;
152                                         u8 ipv4_source_address[4];
153                                         u8 ipv4_dest_address[4];
154                                         u16 tcp_source_port_number;
155                                         u16 tcp_dest_port_number;
156                                 } ipv4_tcp_syn_parameters;
157
158                                 struct {
159                                         u32 flags;
160                                         u8 ipv6_source_address[16];
161                                         u8 ipv6_dest_address[16];
162                                         u16 tcp_source_port_number;
163                                         u16 tcp_dest_port_number;
164                                 } ipv6_tcp_syn_parameters;
165
166                                 struct {
167                                         u32 flags;
168                                 } eapol_request_id_message_parameters;
169
170                                 struct {
171                                         u32 flags;
172                                         u32 mask_offset;
173                                         u32 mask_size;
174                                         u32 pattern_offset;
175                                         u32 pattern_size;
176                                 } wol_bit_map_pattern;
177                                 struct {
178                                         u8 mac_addr[6];
179                                 } wol_magic_packet_pattern;
180
181                         } wol_pattern;
182                 } msg_wol;
183
184                 struct {
185                         u16 tc_quanta[8];
186                         u16 tc_threshold[8];
187                 } msg_msm_pfc_quantas;
188
189                 struct {
190                         union {
191                                 u32 pattern_mask;
192                                 struct {
193                                         u32 aq_pm_wol_reason_arp_v4_pkt : 1;
194                                         u32 aq_pm_wol_reason_ipv4_ping_pkt : 1;
195                                         u32 aq_pm_wol_reason_ipv6_ns_pkt : 1;
196                                         u32 aq_pm_wol_reason_ipv6_ping_pkt : 1;
197                                         u32 aq_pm_wol_reason_link_up : 1;
198                                         u32 aq_pm_wol_reason_link_down : 1;
199                                         u32 aq_pm_wol_reason_maximum : 1;
200                                 };
201                         };
202                         union {
203                                 u32 offload_mask;
204                         };
205                 } msg_enable_wakeup;
206
207                 struct {
208                         u32 priority;
209                         u32 protocol_offload_type;
210                         u32 protocol_offload_id;
211                         u32 next_protocol_offload_offset;
212
213                         union {
214                                 struct {
215                                         u32 flags;
216                                         u8 remote_ipv4_addr[4];
217                                         u8 host_ipv4_addr[4];
218                                         u8 mac_addr[6];
219                                 } ipv4_arp_params;
220                         };
221                 } msg_offload;
222
223                 struct {
224                         u32 id;
225                 } msg_del_id;
226
227         };
228 } __attribute__((__packed__));
229
230 struct hw_aq_atl_utils_mbox_header {
231         u32 version;
232         u32 transaction_id;
233         u32 error;
234 } __attribute__((__packed__));
235
236 struct hw_aq_info {
237         u8 reserved[6];
238         u16 phy_fault_code;
239         u16 phy_temperature;
240         u8 cable_len;
241         u8 reserved1;
242         u32 cable_diag_data[4];
243         u8 reserved2[32];
244         u32 caps_lo;
245         u32 caps_hi;
246 } __attribute__((__packed__));
247
248 struct hw_aq_atl_utils_mbox {
249         struct hw_aq_atl_utils_mbox_header header;
250         struct hw_atl_stats_s stats;
251         struct hw_aq_info info;
252 } __attribute__((__packed__));
253
254 /* fw2x */
255 typedef u16     in_port_t;
256 typedef u32     ip4_addr_t;
257 typedef int     int32_t;
258 typedef short   int16_t;
259 typedef u32     fw_offset_t;
260
261 struct ip6_addr {
262         u32 addr[4];
263 } __attribute__((__packed__));
264
265 struct offload_ka_v4 {
266         u32 timeout;
267         in_port_t local_port;
268         in_port_t remote_port;
269         u8 remote_mac_addr[6];
270         u16 win_size;
271         u32 seq_num;
272         u32 ack_num;
273         ip4_addr_t local_ip;
274         ip4_addr_t remote_ip;
275 } __attribute__((__packed__));
276
277 struct offload_ka_v6 {
278         u32 timeout;
279         in_port_t local_port;
280         in_port_t remote_port;
281         u8 remote_mac_addr[6];
282         u16 win_size;
283         u32 seq_num;
284         u32 ack_num;
285         struct ip6_addr local_ip;
286         struct ip6_addr remote_ip;
287 } __attribute__((__packed__));
288
289 struct offload_ip_info {
290         u8 v4_local_addr_count;
291         u8 v4_addr_count;
292         u8 v6_local_addr_count;
293         u8 v6_addr_count;
294         fw_offset_t v4_addr;
295         fw_offset_t v4_prefix;
296         fw_offset_t v6_addr;
297         fw_offset_t v6_prefix;
298 } __attribute__((__packed__));
299
300 struct offload_port_info {
301         u16 udp_port_count;
302         u16 tcp_port_count;
303         fw_offset_t udp_port;
304         fw_offset_t tcp_port;
305 } __attribute__((__packed__));
306
307 struct offload_ka_info {
308         u16 v4_ka_count;
309         u16 v6_ka_count;
310         u32 retry_count;
311         u32 retry_interval;
312         fw_offset_t v4_ka;
313         fw_offset_t v6_ka;
314 } __attribute__((__packed__));
315
316 struct offload_rr_info {
317         u32 rr_count;
318         u32 rr_buf_len;
319         fw_offset_t rr_id_x;
320         fw_offset_t rr_buf;
321 } __attribute__((__packed__));
322
323 struct offload_info {
324         u32 version;            // current version is 0x00000000
325         u32 len;                // The whole structure length
326                                 // including the variable-size buf
327         u8 mac_addr[6];         // 8 bytes to keep alignment. Only
328                                 // first 6 meaningful.
329
330         u8 reserved[2];
331
332         struct offload_ip_info ips;
333         struct offload_port_info ports;
334         struct offload_ka_info kas;
335         struct offload_rr_info rrs;
336         u8 buf[0];
337 } __attribute__((__packed__));
338
339 struct smbus_read_request {
340         u32 offset; /* not used */
341         u32 device_id;
342         u32 address;
343         u32 length;
344 } __attribute__((__packed__));
345
346 struct smbus_write_request {
347         u32 offset; /* not used */
348         u32 device_id;
349         u32 address;
350         u32 length;
351 } __attribute__((__packed__));
352
353 #define HAL_ATLANTIC_UTILS_CHIP_MIPS         0x00000001U
354 #define HAL_ATLANTIC_UTILS_CHIP_TPO2         0x00000002U
355 #define HAL_ATLANTIC_UTILS_CHIP_RPF2         0x00000004U
356 #define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ       0x00000010U
357 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0  0x01000000U
358 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0  0x02000000U
359 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1  0x04000000U
360
361
362 #define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
363         self->chip_features)
364
365 enum hal_atl_utils_fw_state_e {
366         MPI_DEINIT = 0,
367         MPI_RESET = 1,
368         MPI_INIT = 2,
369         MPI_POWER = 4,
370 };
371
372 #define HAL_ATLANTIC_RATE_10G        BIT(0)
373 #define HAL_ATLANTIC_RATE_5G         BIT(1)
374 #define HAL_ATLANTIC_RATE_5GSR       BIT(2)
375 #define HAL_ATLANTIC_RATE_2GS        BIT(3)
376 #define HAL_ATLANTIC_RATE_1G         BIT(4)
377 #define HAL_ATLANTIC_RATE_100M       BIT(5)
378 #define HAL_ATLANTIC_RATE_INVALID    BIT(6)
379
380 #define HAL_ATLANTIC_UTILS_FW_MSG_PING     1U
381 #define HAL_ATLANTIC_UTILS_FW_MSG_ARP      2U
382 #define HAL_ATLANTIC_UTILS_FW_MSG_INJECT   3U
383 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD 4U
384 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL 5U
385 #define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 6U
386 #define HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC  7U
387 #define HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING 8U
388 #define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD  9U
389 #define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL  10U
390 #define HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG   13U // 0xd
391
392 #define SMBUS_READ_REQUEST BIT(13)
393 #define SMBUS_WRITE_REQUEST BIT(14)
394 #define SMBUS_DEVICE_ID 0x50
395
396 enum hw_atl_fw2x_rate {
397         FW2X_RATE_100M    = 0x20,
398         FW2X_RATE_1G      = 0x100,
399         FW2X_RATE_2G5     = 0x200,
400         FW2X_RATE_5G      = 0x400,
401         FW2X_RATE_10G     = 0x800,
402 };
403
404 enum hw_atl_fw2x_caps_lo {
405         CAPS_LO_10BASET_HD = 0x00,
406         CAPS_LO_10BASET_FD,
407         CAPS_LO_100BASETX_HD,
408         CAPS_LO_100BASET4_HD,
409         CAPS_LO_100BASET2_HD,
410         CAPS_LO_100BASETX_FD,
411         CAPS_LO_100BASET2_FD,
412         CAPS_LO_1000BASET_HD,
413         CAPS_LO_1000BASET_FD,
414         CAPS_LO_2P5GBASET_FD,
415         CAPS_LO_5GBASET_FD,
416         CAPS_LO_10GBASET_FD,
417 };
418
419 enum hw_atl_fw2x_caps_hi {
420         CAPS_HI_RESERVED1 = 0x00,
421         CAPS_HI_10BASET_EEE,
422         CAPS_HI_RESERVED2,
423         CAPS_HI_PAUSE,
424         CAPS_HI_ASYMMETRIC_PAUSE,
425         CAPS_HI_100BASETX_EEE,
426         CAPS_HI_RESERVED3,
427         CAPS_HI_RESERVED4,
428         CAPS_HI_1000BASET_FD_EEE,
429         CAPS_HI_2P5GBASET_FD_EEE,
430         CAPS_HI_5GBASET_FD_EEE,
431         CAPS_HI_10GBASET_FD_EEE,
432         CAPS_HI_RESERVED5,
433         CAPS_HI_RESERVED6,
434         CAPS_HI_RESERVED7,
435         CAPS_HI_RESERVED8,
436         CAPS_HI_RESERVED9,
437         CAPS_HI_CABLE_DIAG,
438         CAPS_HI_TEMPERATURE,
439         CAPS_HI_DOWNSHIFT,
440         CAPS_HI_PTP_AVB_EN,
441         CAPS_HI_MEDIA_DETECT,
442         CAPS_HI_LINK_DROP,
443         CAPS_HI_SLEEP_PROXY,
444         CAPS_HI_WOL,
445         CAPS_HI_MAC_STOP,
446         CAPS_HI_EXT_LOOPBACK,
447         CAPS_HI_INT_LOOPBACK,
448         CAPS_HI_EFUSE_AGENT,
449         CAPS_HI_WOL_TIMER,
450         CAPS_HI_STATISTICS,
451         CAPS_HI_TRANSACTION_ID,
452 };
453
454 struct aq_hw_s;
455 struct aq_fw_ops;
456 struct aq_hw_link_status_s;
457
458 int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops);
459
460 int hw_atl_utils_soft_reset(struct aq_hw_s *self);
461
462 void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
463
464 int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
465                                struct hw_aq_atl_utils_mbox_header *pmbox);
466
467 void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
468                                  struct hw_aq_atl_utils_mbox *pmbox);
469
470 void hw_atl_utils_mpi_set(struct aq_hw_s *self,
471                           enum hal_atl_utils_fw_state_e state,
472                           u32 speed);
473
474 int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self);
475
476 unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps);
477
478 unsigned int hw_atl_utils_hw_get_reg_length(void);
479
480 int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
481                              u32 *regs_buff);
482
483 int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
484                               unsigned int power_state);
485
486 int hw_atl_utils_hw_deinit(struct aq_hw_s *self);
487
488 int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
489
490 int hw_atl_utils_update_stats(struct aq_hw_s *self);
491
492 struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self);
493
494 int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
495                                   u32 *p, u32 cnt);
496
497 int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
498                                 u32 cnt);
499
500 int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac);
501
502 int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size);
503
504 int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
505                     struct hw_aq_atl_utils_fw_rpc **rpc);
506
507 extern const struct aq_fw_ops aq_fw_1x_ops;
508 extern const struct aq_fw_ops aq_fw_2x_ops;
509
510 #endif /* HW_ATL_UTILS_H */