1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */
2 /* Copyright (C) 2014-2017 aQuantia Corporation. */
4 /* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware
11 #define BIT(x) (1UL << (x))
12 #define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
14 /* Hardware tx descriptor */
30 } __attribute__((__packed__));
33 } __attribute__((__packed__));
35 /* Hardware tx context descriptor */
54 } __attribute__((__packed__));
55 } __attribute__((__packed__));
57 enum aq_tx_desc_type {
58 tx_desc_type_desc = 1,
67 tx_desc_cmd_lso = 0x10,
68 tx_desc_cmd_wb = 0x20,
72 /* Hardware rx descriptor */
76 } __attribute__((__packed__));
78 /* Hardware rx descriptor writeback */
79 struct hw_atl_rxd_wb_s {
92 } __attribute__((__packed__));
94 struct hw_atl_stats_s {
110 } __attribute__((__packed__));
120 } __attribute__((__packed__));
122 struct hw_aq_atl_utils_fw_rpc {
149 u32 next_wol_pattern_offset;
153 u8 ipv4_source_address[4];
154 u8 ipv4_dest_address[4];
155 u16 tcp_source_port_number;
156 u16 tcp_dest_port_number;
157 } ipv4_tcp_syn_parameters;
161 u8 ipv6_source_address[16];
162 u8 ipv6_dest_address[16];
163 u16 tcp_source_port_number;
164 u16 tcp_dest_port_number;
165 } ipv6_tcp_syn_parameters;
169 } eapol_request_id_message_parameters;
177 } wol_bit_map_pattern;
180 } wol_magic_packet_pattern;
188 } msg_msm_pfc_quantas;
194 u32 aq_pm_wol_reason_arp_v4_pkt : 1;
195 u32 aq_pm_wol_reason_ipv4_ping_pkt : 1;
196 u32 aq_pm_wol_reason_ipv6_ns_pkt : 1;
197 u32 aq_pm_wol_reason_ipv6_ping_pkt : 1;
198 u32 aq_pm_wol_reason_link_up : 1;
199 u32 aq_pm_wol_reason_link_down : 1;
200 u32 aq_pm_wol_reason_maximum : 1;
210 u32 protocol_offload_type;
211 u32 protocol_offload_id;
212 u32 next_protocol_offload_offset;
217 u8 remote_ipv4_addr[4];
218 u8 host_ipv4_addr[4];
229 } __attribute__((__packed__));
231 struct hw_aq_atl_utils_mbox_header {
235 } __attribute__((__packed__));
243 u32 cable_diag_data[4];
247 } __attribute__((__packed__));
249 struct hw_aq_atl_utils_mbox {
250 struct hw_aq_atl_utils_mbox_header header;
251 struct hw_atl_stats_s stats;
252 struct hw_aq_info info;
253 } __attribute__((__packed__));
256 typedef u16 in_port_t;
257 typedef u32 ip4_addr_t;
259 typedef short int16_t;
260 typedef u32 fw_offset_t;
264 } __attribute__((__packed__));
266 struct offload_ka_v4 {
268 in_port_t local_port;
269 in_port_t remote_port;
270 u8 remote_mac_addr[6];
275 ip4_addr_t remote_ip;
276 } __attribute__((__packed__));
278 struct offload_ka_v6 {
280 in_port_t local_port;
281 in_port_t remote_port;
282 u8 remote_mac_addr[6];
286 struct ip6_addr local_ip;
287 struct ip6_addr remote_ip;
288 } __attribute__((__packed__));
290 struct offload_ip_info {
291 u8 v4_local_addr_count;
293 u8 v6_local_addr_count;
296 fw_offset_t v4_prefix;
298 fw_offset_t v6_prefix;
299 } __attribute__((__packed__));
301 struct offload_port_info {
304 fw_offset_t udp_port;
305 fw_offset_t tcp_port;
306 } __attribute__((__packed__));
308 struct offload_ka_info {
315 } __attribute__((__packed__));
317 struct offload_rr_info {
322 } __attribute__((__packed__));
324 struct offload_info {
325 u32 version; // current version is 0x00000000
326 u32 len; // The whole structure length
327 // including the variable-size buf
328 u8 mac_addr[6]; // 8 bytes to keep alignment. Only
329 // first 6 meaningful.
333 struct offload_ip_info ips;
334 struct offload_port_info ports;
335 struct offload_ka_info kas;
336 struct offload_rr_info rrs;
338 } __attribute__((__packed__));
340 struct smbus_read_request {
341 u32 offset; /* not used */
345 } __attribute__((__packed__));
347 struct smbus_write_request {
348 u32 offset; /* not used */
352 } __attribute__((__packed__));
354 #define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U
355 #define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U
356 #define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U
357 #define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ 0x00000010U
358 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 0x01000000U
359 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U
360 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 0x04000000U
363 #define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
366 enum hal_atl_utils_fw_state_e {
373 #define HAL_ATLANTIC_RATE_10G BIT(0)
374 #define HAL_ATLANTIC_RATE_5G BIT(1)
375 #define HAL_ATLANTIC_RATE_5GSR BIT(2)
376 #define HAL_ATLANTIC_RATE_2GS BIT(3)
377 #define HAL_ATLANTIC_RATE_1G BIT(4)
378 #define HAL_ATLANTIC_RATE_100M BIT(5)
379 #define HAL_ATLANTIC_RATE_INVALID BIT(6)
381 #define HAL_ATLANTIC_UTILS_FW_MSG_PING 1U
382 #define HAL_ATLANTIC_UTILS_FW_MSG_ARP 2U
383 #define HAL_ATLANTIC_UTILS_FW_MSG_INJECT 3U
384 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD 4U
385 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL 5U
386 #define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 6U
387 #define HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC 7U
388 #define HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING 8U
389 #define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD 9U
390 #define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL 10U
391 #define HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG 13U // 0xd
393 #define SMBUS_DEVICE_ID 0x50
395 enum hw_atl_fw2x_caps_lo {
396 CAPS_LO_10BASET_HD = 0x00,
398 CAPS_LO_100BASETX_HD,
399 CAPS_LO_100BASET4_HD,
400 CAPS_LO_100BASET2_HD,
401 CAPS_LO_100BASETX_FD,
402 CAPS_LO_100BASET2_FD,
403 CAPS_LO_1000BASET_HD,
404 CAPS_LO_1000BASET_FD,
405 CAPS_LO_2P5GBASET_FD,
414 enum hw_atl_fw2x_caps_hi {
415 CAPS_HI_RESERVED1 = 0x00,
419 CAPS_HI_ASYMMETRIC_PAUSE,
420 CAPS_HI_100BASETX_EEE,
423 CAPS_HI_1000BASET_FD_EEE,
424 CAPS_HI_2P5GBASET_FD_EEE,
425 CAPS_HI_5GBASET_FD_EEE,
426 CAPS_HI_10GBASET_FD_EEE,
436 CAPS_HI_MEDIA_DETECT,
441 CAPS_HI_EXT_LOOPBACK,
442 CAPS_HI_INT_LOOPBACK,
446 CAPS_HI_TRANSACTION_ID,
449 enum hw_atl_fw2x_rate {
450 FW2X_RATE_100M = BIT(CAPS_LO_100BASETX_FD),
451 FW2X_RATE_1G = BIT(CAPS_LO_1000BASET_FD),
452 FW2X_RATE_2G5 = BIT(CAPS_LO_2P5GBASET_FD),
453 FW2X_RATE_5G = BIT(CAPS_LO_5GBASET_FD),
454 FW2X_RATE_10G = BIT(CAPS_LO_10GBASET_FD),
459 struct aq_hw_link_status_s;
461 int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops);
463 int hw_atl_utils_soft_reset(struct aq_hw_s *self);
465 void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
467 int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
468 struct hw_aq_atl_utils_mbox_header *pmbox);
470 void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
471 struct hw_aq_atl_utils_mbox *pmbox);
473 void hw_atl_utils_mpi_set(struct aq_hw_s *self,
474 enum hal_atl_utils_fw_state_e state,
477 int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self);
479 unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps);
481 unsigned int hw_atl_utils_hw_get_reg_length(void);
483 int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
486 int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
487 unsigned int power_state);
489 int hw_atl_utils_hw_deinit(struct aq_hw_s *self);
491 int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
493 int hw_atl_utils_update_stats(struct aq_hw_s *self);
495 struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self);
497 int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
500 int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
503 int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac);
505 int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size);
507 int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
508 struct hw_aq_atl_utils_fw_rpc **rpc);
510 extern const struct aq_fw_ops aq_fw_1x_ops;
511 extern const struct aq_fw_ops aq_fw_2x_ops;
513 #endif /* HW_ATL_UTILS_H */