1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 /* Copyright (C) 2014-2017 aQuantia Corporation. */
4 /* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
5 * Atlantic hardware abstraction layer.
9 #include "../atl_hw_regs.h"
11 #include "../atl_types.h"
12 #include "hw_atl_utils.h"
13 #include "hw_atl_llh.h"
15 #define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
16 #define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
17 #define HW_ATL_FW2X_MPI_RPC_ADDR 0x334
19 #define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
20 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
21 #define HW_ATL_FW2X_MPI_LED_ADDR 0x31c
23 #define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
24 #define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
26 #define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY)
27 #define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL)
29 #define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE)
30 #define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE)
31 #define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE)
32 #define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE)
34 #define HAL_ATLANTIC_WOL_FILTERS_COUNT 8
35 #define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E
37 #define HW_ATL_FW_FEATURE_LED 0x03010026
39 struct fw2x_msg_wol_pattern {
42 } __attribute__((__packed__));
47 u8 magic_packet_enabled;
49 struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];
54 u32 link_down_timeout;
55 } __attribute__((__packed__));
57 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
58 static int aq_fw2x_set_state(struct aq_hw_s *self,
59 enum hal_atl_utils_fw_state_e state);
61 static int aq_fw2x_init(struct aq_hw_s *self)
64 struct hw_aq_atl_utils_mbox mbox;
66 /* check 10 times by 1ms */
67 AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
68 aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)),
70 AQ_HW_WAIT_FOR(0U != (self->rpc_addr =
71 aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)),
75 hw_atl_utils_mpi_read_stats(self, &mbox);
77 self->caps_lo = mbox.info.caps_lo;
82 static int aq_fw2x_deinit(struct aq_hw_s *self)
84 int err = aq_fw2x_set_link_speed(self, 0);
87 err = aq_fw2x_set_state(self, MPI_DEINIT);
92 static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
94 enum hw_atl_fw2x_rate rate = 0;
96 if (speed & AQ_NIC_RATE_10G)
97 rate |= FW2X_RATE_10G;
99 if (speed & AQ_NIC_RATE_5G)
100 rate |= FW2X_RATE_5G;
102 if (speed & AQ_NIC_RATE_5G5R)
103 rate |= FW2X_RATE_5G;
105 if (speed & AQ_NIC_RATE_2G5)
106 rate |= FW2X_RATE_2G5;
108 if (speed & AQ_NIC_RATE_1G)
109 rate |= FW2X_RATE_1G;
111 if (speed & AQ_NIC_RATE_100M)
112 rate |= FW2X_RATE_100M;
117 static u32 fw2x_to_eee_mask(u32 speed)
121 if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK)
122 rate |= AQ_NIC_RATE_EEE_10G;
124 if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK)
125 rate |= AQ_NIC_RATE_EEE_5G;
127 if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK)
128 rate |= AQ_NIC_RATE_EEE_2G5;
130 if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK)
131 rate |= AQ_NIC_RATE_EEE_1G;
136 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
138 u32 rate_mask = link_speed_mask_2fw2x_ratemask(speed);
139 u32 reg_val = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
140 u32 val = rate_mask | ((BIT(CAPS_LO_SMBUS_READ) |
141 BIT(CAPS_LO_SMBUS_WRITE) |
142 BIT(CAPS_LO_MACSEC)) & reg_val);
144 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
149 static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)
151 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)
152 *mpi_state |= BIT(CAPS_HI_PAUSE);
154 *mpi_state &= ~BIT(CAPS_HI_PAUSE);
156 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)
157 *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);
159 *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);
162 static int aq_fw2x_set_state(struct aq_hw_s *self,
163 enum hal_atl_utils_fw_state_e state)
165 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
169 mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
170 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
173 mpi_state |= BIT(CAPS_HI_LINK_DROP);
180 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
184 static int aq_fw2x_update_link_status(struct aq_hw_s *self)
186 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
187 u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
188 FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
189 struct aq_hw_link_status_s *link_status = &self->aq_link_status;
192 if (speed & FW2X_RATE_10G)
193 link_status->mbps = 10000;
194 else if (speed & FW2X_RATE_5G)
195 link_status->mbps = 5000;
196 else if (speed & FW2X_RATE_2G5)
197 link_status->mbps = 2500;
198 else if (speed & FW2X_RATE_1G)
199 link_status->mbps = 1000;
200 else if (speed & FW2X_RATE_100M)
201 link_status->mbps = 100;
203 link_status->mbps = 10000;
205 link_status->mbps = 0;
212 int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
217 u32 mac_addr[2] = { 0 };
218 u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
220 if (efuse_addr != 0) {
221 err = hw_atl_utils_fw_downld_dwords(self,
222 efuse_addr + (40U * 4U),
224 ARRAY_SIZE(mac_addr));
227 mac_addr[0] = rte_constant_bswap32(mac_addr[0]);
228 mac_addr[1] = rte_constant_bswap32(mac_addr[1]);
231 rte_ether_addr_copy((struct rte_ether_addr *)mac_addr,
232 (struct rte_ether_addr *)mac);
234 if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
235 unsigned int rnd = (uint32_t)rte_rand();
237 //get_random_bytes(&rnd, sizeof(unsigned int));
244 mac[5] = (u8)(0xFFU & l);
246 mac[4] = (u8)(0xFFU & l);
248 mac[3] = (u8)(0xFFU & l);
250 mac[2] = (u8)(0xFFU & l);
251 mac[1] = (u8)(0xFFU & h);
253 mac[0] = (u8)(0xFFU & h);
258 static int aq_fw2x_update_stats(struct aq_hw_s *self)
261 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
262 u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
264 /* Toggle statistics bit for FW to update */
265 mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
266 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
268 /* Wait FW to report back */
269 AQ_HW_WAIT_FOR(orig_stats_val !=
270 (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
271 BIT(CAPS_HI_STATISTICS)),
276 return hw_atl_utils_update_stats(self);
279 static int aq_fw2x_get_temp(struct aq_hw_s *self, int *temp)
282 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
283 u32 temp_val = mpi_opts & BIT(CAPS_HI_TEMPERATURE);
286 /* Toggle statistics bit for FW to 0x36C.18 (CAPS_HI_TEMPERATURE) */
287 mpi_opts = mpi_opts ^ BIT(CAPS_HI_TEMPERATURE);
288 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
290 /* Wait FW to report back */
291 AQ_HW_WAIT_FOR(temp_val !=
292 (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
293 BIT(CAPS_HI_TEMPERATURE)), 1U, 10000U);
294 err = hw_atl_utils_fw_downld_dwords(self,
296 offsetof(struct hw_aq_atl_utils_mbox, info) +
297 offsetof(struct hw_aq_info, phy_temperature),
299 sizeof(temp_res) / sizeof(u32));
304 *temp = temp_res * 100 / 256;
308 static int aq_fw2x_get_cable_len(struct aq_hw_s *self, int *cable_len)
313 err = hw_atl_utils_fw_downld_dwords(self,
315 offsetof(struct hw_aq_atl_utils_mbox, info) +
316 offsetof(struct hw_aq_info, phy_temperature),
318 sizeof(cable_len_res) / sizeof(u32));
323 *cable_len = (cable_len_res >> 16) & 0xFF;
331 static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
334 struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
335 struct offload_info *cfg = NULL;
336 unsigned int rpc_size = 0U;
339 rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg);
341 err = hw_atl_utils_fw_rpc_wait(self, &rpc);
345 memset(rpc, 0, rpc_size);
346 cfg = (struct offload_info *)(&rpc->msg_id + 1);
348 memcpy(cfg->mac_addr, mac, ETH_ALEN);
349 cfg->len = sizeof(*cfg);
351 /* Clear bit 0x36C.23 */
352 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
353 mpi_opts &= ~HW_ATL_FW2X_CAP_SLEEP_PROXY;
355 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
357 err = hw_atl_utils_fw_rpc_call(self, rpc_size);
361 /* Set bit 0x36C.23 */
362 mpi_opts |= HW_ATL_FW2X_CAP_SLEEP_PROXY;
363 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
365 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
366 HW_ATL_FW2X_CAP_SLEEP_PROXY), 1U, 10000U);
371 static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
374 struct fw2x_msg_wol *msg = NULL;
377 struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
379 err = hw_atl_utils_fw_rpc_wait(self, &rpc);
383 msg = (struct fw2x_msg_wol *)rpc;
385 msg->msg_id = HAL_ATLANTIC_UTILS_FW2X_MSG_WOL;
386 msg->magic_packet_enabled = true;
387 memcpy(msg->hw_addr, mac, ETH_ALEN);
389 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
390 mpi_opts &= ~(HW_ATL_FW2X_CAP_SLEEP_PROXY | HW_ATL_FW2X_CAP_WOL);
392 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
394 err = hw_atl_utils_fw_rpc_call(self, sizeof(*msg));
398 /* Set bit 0x36C.24 */
399 mpi_opts |= HW_ATL_FW2X_CAP_WOL;
400 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
402 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
403 HW_ATL_FW2X_CAP_WOL), 1U, 10000U);
408 static int aq_fw2x_set_power(struct aq_hw_s *self,
409 unsigned int power_state __rte_unused,
414 if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) {
415 err = aq_fw2x_set_sleep_proxy(self, mac);
418 err = aq_fw2x_set_wol_params(self, mac);
426 static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed)
428 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
429 mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK |
430 HW_ATL_FW2X_CAP_EEE_2G5_MASK | HW_ATL_FW2X_CAP_EEE_5G_MASK |
431 HW_ATL_FW2X_CAP_EEE_10G_MASK);
433 if (speed & AQ_NIC_RATE_EEE_10G)
434 mpi_opts |= HW_ATL_FW2X_CAP_EEE_10G_MASK;
436 if (speed & AQ_NIC_RATE_EEE_5G)
437 mpi_opts |= HW_ATL_FW2X_CAP_EEE_5G_MASK;
439 if (speed & AQ_NIC_RATE_EEE_2G5)
440 mpi_opts |= HW_ATL_FW2X_CAP_EEE_2G5_MASK;
442 if (speed & AQ_NIC_RATE_EEE_1G)
443 mpi_opts |= HW_ATL_FW2X_CAP_EEE_1G_MASK;
445 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
450 static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate,
451 u32 *supported_rates)
457 err = hw_atl_utils_fw_downld_dwords(self,
459 offsetof(struct hw_aq_atl_utils_mbox, info) +
460 offsetof(struct hw_aq_info, caps_hi),
462 sizeof(caps_hi) / sizeof(u32));
467 *supported_rates = fw2x_to_eee_mask(caps_hi);
469 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
470 *rate = fw2x_to_eee_mask(mpi_state);
475 static int aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fc)
477 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
479 *fc = ((mpi_state & BIT(CAPS_HI_PAUSE)) ? AQ_NIC_FC_RX : 0) |
480 ((mpi_state & BIT(CAPS_HI_ASYMMETRIC_PAUSE)) ? AQ_NIC_FC_TX : 0);
485 static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
487 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
489 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
491 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
496 static int aq_fw2x_led_control(struct aq_hw_s *self, u32 mode)
498 if (self->fw_ver_actual < HW_ATL_FW_FEATURE_LED)
501 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_LED_ADDR, mode);
505 static int aq_fw2x_get_eeprom(struct aq_hw_s *self, int dev_addr,
506 u32 *data, u32 len, u32 offset)
508 u32 bytes_remains = len % sizeof(u32);
509 u32 num_dwords = len / sizeof(u32);
510 struct smbus_request request;
515 if ((self->caps_lo & BIT(CAPS_LO_SMBUS_READ)) == 0)
519 request.device_id = dev_addr;
520 request.address = offset;
521 request.length = len;
523 /* Write SMBUS request to cfg memory */
524 err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
525 (u32 *)(void *)&request,
526 sizeof(request) / sizeof(u32));
531 /* Toggle 0x368.CAPS_LO_SMBUS_READ bit */
532 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
533 mpi_opts ^= BIT(CAPS_LO_SMBUS_READ);
535 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
537 /* Wait until REQUEST_BIT matched in 0x370 */
539 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
540 BIT(CAPS_LO_SMBUS_READ)) == (mpi_opts & BIT(CAPS_LO_SMBUS_READ)),
546 err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
548 sizeof(result) / sizeof(u32));
557 err = hw_atl_utils_fw_downld_dwords(self,
558 self->rpc_addr + sizeof(u32) * 2,
569 err = hw_atl_utils_fw_downld_dwords(self,
570 self->rpc_addr + (sizeof(u32) * 2) +
571 (num_dwords * sizeof(u32)),
578 rte_memcpy((u8 *)data + len - bytes_remains,
579 &val, bytes_remains);
586 static int aq_fw2x_set_eeprom(struct aq_hw_s *self, int dev_addr,
587 u32 *data, u32 len, u32 offset)
589 struct smbus_request request;
590 u32 mpi_opts, result = 0;
593 if ((self->caps_lo & BIT(CAPS_LO_SMBUS_WRITE)) == 0)
597 request.device_id = dev_addr;
598 request.address = offset;
599 request.length = len;
601 /* Write SMBUS request to cfg memory */
602 err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
603 (u32 *)(void *)&request,
604 sizeof(request) / sizeof(u32));
609 /* Write SMBUS data to cfg memory */
610 u32 num_dwords = len / sizeof(u32);
611 u32 bytes_remains = len % sizeof(u32);
614 err = hw_atl_utils_fw_upload_dwords(self,
615 self->rpc_addr + sizeof(request),
626 rte_memcpy(&val, (u8 *)data + (sizeof(u32) * num_dwords),
629 err = hw_atl_utils_fw_upload_dwords(self,
630 self->rpc_addr + sizeof(request) +
631 (num_dwords * sizeof(u32)),
639 /* Toggle 0x368.CAPS_LO_SMBUS_WRITE bit */
640 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
641 mpi_opts ^= BIT(CAPS_LO_SMBUS_WRITE);
643 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
645 /* Wait until REQUEST_BIT matched in 0x370 */
646 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
647 BIT(CAPS_LO_SMBUS_WRITE)) == (mpi_opts & BIT(CAPS_LO_SMBUS_WRITE)),
653 /* Read status of write operation */
654 err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
656 sizeof(result) / sizeof(u32));
667 static int aq_fw2x_send_macsec_request(struct aq_hw_s *self,
668 struct macsec_msg_fw_request *req,
669 struct macsec_msg_fw_response *response)
674 if (!req || !response)
677 if ((self->caps_lo & BIT(CAPS_LO_MACSEC)) == 0)
680 /* Write macsec request to cfg memory */
681 err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
683 RTE_ALIGN(sizeof(*req) / sizeof(u32), sizeof(u32)));
688 /* Toggle 0x368.CAPS_LO_MACSEC bit */
689 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
690 mpi_opts ^= BIT(CAPS_LO_MACSEC);
692 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
694 /* Wait until REQUEST_BIT matched in 0x370 */
695 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
696 BIT(CAPS_LO_MACSEC)) == (mpi_opts & BIT(CAPS_LO_MACSEC)),
702 /* Read status of write operation */
703 err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
704 (u32 *)(void *)response,
705 RTE_ALIGN(sizeof(*response) / sizeof(u32), sizeof(u32)));
710 const struct aq_fw_ops aq_fw_2x_ops = {
711 .init = aq_fw2x_init,
712 .deinit = aq_fw2x_deinit,
714 .get_mac_permanent = aq_fw2x_get_mac_permanent,
715 .set_link_speed = aq_fw2x_set_link_speed,
716 .set_state = aq_fw2x_set_state,
717 .update_link_status = aq_fw2x_update_link_status,
718 .update_stats = aq_fw2x_update_stats,
719 .set_power = aq_fw2x_set_power,
720 .get_temp = aq_fw2x_get_temp,
721 .get_cable_len = aq_fw2x_get_cable_len,
722 .set_eee_rate = aq_fw2x_set_eee_rate,
723 .get_eee_rate = aq_fw2x_get_eee_rate,
724 .get_flow_control = aq_fw2x_get_flow_control,
725 .set_flow_control = aq_fw2x_set_flow_control,
726 .led_control = aq_fw2x_led_control,
727 .get_eeprom = aq_fw2x_get_eeprom,
728 .set_eeprom = aq_fw2x_set_eeprom,
729 .send_macsec_req = aq_fw2x_send_macsec_request,