1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
13 #include <sys/queue.h>
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev.h>
28 #include "base/avf_prototype.h"
29 #include "base/avf_type.h"
34 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
36 /* The following constraints must be satisfied:
37 * thresh < rxq->nb_rx_desc
39 if (thresh >= nb_desc) {
40 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
48 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
49 uint16_t tx_free_thresh)
51 /* TX descriptors will have their RS bit set after tx_rs_thresh
52 * descriptors have been used. The TX descriptor ring will be cleaned
53 * after tx_free_thresh descriptors are used or if the number of
54 * descriptors required to transmit a packet is greater than the
55 * number of free TX descriptors.
57 * The following constraints must be satisfied:
58 * - tx_rs_thresh must be less than the size of the ring minus 2.
59 * - tx_free_thresh must be less than the size of the ring minus 3.
60 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
61 * - tx_rs_thresh must be a divisor of the ring size.
63 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
64 * race condition, hence the maximum threshold constraints. When set
65 * to zero use default values.
67 if (tx_rs_thresh >= (nb_desc - 2)) {
68 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
69 "number of TX descriptors (%u) minus 2",
70 tx_rs_thresh, nb_desc);
73 if (tx_free_thresh >= (nb_desc - 3)) {
74 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
75 "number of TX descriptors (%u) minus 3.",
76 tx_free_thresh, nb_desc);
79 if (tx_rs_thresh > tx_free_thresh) {
80 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
81 "equal to tx_free_thresh (%u).",
82 tx_rs_thresh, tx_free_thresh);
85 if ((nb_desc % tx_rs_thresh) != 0) {
86 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
87 "number of TX descriptors (%u).",
88 tx_rs_thresh, nb_desc);
95 #ifdef RTE_LIBRTE_AVF_INC_VECTOR
97 check_rx_vec_allow(struct avf_rx_queue *rxq)
99 if (rxq->rx_free_thresh >= AVF_VPMD_RX_MAX_BURST &&
100 rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
101 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
105 PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
110 check_tx_vec_allow(struct avf_tx_queue *txq)
112 if ((txq->txq_flags & AVF_SIMPLE_FLAGS) == AVF_SIMPLE_FLAGS &&
113 txq->rs_thresh >= AVF_VPMD_TX_MAX_BURST &&
114 txq->rs_thresh <= AVF_VPMD_TX_MAX_FREE_BUF) {
115 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
118 PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
124 check_rx_bulk_allow(struct avf_rx_queue *rxq)
128 if (!(rxq->rx_free_thresh >= AVF_RX_MAX_BURST)) {
129 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
130 "rxq->rx_free_thresh=%d, "
131 "AVF_RX_MAX_BURST=%d",
132 rxq->rx_free_thresh, AVF_RX_MAX_BURST);
134 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
135 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
136 "rxq->nb_rx_desc=%d, "
137 "rxq->rx_free_thresh=%d",
138 rxq->nb_rx_desc, rxq->rx_free_thresh);
145 reset_rx_queue(struct avf_rx_queue *rxq)
152 len = rxq->nb_rx_desc + AVF_RX_MAX_BURST;
154 for (i = 0; i < len * sizeof(union avf_rx_desc); i++)
155 ((volatile char *)rxq->rx_ring)[i] = 0;
157 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
159 for (i = 0; i < AVF_RX_MAX_BURST; i++)
160 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
163 rxq->rx_nb_avail = 0;
164 rxq->rx_next_avail = 0;
165 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
169 rxq->pkt_first_seg = NULL;
170 rxq->pkt_last_seg = NULL;
174 reset_tx_queue(struct avf_tx_queue *txq)
176 struct avf_tx_entry *txe;
177 uint16_t i, prev, size;
180 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
185 size = sizeof(struct avf_tx_desc) * txq->nb_tx_desc;
186 for (i = 0; i < size; i++)
187 ((volatile char *)txq->tx_ring)[i] = 0;
189 prev = (uint16_t)(txq->nb_tx_desc - 1);
190 for (i = 0; i < txq->nb_tx_desc; i++) {
191 txq->tx_ring[i].cmd_type_offset_bsz =
192 rte_cpu_to_le_64(AVF_TX_DESC_DTYPE_DESC_DONE);
195 txe[prev].next_id = i;
202 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
203 txq->nb_free = txq->nb_tx_desc - 1;
205 txq->next_dd = txq->rs_thresh - 1;
206 txq->next_rs = txq->rs_thresh - 1;
210 alloc_rxq_mbufs(struct avf_rx_queue *rxq)
212 volatile union avf_rx_desc *rxd;
213 struct rte_mbuf *mbuf = NULL;
217 for (i = 0; i < rxq->nb_rx_desc; i++) {
218 mbuf = rte_mbuf_raw_alloc(rxq->mp);
219 if (unlikely(!mbuf)) {
220 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
224 rte_mbuf_refcnt_set(mbuf, 1);
226 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
228 mbuf->port = rxq->port_id;
231 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
233 rxd = &rxq->rx_ring[i];
234 rxd->read.pkt_addr = dma_addr;
235 rxd->read.hdr_addr = 0;
236 #ifndef RTE_LIBRTE_AVF_16BYTE_RX_DESC
241 rxq->sw_ring[i] = mbuf;
248 release_rxq_mbufs(struct avf_rx_queue *rxq)
250 struct rte_mbuf *mbuf;
256 for (i = 0; i < rxq->nb_rx_desc; i++) {
257 if (rxq->sw_ring[i]) {
258 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
259 rxq->sw_ring[i] = NULL;
264 if (rxq->rx_nb_avail == 0)
266 for (i = 0; i < rxq->rx_nb_avail; i++) {
267 struct rte_mbuf *mbuf;
269 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
270 rte_pktmbuf_free_seg(mbuf);
272 rxq->rx_nb_avail = 0;
276 release_txq_mbufs(struct avf_tx_queue *txq)
280 if (!txq || !txq->sw_ring) {
281 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
285 for (i = 0; i < txq->nb_tx_desc; i++) {
286 if (txq->sw_ring[i].mbuf) {
287 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
288 txq->sw_ring[i].mbuf = NULL;
293 static const struct avf_rxq_ops def_rxq_ops = {
294 .release_mbufs = release_rxq_mbufs,
297 static const struct avf_txq_ops def_txq_ops = {
298 .release_mbufs = release_txq_mbufs,
302 avf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
303 uint16_t nb_desc, unsigned int socket_id,
304 const struct rte_eth_rxconf *rx_conf,
305 struct rte_mempool *mp)
307 struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
308 struct avf_adapter *ad =
309 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
310 struct avf_rx_queue *rxq;
311 const struct rte_memzone *mz;
314 uint16_t rx_free_thresh;
315 uint16_t base, bsf, tc_mapping;
317 PMD_INIT_FUNC_TRACE();
319 if (nb_desc % AVF_ALIGN_RING_DESC != 0 ||
320 nb_desc > AVF_MAX_RING_DESC ||
321 nb_desc < AVF_MIN_RING_DESC) {
322 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
327 /* Check free threshold */
328 rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
329 AVF_DEFAULT_RX_FREE_THRESH :
330 rx_conf->rx_free_thresh;
331 if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
334 /* Free memory if needed */
335 if (dev->data->rx_queues[queue_idx]) {
336 avf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
337 dev->data->rx_queues[queue_idx] = NULL;
340 /* Allocate the rx queue data structure */
341 rxq = rte_zmalloc_socket("avf rxq",
342 sizeof(struct avf_rx_queue),
346 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
347 "rx queue data structure");
352 rxq->nb_rx_desc = nb_desc;
353 rxq->rx_free_thresh = rx_free_thresh;
354 rxq->queue_id = queue_idx;
355 rxq->port_id = dev->data->port_id;
356 rxq->crc_len = 0; /* crc stripping by default */
357 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
360 len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
361 rxq->rx_buf_len = RTE_ALIGN(len, (1 << AVF_RXQ_CTX_DBUFF_SHIFT));
363 /* Allocate the software ring. */
364 len = nb_desc + AVF_RX_MAX_BURST;
366 rte_zmalloc_socket("avf rx sw ring",
367 sizeof(struct rte_mbuf *) * len,
371 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
376 /* Allocate the maximun number of RX ring hardware descriptor with
377 * a liitle more to support bulk allocate.
379 len = AVF_MAX_RING_DESC + AVF_RX_MAX_BURST;
380 ring_size = RTE_ALIGN(len * sizeof(union avf_rx_desc),
382 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
383 ring_size, AVF_RING_BASE_ALIGN,
386 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
387 rte_free(rxq->sw_ring);
391 /* Zero all the descriptors in the ring. */
392 memset(mz->addr, 0, ring_size);
393 rxq->rx_ring_phys_addr = mz->iova;
394 rxq->rx_ring = (union avf_rx_desc *)mz->addr;
399 dev->data->rx_queues[queue_idx] = rxq;
400 rxq->qrx_tail = hw->hw_addr + AVF_QRX_TAIL1(rxq->queue_id);
401 rxq->ops = &def_rxq_ops;
403 if (check_rx_bulk_allow(rxq) == TRUE) {
404 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
405 "satisfied. Rx Burst Bulk Alloc function will be "
406 "used on port=%d, queue=%d.",
407 rxq->port_id, rxq->queue_id);
409 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
410 "not satisfied, Scattered Rx is requested "
411 "on port=%d, queue=%d.",
412 rxq->port_id, rxq->queue_id);
413 ad->rx_bulk_alloc_allowed = false;
416 #ifdef RTE_LIBRTE_AVF_INC_VECTOR
417 if (check_rx_vec_allow(rxq) == FALSE)
418 ad->rx_vec_allowed = false;
424 avf_dev_tx_queue_setup(struct rte_eth_dev *dev,
427 unsigned int socket_id,
428 const struct rte_eth_txconf *tx_conf)
430 struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
431 struct avf_adapter *ad =
432 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
433 struct avf_tx_queue *txq;
434 const struct rte_memzone *mz;
436 uint16_t tx_rs_thresh, tx_free_thresh;
437 uint16_t i, base, bsf, tc_mapping;
439 PMD_INIT_FUNC_TRACE();
441 if (nb_desc % AVF_ALIGN_RING_DESC != 0 ||
442 nb_desc > AVF_MAX_RING_DESC ||
443 nb_desc < AVF_MIN_RING_DESC) {
444 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
449 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
450 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
451 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
452 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
453 check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
455 /* Free memory if needed. */
456 if (dev->data->tx_queues[queue_idx]) {
457 avf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
458 dev->data->tx_queues[queue_idx] = NULL;
461 /* Allocate the TX queue data structure. */
462 txq = rte_zmalloc_socket("avf txq",
463 sizeof(struct avf_tx_queue),
467 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
468 "tx queue structure");
472 txq->nb_tx_desc = nb_desc;
473 txq->rs_thresh = tx_rs_thresh;
474 txq->free_thresh = tx_free_thresh;
475 txq->queue_id = queue_idx;
476 txq->port_id = dev->data->port_id;
477 txq->txq_flags = tx_conf->txq_flags;
478 txq->tx_deferred_start = tx_conf->tx_deferred_start;
480 /* Allocate software ring */
482 rte_zmalloc_socket("avf tx sw ring",
483 sizeof(struct avf_tx_entry) * nb_desc,
487 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
492 /* Allocate TX hardware ring descriptors. */
493 ring_size = sizeof(struct avf_tx_desc) * AVF_MAX_RING_DESC;
494 ring_size = RTE_ALIGN(ring_size, AVF_DMA_MEM_ALIGN);
495 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
496 ring_size, AVF_RING_BASE_ALIGN,
499 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
500 rte_free(txq->sw_ring);
504 txq->tx_ring_phys_addr = mz->iova;
505 txq->tx_ring = (struct avf_tx_desc *)mz->addr;
510 dev->data->tx_queues[queue_idx] = txq;
511 txq->qtx_tail = hw->hw_addr + AVF_QTX_TAIL1(queue_idx);
512 txq->ops = &def_txq_ops;
514 #ifdef RTE_LIBRTE_AVF_INC_VECTOR
515 if (check_tx_vec_allow(txq) == FALSE)
516 ad->tx_vec_allowed = false;
523 avf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
525 struct avf_adapter *adapter =
526 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
527 struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
528 struct avf_rx_queue *rxq;
531 PMD_DRV_FUNC_TRACE();
533 if (rx_queue_id >= dev->data->nb_rx_queues)
536 rxq = dev->data->rx_queues[rx_queue_id];
538 err = alloc_rxq_mbufs(rxq);
540 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
546 /* Init the RX tail register. */
547 AVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
550 /* Ready to switch the queue on */
551 err = avf_switch_queue(adapter, rx_queue_id, TRUE, TRUE);
553 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
556 dev->data->rx_queue_state[rx_queue_id] =
557 RTE_ETH_QUEUE_STATE_STARTED;
563 avf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
565 struct avf_adapter *adapter =
566 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
567 struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
568 struct avf_tx_queue *txq;
571 PMD_DRV_FUNC_TRACE();
573 if (tx_queue_id >= dev->data->nb_tx_queues)
576 txq = dev->data->tx_queues[tx_queue_id];
578 /* Init the RX tail register. */
579 AVF_PCI_REG_WRITE(txq->qtx_tail, 0);
582 /* Ready to switch the queue on */
583 err = avf_switch_queue(adapter, tx_queue_id, FALSE, TRUE);
586 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
589 dev->data->tx_queue_state[tx_queue_id] =
590 RTE_ETH_QUEUE_STATE_STARTED;
596 avf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
598 struct avf_adapter *adapter =
599 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
600 struct avf_rx_queue *rxq;
603 PMD_DRV_FUNC_TRACE();
605 if (rx_queue_id >= dev->data->nb_rx_queues)
608 err = avf_switch_queue(adapter, rx_queue_id, TRUE, FALSE);
610 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
615 rxq = dev->data->rx_queues[rx_queue_id];
616 rxq->ops->release_mbufs(rxq);
618 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
624 avf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
626 struct avf_adapter *adapter =
627 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
628 struct avf_tx_queue *txq;
631 PMD_DRV_FUNC_TRACE();
633 if (tx_queue_id >= dev->data->nb_tx_queues)
636 err = avf_switch_queue(adapter, tx_queue_id, FALSE, FALSE);
638 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
643 txq = dev->data->tx_queues[tx_queue_id];
644 txq->ops->release_mbufs(txq);
646 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
652 avf_dev_rx_queue_release(void *rxq)
654 struct avf_rx_queue *q = (struct avf_rx_queue *)rxq;
659 q->ops->release_mbufs(q);
660 rte_free(q->sw_ring);
661 rte_memzone_free(q->mz);
666 avf_dev_tx_queue_release(void *txq)
668 struct avf_tx_queue *q = (struct avf_tx_queue *)txq;
673 q->ops->release_mbufs(q);
674 rte_free(q->sw_ring);
675 rte_memzone_free(q->mz);
680 avf_stop_queues(struct rte_eth_dev *dev)
682 struct avf_adapter *adapter =
683 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
684 struct avf_rx_queue *rxq;
685 struct avf_tx_queue *txq;
688 /* Stop All queues */
689 ret = avf_disable_queues(adapter);
691 PMD_DRV_LOG(WARNING, "Fail to stop queues");
693 for (i = 0; i < dev->data->nb_tx_queues; i++) {
694 txq = dev->data->tx_queues[i];
697 txq->ops->release_mbufs(txq);
699 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
701 for (i = 0; i < dev->data->nb_rx_queues; i++) {
702 rxq = dev->data->rx_queues[i];
705 rxq->ops->release_mbufs(rxq);
707 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
712 avf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union avf_rx_desc *rxdp)
714 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
715 (1 << AVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
716 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
718 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
724 /* Translate the rx descriptor status and error fields to pkt flags */
725 static inline uint64_t
726 avf_rxd_to_pkt_flags(uint64_t qword)
729 uint64_t error_bits = (qword >> AVF_RXD_QW1_ERROR_SHIFT);
731 #define AVF_RX_ERR_BITS 0x3f
733 /* Check if RSS_HASH */
734 flags = (((qword >> AVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
735 AVF_RX_DESC_FLTSTAT_RSS_HASH) ==
736 AVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
738 if (likely((error_bits & AVF_RX_ERR_BITS) == 0)) {
739 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
743 if (unlikely(error_bits & (1 << AVF_RX_DESC_ERROR_IPE_SHIFT)))
744 flags |= PKT_RX_IP_CKSUM_BAD;
746 flags |= PKT_RX_IP_CKSUM_GOOD;
748 if (unlikely(error_bits & (1 << AVF_RX_DESC_ERROR_L4E_SHIFT)))
749 flags |= PKT_RX_L4_CKSUM_BAD;
751 flags |= PKT_RX_L4_CKSUM_GOOD;
753 /* TODO: Oversize error bit is not processed here */
758 /* implement recv_pkts */
760 avf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
762 volatile union avf_rx_desc *rx_ring;
763 volatile union avf_rx_desc *rxdp;
764 struct avf_rx_queue *rxq;
765 union avf_rx_desc rxd;
766 struct rte_mbuf *rxe;
767 struct rte_eth_dev *dev;
768 struct rte_mbuf *rxm;
769 struct rte_mbuf *nmb;
773 uint16_t rx_packet_len;
774 uint16_t rx_id, nb_hold;
777 static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
779 [1] = RTE_PTYPE_L2_ETHER,
780 /* [2] - [21] reserved */
781 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
783 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
784 RTE_PTYPE_L4_NONFRAG,
785 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
788 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
790 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
792 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
794 /* All others reserved */
800 rx_id = rxq->rx_tail;
801 rx_ring = rxq->rx_ring;
803 while (nb_rx < nb_pkts) {
804 rxdp = &rx_ring[rx_id];
805 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
806 rx_status = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
807 AVF_RXD_QW1_STATUS_SHIFT;
809 /* Check the DD bit first */
810 if (!(rx_status & (1 << AVF_RX_DESC_STATUS_DD_SHIFT)))
812 AVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
814 nmb = rte_mbuf_raw_alloc(rxq->mp);
815 if (unlikely(!nmb)) {
816 dev = &rte_eth_devices[rxq->port_id];
817 dev->data->rx_mbuf_alloc_failed++;
818 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
819 "queue_id=%u", rxq->port_id, rxq->queue_id);
825 rxe = rxq->sw_ring[rx_id];
827 if (unlikely(rx_id == rxq->nb_rx_desc))
830 /* Prefetch next mbuf */
831 rte_prefetch0(rxq->sw_ring[rx_id]);
833 /* When next RX descriptor is on a cache line boundary,
834 * prefetch the next 4 RX descriptors and next 8 pointers
837 if ((rx_id & 0x3) == 0) {
838 rte_prefetch0(&rx_ring[rx_id]);
839 rte_prefetch0(rxq->sw_ring[rx_id]);
844 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
845 rxdp->read.hdr_addr = 0;
846 rxdp->read.pkt_addr = dma_addr;
848 rx_packet_len = ((qword1 & AVF_RXD_QW1_LENGTH_PBUF_MASK) >>
849 AVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
851 rxm->data_off = RTE_PKTMBUF_HEADROOM;
852 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
855 rxm->pkt_len = rx_packet_len;
856 rxm->data_len = rx_packet_len;
857 rxm->port = rxq->port_id;
859 avf_rxd_to_vlan_tci(rxm, &rxd);
860 pkt_flags = avf_rxd_to_pkt_flags(qword1);
862 ptype_tbl[(uint8_t)((qword1 &
863 AVF_RXD_QW1_PTYPE_MASK) >> AVF_RXD_QW1_PTYPE_SHIFT)];
865 if (pkt_flags & PKT_RX_RSS_HASH)
867 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
869 rxm->ol_flags |= pkt_flags;
871 rx_pkts[nb_rx++] = rxm;
873 rxq->rx_tail = rx_id;
875 /* If the number of free RX descriptors is greater than the RX free
876 * threshold of the queue, advance the receive tail register of queue.
877 * Update that register with the value of the last processed RX
878 * descriptor minus 1.
880 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
881 if (nb_hold > rxq->rx_free_thresh) {
882 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
883 "nb_hold=%u nb_rx=%u",
884 rxq->port_id, rxq->queue_id,
885 rx_id, nb_hold, nb_rx);
886 rx_id = (uint16_t)((rx_id == 0) ?
887 (rxq->nb_rx_desc - 1) : (rx_id - 1));
888 AVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
891 rxq->nb_rx_hold = nb_hold;
896 /* implement recv_scattered_pkts */
898 avf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
901 struct avf_rx_queue *rxq = rx_queue;
902 union avf_rx_desc rxd;
903 struct rte_mbuf *rxe;
904 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
905 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
906 struct rte_mbuf *nmb, *rxm;
907 uint16_t rx_id = rxq->rx_tail;
908 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
909 struct rte_eth_dev *dev;
915 volatile union avf_rx_desc *rx_ring = rxq->rx_ring;
916 volatile union avf_rx_desc *rxdp;
917 static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
919 [1] = RTE_PTYPE_L2_ETHER,
920 /* [2] - [21] reserved */
921 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
923 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
924 RTE_PTYPE_L4_NONFRAG,
925 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
928 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
930 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
932 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
934 /* All others reserved */
937 while (nb_rx < nb_pkts) {
938 rxdp = &rx_ring[rx_id];
939 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
940 rx_status = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
941 AVF_RXD_QW1_STATUS_SHIFT;
943 /* Check the DD bit */
944 if (!(rx_status & (1 << AVF_RX_DESC_STATUS_DD_SHIFT)))
946 AVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
948 nmb = rte_mbuf_raw_alloc(rxq->mp);
949 if (unlikely(!nmb)) {
950 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
951 "queue_id=%u", rxq->port_id, rxq->queue_id);
952 dev = &rte_eth_devices[rxq->port_id];
953 dev->data->rx_mbuf_alloc_failed++;
959 rxe = rxq->sw_ring[rx_id];
961 if (rx_id == rxq->nb_rx_desc)
964 /* Prefetch next mbuf */
965 rte_prefetch0(rxq->sw_ring[rx_id]);
967 /* When next RX descriptor is on a cache line boundary,
968 * prefetch the next 4 RX descriptors and next 8 pointers
971 if ((rx_id & 0x3) == 0) {
972 rte_prefetch0(&rx_ring[rx_id]);
973 rte_prefetch0(rxq->sw_ring[rx_id]);
979 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
981 /* Set data buffer address and data length of the mbuf */
982 rxdp->read.hdr_addr = 0;
983 rxdp->read.pkt_addr = dma_addr;
984 rx_packet_len = (qword1 & AVF_RXD_QW1_LENGTH_PBUF_MASK) >>
985 AVF_RXD_QW1_LENGTH_PBUF_SHIFT;
986 rxm->data_len = rx_packet_len;
987 rxm->data_off = RTE_PKTMBUF_HEADROOM;
989 /* If this is the first buffer of the received packet, set the
990 * pointer to the first mbuf of the packet and initialize its
991 * context. Otherwise, update the total length and the number
992 * of segments of the current scattered packet, and update the
993 * pointer to the last mbuf of the current packet.
997 first_seg->nb_segs = 1;
998 first_seg->pkt_len = rx_packet_len;
1000 first_seg->pkt_len =
1001 (uint16_t)(first_seg->pkt_len +
1003 first_seg->nb_segs++;
1004 last_seg->next = rxm;
1007 /* If this is not the last buffer of the received packet,
1008 * update the pointer to the last mbuf of the current scattered
1009 * packet and continue to parse the RX ring.
1011 if (!(rx_status & (1 << AVF_RX_DESC_STATUS_EOF_SHIFT))) {
1016 /* This is the last buffer of the received packet. If the CRC
1017 * is not stripped by the hardware:
1018 * - Subtract the CRC length from the total packet length.
1019 * - If the last buffer only contains the whole CRC or a part
1020 * of it, free the mbuf associated to the last buffer. If part
1021 * of the CRC is also contained in the previous mbuf, subtract
1022 * the length of that CRC part from the data length of the
1026 if (unlikely(rxq->crc_len > 0)) {
1027 first_seg->pkt_len -= ETHER_CRC_LEN;
1028 if (rx_packet_len <= ETHER_CRC_LEN) {
1029 rte_pktmbuf_free_seg(rxm);
1030 first_seg->nb_segs--;
1031 last_seg->data_len =
1032 (uint16_t)(last_seg->data_len -
1033 (ETHER_CRC_LEN - rx_packet_len));
1034 last_seg->next = NULL;
1036 rxm->data_len = (uint16_t)(rx_packet_len -
1040 first_seg->port = rxq->port_id;
1041 first_seg->ol_flags = 0;
1042 avf_rxd_to_vlan_tci(first_seg, &rxd);
1043 pkt_flags = avf_rxd_to_pkt_flags(qword1);
1044 first_seg->packet_type =
1045 ptype_tbl[(uint8_t)((qword1 &
1046 AVF_RXD_QW1_PTYPE_MASK) >> AVF_RXD_QW1_PTYPE_SHIFT)];
1048 if (pkt_flags & PKT_RX_RSS_HASH)
1049 first_seg->hash.rss =
1050 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1052 first_seg->ol_flags |= pkt_flags;
1054 /* Prefetch data of first segment, if configured to do so. */
1055 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1056 first_seg->data_off));
1057 rx_pkts[nb_rx++] = first_seg;
1061 /* Record index of the next RX descriptor to probe. */
1062 rxq->rx_tail = rx_id;
1063 rxq->pkt_first_seg = first_seg;
1064 rxq->pkt_last_seg = last_seg;
1066 /* If the number of free RX descriptors is greater than the RX free
1067 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1068 * register. Update the RDT with the value of the last processed RX
1069 * descriptor minus 1, to guarantee that the RDT register is never
1070 * equal to the RDH register, which creates a "full" ring situtation
1071 * from the hardware point of view.
1073 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1074 if (nb_hold > rxq->rx_free_thresh) {
1075 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1076 "nb_hold=%u nb_rx=%u",
1077 rxq->port_id, rxq->queue_id,
1078 rx_id, nb_hold, nb_rx);
1079 rx_id = (uint16_t)(rx_id == 0 ?
1080 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1081 AVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1084 rxq->nb_rx_hold = nb_hold;
1089 #define AVF_LOOK_AHEAD 8
1091 avf_rx_scan_hw_ring(struct avf_rx_queue *rxq)
1093 volatile union avf_rx_desc *rxdp;
1094 struct rte_mbuf **rxep;
1095 struct rte_mbuf *mb;
1099 int32_t s[AVF_LOOK_AHEAD], nb_dd;
1100 int32_t i, j, nb_rx = 0;
1102 static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
1104 [1] = RTE_PTYPE_L2_ETHER,
1105 /* [2] - [21] reserved */
1106 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1108 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1109 RTE_PTYPE_L4_NONFRAG,
1110 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1113 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1115 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1117 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1119 /* All others reserved */
1122 rxdp = &rxq->rx_ring[rxq->rx_tail];
1123 rxep = &rxq->sw_ring[rxq->rx_tail];
1125 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1126 rx_status = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
1127 AVF_RXD_QW1_STATUS_SHIFT;
1129 /* Make sure there is at least 1 packet to receive */
1130 if (!(rx_status & (1 << AVF_RX_DESC_STATUS_DD_SHIFT)))
1133 /* Scan LOOK_AHEAD descriptors at a time to determine which
1134 * descriptors reference packets that are ready to be received.
1136 for (i = 0; i < AVF_RX_MAX_BURST; i += AVF_LOOK_AHEAD,
1137 rxdp += AVF_LOOK_AHEAD, rxep += AVF_LOOK_AHEAD) {
1138 /* Read desc statuses backwards to avoid race condition */
1139 for (j = AVF_LOOK_AHEAD - 1; j >= 0; j--) {
1140 qword1 = rte_le_to_cpu_64(
1141 rxdp[j].wb.qword1.status_error_len);
1142 s[j] = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
1143 AVF_RXD_QW1_STATUS_SHIFT;
1148 /* Compute how many status bits were set */
1149 for (j = 0, nb_dd = 0; j < AVF_LOOK_AHEAD; j++)
1150 nb_dd += s[j] & (1 << AVF_RX_DESC_STATUS_DD_SHIFT);
1154 /* Translate descriptor info to mbuf parameters */
1155 for (j = 0; j < nb_dd; j++) {
1156 AVF_DUMP_RX_DESC(rxq, &rxdp[j],
1157 rxq->rx_tail + i * AVF_LOOK_AHEAD + j);
1160 qword1 = rte_le_to_cpu_64
1161 (rxdp[j].wb.qword1.status_error_len);
1162 pkt_len = ((qword1 & AVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1163 AVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1164 mb->data_len = pkt_len;
1165 mb->pkt_len = pkt_len;
1167 avf_rxd_to_vlan_tci(mb, &rxdp[j]);
1168 pkt_flags = avf_rxd_to_pkt_flags(qword1);
1170 ptype_tbl[(uint8_t)((qword1 &
1171 AVF_RXD_QW1_PTYPE_MASK) >>
1172 AVF_RXD_QW1_PTYPE_SHIFT)];
1174 if (pkt_flags & PKT_RX_RSS_HASH)
1175 mb->hash.rss = rte_le_to_cpu_32(
1176 rxdp[j].wb.qword0.hi_dword.rss);
1178 mb->ol_flags |= pkt_flags;
1181 for (j = 0; j < AVF_LOOK_AHEAD; j++)
1182 rxq->rx_stage[i + j] = rxep[j];
1184 if (nb_dd != AVF_LOOK_AHEAD)
1188 /* Clear software ring entries */
1189 for (i = 0; i < nb_rx; i++)
1190 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1195 static inline uint16_t
1196 avf_rx_fill_from_stage(struct avf_rx_queue *rxq,
1197 struct rte_mbuf **rx_pkts,
1201 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1203 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1205 for (i = 0; i < nb_pkts; i++)
1206 rx_pkts[i] = stage[i];
1208 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1209 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1215 avf_rx_alloc_bufs(struct avf_rx_queue *rxq)
1217 volatile union avf_rx_desc *rxdp;
1218 struct rte_mbuf **rxep;
1219 struct rte_mbuf *mb;
1220 uint16_t alloc_idx, i;
1224 /* Allocate buffers in bulk */
1225 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1226 (rxq->rx_free_thresh - 1));
1227 rxep = &rxq->sw_ring[alloc_idx];
1228 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1229 rxq->rx_free_thresh);
1230 if (unlikely(diag != 0)) {
1231 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1235 rxdp = &rxq->rx_ring[alloc_idx];
1236 for (i = 0; i < rxq->rx_free_thresh; i++) {
1237 if (likely(i < (rxq->rx_free_thresh - 1)))
1238 /* Prefetch next mbuf */
1239 rte_prefetch0(rxep[i + 1]);
1242 rte_mbuf_refcnt_set(mb, 1);
1244 mb->data_off = RTE_PKTMBUF_HEADROOM;
1246 mb->port = rxq->port_id;
1247 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1248 rxdp[i].read.hdr_addr = 0;
1249 rxdp[i].read.pkt_addr = dma_addr;
1252 /* Update rx tail register */
1254 AVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1256 rxq->rx_free_trigger =
1257 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1258 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1259 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1264 static inline uint16_t
1265 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1267 struct avf_rx_queue *rxq = (struct avf_rx_queue *)rx_queue;
1268 struct rte_eth_dev *dev;
1274 if (rxq->rx_nb_avail)
1275 return avf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1277 nb_rx = (uint16_t)avf_rx_scan_hw_ring(rxq);
1278 rxq->rx_next_avail = 0;
1279 rxq->rx_nb_avail = nb_rx;
1280 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1282 if (rxq->rx_tail > rxq->rx_free_trigger) {
1283 if (avf_rx_alloc_bufs(rxq) != 0) {
1286 /* TODO: count rx_mbuf_alloc_failed here */
1288 rxq->rx_nb_avail = 0;
1289 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1290 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1291 rxq->sw_ring[j] = rxq->rx_stage[i];
1297 if (rxq->rx_tail >= rxq->nb_rx_desc)
1300 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1301 rxq->port_id, rxq->queue_id,
1302 rxq->rx_tail, nb_rx);
1304 if (rxq->rx_nb_avail)
1305 return avf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1311 avf_recv_pkts_bulk_alloc(void *rx_queue,
1312 struct rte_mbuf **rx_pkts,
1315 uint16_t nb_rx = 0, n, count;
1317 if (unlikely(nb_pkts == 0))
1320 if (likely(nb_pkts <= AVF_RX_MAX_BURST))
1321 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1324 n = RTE_MIN(nb_pkts, AVF_RX_MAX_BURST);
1325 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1326 nb_rx = (uint16_t)(nb_rx + count);
1327 nb_pkts = (uint16_t)(nb_pkts - count);
1336 avf_xmit_cleanup(struct avf_tx_queue *txq)
1338 struct avf_tx_entry *sw_ring = txq->sw_ring;
1339 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1340 uint16_t nb_tx_desc = txq->nb_tx_desc;
1341 uint16_t desc_to_clean_to;
1342 uint16_t nb_tx_to_clean;
1344 volatile struct avf_tx_desc *txd = txq->tx_ring;
1346 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
1347 if (desc_to_clean_to >= nb_tx_desc)
1348 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1350 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1351 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
1352 rte_cpu_to_le_64(AVF_TXD_QW1_DTYPE_MASK)) !=
1353 rte_cpu_to_le_64(AVF_TX_DESC_DTYPE_DESC_DONE)) {
1354 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1355 "(port=%d queue=%d)", desc_to_clean_to,
1356 txq->port_id, txq->queue_id);
1360 if (last_desc_cleaned > desc_to_clean_to)
1361 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1364 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1367 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1369 txq->last_desc_cleaned = desc_to_clean_to;
1370 txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
1375 /* Check if the context descriptor is needed for TX offloading */
1376 static inline uint16_t
1377 avf_calc_context_desc(uint64_t flags)
1379 static uint64_t mask = PKT_TX_TCP_SEG;
1381 return (flags & mask) ? 1 : 0;
1385 avf_txd_enable_checksum(uint64_t ol_flags,
1387 uint32_t *td_offset,
1388 union avf_tx_offload tx_offload)
1391 *td_offset |= (tx_offload.l2_len >> 1) <<
1392 AVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1394 /* Enable L3 checksum offloads */
1395 if (ol_flags & PKT_TX_IP_CKSUM) {
1396 *td_cmd |= AVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
1397 *td_offset |= (tx_offload.l3_len >> 2) <<
1398 AVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1399 } else if (ol_flags & PKT_TX_IPV4) {
1400 *td_cmd |= AVF_TX_DESC_CMD_IIPT_IPV4;
1401 *td_offset |= (tx_offload.l3_len >> 2) <<
1402 AVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1403 } else if (ol_flags & PKT_TX_IPV6) {
1404 *td_cmd |= AVF_TX_DESC_CMD_IIPT_IPV6;
1405 *td_offset |= (tx_offload.l3_len >> 2) <<
1406 AVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1409 if (ol_flags & PKT_TX_TCP_SEG) {
1410 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_TCP;
1411 *td_offset |= (tx_offload.l4_len >> 2) <<
1412 AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1416 /* Enable L4 checksum offloads */
1417 switch (ol_flags & PKT_TX_L4_MASK) {
1418 case PKT_TX_TCP_CKSUM:
1419 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_TCP;
1420 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
1421 AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1423 case PKT_TX_SCTP_CKSUM:
1424 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_SCTP;
1425 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
1426 AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1428 case PKT_TX_UDP_CKSUM:
1429 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_UDP;
1430 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
1431 AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1438 /* set TSO context descriptor
1439 * support IP -> L4 and IP -> IP -> L4
1441 static inline uint64_t
1442 avf_set_tso_ctx(struct rte_mbuf *mbuf, union avf_tx_offload tx_offload)
1444 uint64_t ctx_desc = 0;
1445 uint32_t cd_cmd, hdr_len, cd_tso_len;
1447 if (!tx_offload.l4_len) {
1448 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1452 /* in case of non tunneling packet, the outer_l2_len and
1453 * outer_l3_len must be 0.
1455 hdr_len = tx_offload.l2_len +
1459 cd_cmd = AVF_TX_CTX_DESC_TSO;
1460 cd_tso_len = mbuf->pkt_len - hdr_len;
1461 ctx_desc |= ((uint64_t)cd_cmd << AVF_TXD_CTX_QW1_CMD_SHIFT) |
1462 ((uint64_t)cd_tso_len << AVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1463 ((uint64_t)mbuf->tso_segsz << AVF_TXD_CTX_QW1_MSS_SHIFT);
1468 /* Construct the tx flags */
1469 static inline uint64_t
1470 avf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
1473 return rte_cpu_to_le_64(AVF_TX_DESC_DTYPE_DATA |
1474 ((uint64_t)td_cmd << AVF_TXD_QW1_CMD_SHIFT) |
1475 ((uint64_t)td_offset <<
1476 AVF_TXD_QW1_OFFSET_SHIFT) |
1478 AVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
1479 ((uint64_t)td_tag <<
1480 AVF_TXD_QW1_L2TAG1_SHIFT));
1485 avf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1487 volatile struct avf_tx_desc *txd;
1488 volatile struct avf_tx_desc *txr;
1489 struct avf_tx_queue *txq;
1490 struct avf_tx_entry *sw_ring;
1491 struct avf_tx_entry *txe, *txn;
1492 struct rte_mbuf *tx_pkt;
1493 struct rte_mbuf *m_seg;
1504 uint64_t buf_dma_addr;
1505 union avf_tx_offload tx_offload = {0};
1508 sw_ring = txq->sw_ring;
1510 tx_id = txq->tx_tail;
1511 txe = &sw_ring[tx_id];
1513 /* Check if the descriptor ring needs to be cleaned. */
1514 if (txq->nb_free < txq->free_thresh)
1515 avf_xmit_cleanup(txq);
1517 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1522 tx_pkt = *tx_pkts++;
1523 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1525 ol_flags = tx_pkt->ol_flags;
1526 tx_offload.l2_len = tx_pkt->l2_len;
1527 tx_offload.l3_len = tx_pkt->l3_len;
1528 tx_offload.l4_len = tx_pkt->l4_len;
1529 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1531 /* Calculate the number of context descriptors needed. */
1532 nb_ctx = avf_calc_context_desc(ol_flags);
1534 /* The number of descriptors that must be allocated for
1535 * a packet equals to the number of the segments of that
1536 * packet plus 1 context descriptor if needed.
1538 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1539 tx_last = (uint16_t)(tx_id + nb_used - 1);
1542 if (tx_last >= txq->nb_tx_desc)
1543 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1545 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
1546 " tx_first=%u tx_last=%u",
1547 txq->port_id, txq->queue_id, tx_id, tx_last);
1549 if (nb_used > txq->nb_free) {
1550 if (avf_xmit_cleanup(txq)) {
1555 if (unlikely(nb_used > txq->rs_thresh)) {
1556 while (nb_used > txq->nb_free) {
1557 if (avf_xmit_cleanup(txq)) {
1566 /* Descriptor based VLAN insertion */
1567 if (ol_flags & PKT_TX_VLAN_PKT) {
1568 td_cmd |= AVF_TX_DESC_CMD_IL2TAG1;
1569 td_tag = tx_pkt->vlan_tci;
1572 /* According to datasheet, the bit2 is reserved and must be
1577 /* Enable checksum offloading */
1578 if (ol_flags & AVF_TX_CKSUM_OFFLOAD_MASK)
1579 avf_txd_enable_checksum(ol_flags, &td_cmd,
1580 &td_offset, tx_offload);
1583 /* Setup TX context descriptor if required */
1584 volatile struct avf_tx_context_desc *ctx_txd =
1585 (volatile struct avf_tx_context_desc *)
1587 uint16_t cd_l2tag2 = 0;
1588 uint64_t cd_type_cmd_tso_mss =
1589 AVF_TX_DESC_DTYPE_CONTEXT;
1591 txn = &sw_ring[txe->next_id];
1592 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1594 rte_pktmbuf_free_seg(txe->mbuf);
1599 if (ol_flags & PKT_TX_TCP_SEG)
1600 cd_type_cmd_tso_mss |=
1601 avf_set_tso_ctx(tx_pkt, tx_offload);
1603 AVF_DUMP_TX_DESC(txq, ctx_txd, tx_id);
1604 txe->last_id = tx_last;
1605 tx_id = txe->next_id;
1612 txn = &sw_ring[txe->next_id];
1615 rte_pktmbuf_free_seg(txe->mbuf);
1618 /* Setup TX Descriptor */
1619 slen = m_seg->data_len;
1620 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1621 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1622 txd->cmd_type_offset_bsz = avf_build_ctob(td_cmd,
1627 AVF_DUMP_TX_DESC(txq, txd, tx_id);
1628 txe->last_id = tx_last;
1629 tx_id = txe->next_id;
1631 m_seg = m_seg->next;
1634 /* The last packet data descriptor needs End Of Packet (EOP) */
1635 td_cmd |= AVF_TX_DESC_CMD_EOP;
1636 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
1637 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
1639 if (txq->nb_used >= txq->rs_thresh) {
1640 PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
1641 "%4u (port=%d queue=%d)",
1642 tx_last, txq->port_id, txq->queue_id);
1644 td_cmd |= AVF_TX_DESC_CMD_RS;
1646 /* Update txq RS bit counters */
1650 txd->cmd_type_offset_bsz |=
1651 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1652 AVF_TXD_QW1_CMD_SHIFT);
1653 AVF_DUMP_TX_DESC(txq, txd, tx_id);
1659 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1660 txq->port_id, txq->queue_id, tx_id, nb_tx);
1662 AVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1663 txq->tx_tail = tx_id;
1669 avf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1673 struct avf_tx_queue *txq = (struct avf_tx_queue *)tx_queue;
1678 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1679 ret = avf_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);
1689 /* TX prep functions */
1691 avf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1698 for (i = 0; i < nb_pkts; i++) {
1700 ol_flags = m->ol_flags;
1702 /* Check condition for nb_segs > AVF_TX_MAX_MTU_SEG. */
1703 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1704 if (m->nb_segs > AVF_TX_MAX_MTU_SEG) {
1705 rte_errno = -EINVAL;
1708 } else if ((m->tso_segsz < AVF_MIN_TSO_MSS) ||
1709 (m->tso_segsz > AVF_MAX_TSO_MSS)) {
1710 /* MSS outside the range are considered malicious */
1711 rte_errno = -EINVAL;
1715 if (ol_flags & AVF_TX_OFFLOAD_NOTSUP_MASK) {
1716 rte_errno = -ENOTSUP;
1720 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1721 ret = rte_validate_tx_offload(m);
1727 ret = rte_net_intel_cksum_prepare(m);
1737 /* choose rx function*/
1739 avf_set_rx_function(struct rte_eth_dev *dev)
1741 struct avf_adapter *adapter =
1742 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1743 struct avf_rx_queue *rxq;
1746 if (adapter->rx_vec_allowed) {
1747 if (dev->data->scattered_rx) {
1748 PMD_DRV_LOG(DEBUG, "Using Vector Scattered Rx callback"
1749 " (port=%d).", dev->data->port_id);
1750 dev->rx_pkt_burst = avf_recv_scattered_pkts_vec;
1752 PMD_DRV_LOG(DEBUG, "Using Vector Rx callback"
1753 " (port=%d).", dev->data->port_id);
1754 dev->rx_pkt_burst = avf_recv_pkts_vec;
1756 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1757 rxq = dev->data->rx_queues[i];
1760 avf_rxq_vec_setup(rxq);
1762 } else if (dev->data->scattered_rx) {
1763 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
1764 dev->data->port_id);
1765 dev->rx_pkt_burst = avf_recv_scattered_pkts;
1766 } else if (adapter->rx_bulk_alloc_allowed) {
1767 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
1768 dev->data->port_id);
1769 dev->rx_pkt_burst = avf_recv_pkts_bulk_alloc;
1771 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
1772 dev->data->port_id);
1773 dev->rx_pkt_burst = avf_recv_pkts;
1777 /* choose tx function*/
1779 avf_set_tx_function(struct rte_eth_dev *dev)
1781 struct avf_adapter *adapter =
1782 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1783 struct avf_tx_queue *txq;
1786 if (adapter->tx_vec_allowed) {
1787 PMD_DRV_LOG(DEBUG, "Using Vector Tx callback (port=%d).",
1788 dev->data->port_id);
1789 dev->tx_pkt_burst = avf_xmit_pkts_vec;
1790 dev->tx_pkt_prepare = NULL;
1791 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1792 txq = dev->data->tx_queues[i];
1795 avf_txq_vec_setup(txq);
1798 PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
1799 dev->data->port_id);
1800 dev->tx_pkt_burst = avf_xmit_pkts;
1801 dev->tx_pkt_prepare = avf_prep_pkts;
1806 avf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1807 struct rte_eth_rxq_info *qinfo)
1809 struct avf_rx_queue *rxq;
1811 rxq = dev->data->rx_queues[queue_id];
1813 qinfo->mp = rxq->mp;
1814 qinfo->scattered_rx = dev->data->scattered_rx;
1815 qinfo->nb_desc = rxq->nb_rx_desc;
1817 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1818 qinfo->conf.rx_drop_en = TRUE;
1819 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1823 avf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1824 struct rte_eth_txq_info *qinfo)
1826 struct avf_tx_queue *txq;
1828 txq = dev->data->tx_queues[queue_id];
1830 qinfo->nb_desc = txq->nb_tx_desc;
1832 qinfo->conf.tx_free_thresh = txq->free_thresh;
1833 qinfo->conf.tx_rs_thresh = txq->rs_thresh;
1834 qinfo->conf.txq_flags = txq->txq_flags;
1835 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1838 /* Get the number of used descriptors of a rx queue */
1840 avf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
1842 #define AVF_RXQ_SCAN_INTERVAL 4
1843 volatile union avf_rx_desc *rxdp;
1844 struct avf_rx_queue *rxq;
1847 rxq = dev->data->rx_queues[queue_id];
1848 rxdp = &rxq->rx_ring[rxq->rx_tail];
1849 while ((desc < rxq->nb_rx_desc) &&
1850 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1851 AVF_RXD_QW1_STATUS_MASK) >> AVF_RXD_QW1_STATUS_SHIFT) &
1852 (1 << AVF_RX_DESC_STATUS_DD_SHIFT)) {
1853 /* Check the DD bit of a rx descriptor of each 4 in a group,
1854 * to avoid checking too frequently and downgrading performance
1857 desc += AVF_RXQ_SCAN_INTERVAL;
1858 rxdp += AVF_RXQ_SCAN_INTERVAL;
1859 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1860 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1861 desc - rxq->nb_rx_desc]);
1868 avf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
1870 struct avf_rx_queue *rxq = rx_queue;
1871 volatile uint64_t *status;
1875 if (unlikely(offset >= rxq->nb_rx_desc))
1878 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1879 return RTE_ETH_RX_DESC_UNAVAIL;
1881 desc = rxq->rx_tail + offset;
1882 if (desc >= rxq->nb_rx_desc)
1883 desc -= rxq->nb_rx_desc;
1885 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1886 mask = rte_le_to_cpu_64((1ULL << AVF_RX_DESC_STATUS_DD_SHIFT)
1887 << AVF_RXD_QW1_STATUS_SHIFT);
1889 return RTE_ETH_RX_DESC_DONE;
1891 return RTE_ETH_RX_DESC_AVAIL;
1895 avf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
1897 struct avf_tx_queue *txq = tx_queue;
1898 volatile uint64_t *status;
1899 uint64_t mask, expect;
1902 if (unlikely(offset >= txq->nb_tx_desc))
1905 desc = txq->tx_tail + offset;
1906 /* go to next desc that has the RS bit */
1907 desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
1909 if (desc >= txq->nb_tx_desc) {
1910 desc -= txq->nb_tx_desc;
1911 if (desc >= txq->nb_tx_desc)
1912 desc -= txq->nb_tx_desc;
1915 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1916 mask = rte_le_to_cpu_64(AVF_TXD_QW1_DTYPE_MASK);
1917 expect = rte_cpu_to_le_64(
1918 AVF_TX_DESC_DTYPE_DESC_DONE << AVF_TXD_QW1_DTYPE_SHIFT);
1919 if ((*status & mask) == expect)
1920 return RTE_ETH_TX_DESC_DONE;
1922 return RTE_ETH_TX_DESC_FULL;
1925 uint16_t __attribute__((weak))
1926 avf_recv_pkts_vec(__rte_unused void *rx_queue,
1927 __rte_unused struct rte_mbuf **rx_pkts,
1928 __rte_unused uint16_t nb_pkts)
1933 uint16_t __attribute__((weak))
1934 avf_recv_scattered_pkts_vec(__rte_unused void *rx_queue,
1935 __rte_unused struct rte_mbuf **rx_pkts,
1936 __rte_unused uint16_t nb_pkts)
1941 uint16_t __attribute__((weak))
1942 avf_xmit_fixed_burst_vec(__rte_unused void *tx_queue,
1943 __rte_unused struct rte_mbuf **tx_pkts,
1944 __rte_unused uint16_t nb_pkts)
1949 int __attribute__((weak))
1950 avf_rxq_vec_setup(__rte_unused struct avf_rx_queue *rxq)
1955 int __attribute__((weak))
1956 avf_txq_vec_setup(__rte_unused struct avf_tx_queue *txq)