1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
8 /* In QLEN must be whole number of 32 descriptors. */
9 #define AVF_ALIGN_RING_DESC 32
10 #define AVF_MIN_RING_DESC 64
11 #define AVF_MAX_RING_DESC 4096
12 #define AVF_DMA_MEM_ALIGN 4096
13 /* Base address of the HW descriptor ring should be 128B aligned. */
14 #define AVF_RING_BASE_ALIGN 128
16 /* used for Rx Bulk Allocate */
17 #define AVF_RX_MAX_BURST 32
19 /* used for Vector PMD */
20 #define AVF_VPMD_RX_MAX_BURST 32
21 #define AVF_VPMD_TX_MAX_BURST 32
22 #define AVF_VPMD_DESCS_PER_LOOP 4
23 #define AVF_VPMD_TX_MAX_FREE_BUF 64
25 #define AVF_NO_VECTOR_FLAGS ( \
26 DEV_TX_OFFLOAD_MULTI_SEGS | \
27 DEV_TX_OFFLOAD_VLAN_INSERT | \
28 DEV_TX_OFFLOAD_SCTP_CKSUM | \
29 DEV_TX_OFFLOAD_UDP_CKSUM | \
30 DEV_TX_OFFLOAD_TCP_CKSUM)
32 #define DEFAULT_TX_RS_THRESH 32
33 #define DEFAULT_TX_FREE_THRESH 32
35 #define AVF_MIN_TSO_MSS 256
36 #define AVF_MAX_TSO_MSS 9668
37 #define AVF_TSO_MAX_SEG UINT8_MAX
38 #define AVF_TX_MAX_MTU_SEG 8
40 #define AVF_TX_CKSUM_OFFLOAD_MASK ( \
45 #define AVF_TX_OFFLOAD_MASK ( \
51 #define AVF_TX_OFFLOAD_NOTSUP_MASK \
52 (PKT_TX_OFFLOAD_MASK ^ AVF_TX_OFFLOAD_MASK)
54 /* HW desc structure, both 16-byte and 32-byte types are supported */
55 #ifdef RTE_LIBRTE_AVF_16BYTE_RX_DESC
56 #define avf_rx_desc avf_16byte_rx_desc
58 #define avf_rx_desc avf_32byte_rx_desc
62 void (*release_mbufs)(struct avf_rx_queue *rxq);
66 void (*release_mbufs)(struct avf_tx_queue *txq);
69 /* Structure associated with each Rx queue. */
71 struct rte_mempool *mp; /* mbuf pool to populate Rx ring */
72 const struct rte_memzone *mz; /* memzone for Rx ring */
73 volatile union avf_rx_desc *rx_ring; /* Rx ring virtual address */
74 uint64_t rx_ring_phys_addr; /* Rx ring DMA address */
75 struct rte_mbuf **sw_ring; /* address of SW ring */
76 uint16_t nb_rx_desc; /* ring length */
77 uint16_t rx_tail; /* current value of tail */
78 volatile uint8_t *qrx_tail; /* register address of tail */
79 uint16_t rx_free_thresh; /* max free RX desc to hold */
80 uint16_t nb_rx_hold; /* number of held free RX desc */
81 struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
82 struct rte_mbuf *pkt_last_seg; /* last segment of current packet */
83 struct rte_mbuf fake_mbuf; /* dummy mbuf */
86 uint16_t rxrearm_nb; /* number of remaining to be re-armed */
87 uint16_t rxrearm_start; /* the idx we start the re-arming from */
88 uint64_t mbuf_initializer; /* value to init mbufs */
91 uint16_t rx_nb_avail; /* number of staged packets ready */
92 uint16_t rx_next_avail; /* index of next staged packets */
93 uint16_t rx_free_trigger; /* triggers rx buffer allocation */
94 struct rte_mbuf *rx_stage[AVF_RX_MAX_BURST * 2]; /* store mbuf */
96 uint16_t port_id; /* device port ID */
97 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
98 uint16_t queue_id; /* Rx queue index */
99 uint16_t rx_buf_len; /* The packet buffer size */
100 uint16_t rx_hdr_len; /* The header buffer size */
101 uint16_t max_pkt_len; /* Maximum packet length */
103 bool q_set; /* if rx queue has been configured */
104 bool rx_deferred_start; /* don't start this queue in dev start */
105 const struct avf_rxq_ops *ops;
108 struct avf_tx_entry {
109 struct rte_mbuf *mbuf;
114 /* Structure associated with each TX queue. */
115 struct avf_tx_queue {
116 const struct rte_memzone *mz; /* memzone for Tx ring */
117 volatile struct avf_tx_desc *tx_ring; /* Tx ring virtual address */
118 uint64_t tx_ring_phys_addr; /* Tx ring DMA address */
119 struct avf_tx_entry *sw_ring; /* address array of SW ring */
120 uint16_t nb_tx_desc; /* ring length */
121 uint16_t tx_tail; /* current value of tail */
122 volatile uint8_t *qtx_tail; /* register address of tail */
123 /* number of used desc since RS bit set */
126 uint16_t last_desc_cleaned; /* last desc have been cleaned*/
127 uint16_t free_thresh;
133 uint16_t next_dd; /* next to set RS, for VPMD */
134 uint16_t next_rs; /* next to check DD, for VPMD */
136 bool q_set; /* if rx queue has been configured */
137 bool tx_deferred_start; /* don't start this queue in dev start */
138 const struct avf_txq_ops *ops;
141 /* Offload features */
142 union avf_tx_offload {
145 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
146 uint64_t l3_len:9; /* L3 (IP) Header Length. */
147 uint64_t l4_len:8; /* L4 Header Length. */
148 uint64_t tso_segsz:16; /* TCP TSO segment size */
149 /* uint64_t unused : 24; */
153 int avf_dev_rx_queue_setup(struct rte_eth_dev *dev,
156 unsigned int socket_id,
157 const struct rte_eth_rxconf *rx_conf,
158 struct rte_mempool *mp);
160 int avf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
161 int avf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
162 void avf_dev_rx_queue_release(void *rxq);
164 int avf_dev_tx_queue_setup(struct rte_eth_dev *dev,
167 unsigned int socket_id,
168 const struct rte_eth_txconf *tx_conf);
169 int avf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
170 int avf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
171 void avf_dev_tx_queue_release(void *txq);
172 void avf_stop_queues(struct rte_eth_dev *dev);
173 uint16_t avf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
175 uint16_t avf_recv_scattered_pkts(void *rx_queue,
176 struct rte_mbuf **rx_pkts,
178 uint16_t avf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
180 uint16_t avf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
182 void avf_set_rx_function(struct rte_eth_dev *dev);
183 void avf_set_tx_function(struct rte_eth_dev *dev);
184 void avf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
185 struct rte_eth_rxq_info *qinfo);
186 void avf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
187 struct rte_eth_txq_info *qinfo);
188 uint32_t avf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id);
189 int avf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
190 int avf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
192 uint16_t avf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
194 uint16_t avf_recv_scattered_pkts_vec(void *rx_queue,
195 struct rte_mbuf **rx_pkts,
197 uint16_t avf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
199 int avf_rxq_vec_setup(struct avf_rx_queue *rxq);
200 int avf_txq_vec_setup(struct avf_tx_queue *txq);
203 void avf_dump_rx_descriptor(struct avf_rx_queue *rxq,
207 #ifdef RTE_LIBRTE_AVF_16BYTE_RX_DESC
208 const union avf_16byte_rx_desc *rx_desc = desc;
210 printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
211 rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
212 rx_desc->read.hdr_addr);
214 const union avf_32byte_rx_desc *rx_desc = desc;
216 printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
217 " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
218 rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
219 rx_desc->read.rsvd1, rx_desc->read.rsvd2);
223 /* All the descriptors are 16 bytes, so just use one of them
224 * to print the qwords
227 void avf_dump_tx_descriptor(const struct avf_tx_queue *txq,
228 const void *desc, uint16_t tx_id)
231 const struct avf_tx_desc *tx_desc = desc;
232 enum avf_tx_desc_dtype_value type;
234 type = (enum avf_tx_desc_dtype_value)rte_le_to_cpu_64(
235 tx_desc->cmd_type_offset_bsz &
236 rte_cpu_to_le_64(AVF_TXD_QW1_DTYPE_MASK));
238 case AVF_TX_DESC_DTYPE_DATA:
239 name = "Tx_data_desc";
241 case AVF_TX_DESC_DTYPE_CONTEXT:
242 name = "Tx_context_desc";
245 name = "unknown_desc";
249 printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
250 txq->queue_id, name, tx_id, tx_desc->buffer_addr,
251 tx_desc->cmd_type_offset_bsz);
254 #ifdef DEBUG_DUMP_DESC
255 #define AVF_DUMP_RX_DESC(rxq, desc, rx_id) \
256 avf_dump_rx_descriptor(rxq, desc, rx_id)
257 #define AVF_DUMP_TX_DESC(txq, desc, tx_id) \
258 avf_dump_tx_descriptor(txq, desc, tx_id)
260 #define AVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
261 #define AVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
264 #endif /* _AVF_RXTX_H_ */