1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
8 /* In QLEN must be whole number of 32 descriptors. */
9 #define AVF_ALIGN_RING_DESC 32
10 #define AVF_MIN_RING_DESC 64
11 #define AVF_MAX_RING_DESC 4096
12 #define AVF_DMA_MEM_ALIGN 4096
13 /* Base address of the HW descriptor ring should be 128B aligned. */
14 #define AVF_RING_BASE_ALIGN 128
16 /* used for Rx Bulk Allocate */
17 #define AVF_RX_MAX_BURST 32
19 #define DEFAULT_TX_RS_THRESH 32
20 #define DEFAULT_TX_FREE_THRESH 32
22 /* HW desc structure, both 16-byte and 32-byte types are supported */
23 #ifdef RTE_LIBRTE_AVF_16BYTE_RX_DESC
24 #define avf_rx_desc avf_16byte_rx_desc
26 #define avf_rx_desc avf_32byte_rx_desc
29 /* Structure associated with each Rx queue. */
31 struct rte_mempool *mp; /* mbuf pool to populate Rx ring */
32 const struct rte_memzone *mz; /* memzone for Rx ring */
33 volatile union avf_rx_desc *rx_ring; /* Rx ring virtual address */
34 uint64_t rx_ring_phys_addr; /* Rx ring DMA address */
35 struct rte_mbuf **sw_ring; /* address of SW ring */
36 uint16_t nb_rx_desc; /* ring length */
37 uint16_t rx_tail; /* current value of tail */
38 volatile uint8_t *qrx_tail; /* register address of tail */
39 uint16_t rx_free_thresh; /* max free RX desc to hold */
40 uint16_t nb_rx_hold; /* number of held free RX desc */
41 struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
42 struct rte_mbuf *pkt_last_seg; /* last segment of current packet */
43 struct rte_mbuf fake_mbuf; /* dummy mbuf */
45 uint16_t port_id; /* device port ID */
46 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
47 uint16_t queue_id; /* Rx queue index */
48 uint16_t rx_buf_len; /* The packet buffer size */
49 uint16_t rx_hdr_len; /* The header buffer size */
50 uint16_t max_pkt_len; /* Maximum packet length */
52 bool q_set; /* if rx queue has been configured */
53 bool rx_deferred_start; /* don't start this queue in dev start */
57 struct rte_mbuf *mbuf;
62 /* Structure associated with each TX queue. */
64 const struct rte_memzone *mz; /* memzone for Tx ring */
65 volatile struct avf_tx_desc *tx_ring; /* Tx ring virtual address */
66 uint64_t tx_ring_phys_addr; /* Tx ring DMA address */
67 struct avf_tx_entry *sw_ring; /* address array of SW ring */
68 uint16_t nb_tx_desc; /* ring length */
69 uint16_t tx_tail; /* current value of tail */
70 volatile uint8_t *qtx_tail; /* register address of tail */
71 /* number of used desc since RS bit set */
74 uint16_t last_desc_cleaned; /* last desc have been cleaned*/
81 uint16_t next_dd; /* next to set RS, for VPMD */
82 uint16_t next_rs; /* next to check DD, for VPMD */
84 bool q_set; /* if rx queue has been configured */
85 bool tx_deferred_start; /* don't start this queue in dev start */
88 int avf_dev_rx_queue_setup(struct rte_eth_dev *dev,
91 unsigned int socket_id,
92 const struct rte_eth_rxconf *rx_conf,
93 struct rte_mempool *mp);
95 int avf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
96 int avf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
97 void avf_dev_rx_queue_release(void *rxq);
99 int avf_dev_tx_queue_setup(struct rte_eth_dev *dev,
102 unsigned int socket_id,
103 const struct rte_eth_txconf *tx_conf);
104 int avf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
105 int avf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
106 void avf_dev_tx_queue_release(void *txq);
107 void avf_stop_queues(struct rte_eth_dev *dev);
110 void avf_dump_rx_descriptor(struct avf_rx_queue *rxq,
114 #ifdef RTE_LIBRTE_AVF_16BYTE_RX_DESC
115 const union avf_16byte_rx_desc *rx_desc = desc;
117 printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
118 rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
119 rx_desc->read.hdr_addr);
121 const union avf_32byte_rx_desc *rx_desc = desc;
123 printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
124 " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
125 rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
126 rx_desc->read.rsvd1, rx_desc->read.rsvd2);
130 /* All the descriptors are 16 bytes, so just use one of them
131 * to print the qwords
134 void avf_dump_tx_descriptor(const struct avf_tx_queue *txq,
135 const void *desc, uint16_t tx_id)
138 const struct avf_tx_desc *tx_desc = desc;
139 enum avf_tx_desc_dtype_value type;
141 type = (enum avf_tx_desc_dtype_value)rte_le_to_cpu_64(
142 tx_desc->cmd_type_offset_bsz &
143 rte_cpu_to_le_64(AVF_TXD_QW1_DTYPE_MASK));
145 case AVF_TX_DESC_DTYPE_DATA:
146 name = "Tx_data_desc";
148 case AVF_TX_DESC_DTYPE_CONTEXT:
149 name = "Tx_context_desc";
152 name = "unknown_desc";
156 printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
157 txq->queue_id, name, tx_id, tx_desc->buffer_addr,
158 tx_desc->cmd_type_offset_bsz);
160 #endif /* _AVF_RXTX_H_ */