1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
8 /* In QLEN must be whole number of 32 descriptors. */
9 #define AVF_ALIGN_RING_DESC 32
10 #define AVF_MIN_RING_DESC 64
11 #define AVF_MAX_RING_DESC 4096
12 #define AVF_DMA_MEM_ALIGN 4096
13 /* Base address of the HW descriptor ring should be 128B aligned. */
14 #define AVF_RING_BASE_ALIGN 128
16 /* used for Rx Bulk Allocate */
17 #define AVF_RX_MAX_BURST 32
19 #define DEFAULT_TX_RS_THRESH 32
20 #define DEFAULT_TX_FREE_THRESH 32
22 #define AVF_MIN_TSO_MSS 256
23 #define AVF_MAX_TSO_MSS 9668
24 #define AVF_TSO_MAX_SEG UINT8_MAX
25 #define AVF_TX_MAX_MTU_SEG 8
27 #define AVF_TX_CKSUM_OFFLOAD_MASK ( \
32 #define AVF_TX_OFFLOAD_MASK ( \
38 #define AVF_TX_OFFLOAD_NOTSUP_MASK \
39 (PKT_TX_OFFLOAD_MASK ^ AVF_TX_OFFLOAD_MASK)
41 /* HW desc structure, both 16-byte and 32-byte types are supported */
42 #ifdef RTE_LIBRTE_AVF_16BYTE_RX_DESC
43 #define avf_rx_desc avf_16byte_rx_desc
45 #define avf_rx_desc avf_32byte_rx_desc
48 /* Structure associated with each Rx queue. */
50 struct rte_mempool *mp; /* mbuf pool to populate Rx ring */
51 const struct rte_memzone *mz; /* memzone for Rx ring */
52 volatile union avf_rx_desc *rx_ring; /* Rx ring virtual address */
53 uint64_t rx_ring_phys_addr; /* Rx ring DMA address */
54 struct rte_mbuf **sw_ring; /* address of SW ring */
55 uint16_t nb_rx_desc; /* ring length */
56 uint16_t rx_tail; /* current value of tail */
57 volatile uint8_t *qrx_tail; /* register address of tail */
58 uint16_t rx_free_thresh; /* max free RX desc to hold */
59 uint16_t nb_rx_hold; /* number of held free RX desc */
60 struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
61 struct rte_mbuf *pkt_last_seg; /* last segment of current packet */
62 struct rte_mbuf fake_mbuf; /* dummy mbuf */
64 uint16_t port_id; /* device port ID */
65 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
66 uint16_t queue_id; /* Rx queue index */
67 uint16_t rx_buf_len; /* The packet buffer size */
68 uint16_t rx_hdr_len; /* The header buffer size */
69 uint16_t max_pkt_len; /* Maximum packet length */
71 bool q_set; /* if rx queue has been configured */
72 bool rx_deferred_start; /* don't start this queue in dev start */
76 struct rte_mbuf *mbuf;
81 /* Structure associated with each TX queue. */
83 const struct rte_memzone *mz; /* memzone for Tx ring */
84 volatile struct avf_tx_desc *tx_ring; /* Tx ring virtual address */
85 uint64_t tx_ring_phys_addr; /* Tx ring DMA address */
86 struct avf_tx_entry *sw_ring; /* address array of SW ring */
87 uint16_t nb_tx_desc; /* ring length */
88 uint16_t tx_tail; /* current value of tail */
89 volatile uint8_t *qtx_tail; /* register address of tail */
90 /* number of used desc since RS bit set */
93 uint16_t last_desc_cleaned; /* last desc have been cleaned*/
100 uint16_t next_dd; /* next to set RS, for VPMD */
101 uint16_t next_rs; /* next to check DD, for VPMD */
103 bool q_set; /* if rx queue has been configured */
104 bool tx_deferred_start; /* don't start this queue in dev start */
107 /* Offload features */
108 union avf_tx_offload {
111 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
112 uint64_t l3_len:9; /* L3 (IP) Header Length. */
113 uint64_t l4_len:8; /* L4 Header Length. */
114 uint64_t tso_segsz:16; /* TCP TSO segment size */
115 /* uint64_t unused : 24; */
119 int avf_dev_rx_queue_setup(struct rte_eth_dev *dev,
122 unsigned int socket_id,
123 const struct rte_eth_rxconf *rx_conf,
124 struct rte_mempool *mp);
126 int avf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
127 int avf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
128 void avf_dev_rx_queue_release(void *rxq);
130 int avf_dev_tx_queue_setup(struct rte_eth_dev *dev,
133 unsigned int socket_id,
134 const struct rte_eth_txconf *tx_conf);
135 int avf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
136 int avf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
137 void avf_dev_tx_queue_release(void *txq);
138 void avf_stop_queues(struct rte_eth_dev *dev);
139 uint16_t avf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
141 uint16_t avf_recv_scattered_pkts(void *rx_queue,
142 struct rte_mbuf **rx_pkts,
144 uint16_t avf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
146 uint16_t avf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
148 void avf_set_rx_function(struct rte_eth_dev *dev);
149 void avf_set_tx_function(struct rte_eth_dev *dev);
152 void avf_dump_rx_descriptor(struct avf_rx_queue *rxq,
156 #ifdef RTE_LIBRTE_AVF_16BYTE_RX_DESC
157 const union avf_16byte_rx_desc *rx_desc = desc;
159 printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
160 rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
161 rx_desc->read.hdr_addr);
163 const union avf_32byte_rx_desc *rx_desc = desc;
165 printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
166 " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
167 rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
168 rx_desc->read.rsvd1, rx_desc->read.rsvd2);
172 /* All the descriptors are 16 bytes, so just use one of them
173 * to print the qwords
176 void avf_dump_tx_descriptor(const struct avf_tx_queue *txq,
177 const void *desc, uint16_t tx_id)
180 const struct avf_tx_desc *tx_desc = desc;
181 enum avf_tx_desc_dtype_value type;
183 type = (enum avf_tx_desc_dtype_value)rte_le_to_cpu_64(
184 tx_desc->cmd_type_offset_bsz &
185 rte_cpu_to_le_64(AVF_TXD_QW1_DTYPE_MASK));
187 case AVF_TX_DESC_DTYPE_DATA:
188 name = "Tx_data_desc";
190 case AVF_TX_DESC_DTYPE_CONTEXT:
191 name = "Tx_context_desc";
194 name = "unknown_desc";
198 printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
199 txq->queue_id, name, tx_id, tx_desc->buffer_addr,
200 tx_desc->cmd_type_offset_bsz);
203 #ifdef DEBUG_DUMP_DESC
204 #define AVF_DUMP_RX_DESC(rxq, desc, rx_id) \
205 avf_dump_rx_descriptor(rxq, desc, rx_id)
206 #define AVF_DUMP_TX_DESC(txq, desc, tx_id) \
207 avf_dump_tx_descriptor(txq, desc, tx_id)
209 #define AVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
210 #define AVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
213 #endif /* _AVF_RXTX_H_ */