1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #ifndef __AXGBE_COMMON_H__
7 #define __AXGBE_COMMON_H__
9 #include "axgbe_logs.h"
13 #include <sys/queue.h>
24 #include <rte_byteorder.h>
25 #include <rte_memory.h>
26 #include <rte_malloc.h>
27 #include <rte_hexdump.h>
29 #include <rte_debug.h>
30 #include <rte_branch_prediction.h>
32 #include <rte_memzone.h>
33 #include <rte_ether.h>
34 #include <rte_ethdev.h>
36 #include <rte_errno.h>
38 #include <rte_ethdev_pci.h>
39 #include <rte_common.h>
40 #include <rte_cycles.h>
43 #define BIT(nr) (1 << (nr))
45 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
50 /* DMA register offsets */
52 #define DMA_SBMR 0x3004
53 #define DMA_ISR 0x3008
54 #define DMA_AXIARCR 0x3010
55 #define DMA_AXIAWCR 0x3018
56 #define DMA_AXIAWRCR 0x301c
57 #define DMA_DSR0 0x3020
58 #define DMA_DSR1 0x3024
59 #define EDMA_TX_CONTROL 0x3040
60 #define EDMA_RX_CONTROL 0x3044
62 /* DMA register entry bit positions and sizes */
63 #define DMA_AXIARCR_DRC_INDEX 0
64 #define DMA_AXIARCR_DRC_WIDTH 4
65 #define DMA_AXIARCR_DRD_INDEX 4
66 #define DMA_AXIARCR_DRD_WIDTH 2
67 #define DMA_AXIARCR_TEC_INDEX 8
68 #define DMA_AXIARCR_TEC_WIDTH 4
69 #define DMA_AXIARCR_TED_INDEX 12
70 #define DMA_AXIARCR_TED_WIDTH 2
71 #define DMA_AXIARCR_THC_INDEX 16
72 #define DMA_AXIARCR_THC_WIDTH 4
73 #define DMA_AXIARCR_THD_INDEX 20
74 #define DMA_AXIARCR_THD_WIDTH 2
75 #define DMA_AXIAWCR_DWC_INDEX 0
76 #define DMA_AXIAWCR_DWC_WIDTH 4
77 #define DMA_AXIAWCR_DWD_INDEX 4
78 #define DMA_AXIAWCR_DWD_WIDTH 2
79 #define DMA_AXIAWCR_RPC_INDEX 8
80 #define DMA_AXIAWCR_RPC_WIDTH 4
81 #define DMA_AXIAWCR_RPD_INDEX 12
82 #define DMA_AXIAWCR_RPD_WIDTH 2
83 #define DMA_AXIAWCR_RHC_INDEX 16
84 #define DMA_AXIAWCR_RHC_WIDTH 4
85 #define DMA_AXIAWCR_RHD_INDEX 20
86 #define DMA_AXIAWCR_RHD_WIDTH 2
87 #define DMA_AXIAWCR_RDC_INDEX 24
88 #define DMA_AXIAWCR_RDC_WIDTH 4
89 #define DMA_AXIAWCR_RDD_INDEX 28
90 #define DMA_AXIAWCR_RDD_WIDTH 2
91 #define DMA_AXIAWRCR_TDWC_INDEX 0
92 #define DMA_AXIAWRCR_TDWC_WIDTH 4
93 #define DMA_AXIAWRCR_TDWD_INDEX 4
94 #define DMA_AXIAWRCR_TDWD_WIDTH 4
95 #define DMA_AXIAWRCR_RDRC_INDEX 8
96 #define DMA_AXIAWRCR_RDRC_WIDTH 4
97 #define DMA_ISR_MACIS_INDEX 17
98 #define DMA_ISR_MACIS_WIDTH 1
99 #define DMA_ISR_MTLIS_INDEX 16
100 #define DMA_ISR_MTLIS_WIDTH 1
101 #define DMA_MR_INTM_INDEX 12
102 #define DMA_MR_INTM_WIDTH 2
103 #define DMA_MR_SWR_INDEX 0
104 #define DMA_MR_SWR_WIDTH 1
105 #define DMA_SBMR_WR_OSR_INDEX 24
106 #define DMA_SBMR_WR_OSR_WIDTH 6
107 #define DMA_SBMR_RD_OSR_INDEX 16
108 #define DMA_SBMR_RD_OSR_WIDTH 6
109 #define DMA_SBMR_AAL_INDEX 12
110 #define DMA_SBMR_AAL_WIDTH 1
111 #define DMA_SBMR_EAME_INDEX 11
112 #define DMA_SBMR_EAME_WIDTH 1
113 #define DMA_SBMR_BLEN_256_INDEX 7
114 #define DMA_SBMR_BLEN_256_WIDTH 1
115 #define DMA_SBMR_BLEN_32_INDEX 4
116 #define DMA_SBMR_BLEN_32_WIDTH 1
117 #define DMA_SBMR_UNDEF_INDEX 0
118 #define DMA_SBMR_UNDEF_WIDTH 1
120 /* DMA register values */
121 #define DMA_DSR_RPS_WIDTH 4
122 #define DMA_DSR_TPS_WIDTH 4
123 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
124 #define DMA_DSR0_RPS_START 8
125 #define DMA_DSR0_TPS_START 12
126 #define DMA_DSRX_FIRST_QUEUE 3
127 #define DMA_DSRX_INC 4
128 #define DMA_DSRX_QPR 4
129 #define DMA_DSRX_RPS_START 0
130 #define DMA_DSRX_TPS_START 4
131 #define DMA_TPS_STOPPED 0x00
132 #define DMA_TPS_SUSPENDED 0x06
134 /* DMA channel register offsets
135 * Multiple channels can be active. The first channel has registers
136 * that begin at 0x3100. Each subsequent channel has registers that
137 * are accessed using an offset of 0x80 from the previous channel.
139 #define DMA_CH_BASE 0x3100
140 #define DMA_CH_INC 0x80
142 #define DMA_CH_CR 0x00
143 #define DMA_CH_TCR 0x04
144 #define DMA_CH_RCR 0x08
145 #define DMA_CH_TDLR_HI 0x10
146 #define DMA_CH_TDLR_LO 0x14
147 #define DMA_CH_RDLR_HI 0x18
148 #define DMA_CH_RDLR_LO 0x1c
149 #define DMA_CH_TDTR_LO 0x24
150 #define DMA_CH_RDTR_LO 0x2c
151 #define DMA_CH_TDRLR 0x30
152 #define DMA_CH_RDRLR 0x34
153 #define DMA_CH_IER 0x38
154 #define DMA_CH_RIWT 0x3c
155 #define DMA_CH_CATDR_LO 0x44
156 #define DMA_CH_CARDR_LO 0x4c
157 #define DMA_CH_CATBR_HI 0x50
158 #define DMA_CH_CATBR_LO 0x54
159 #define DMA_CH_CARBR_HI 0x58
160 #define DMA_CH_CARBR_LO 0x5c
161 #define DMA_CH_SR 0x60
163 /* DMA channel register entry bit positions and sizes */
164 #define DMA_CH_CR_PBLX8_INDEX 16
165 #define DMA_CH_CR_PBLX8_WIDTH 1
166 #define DMA_CH_CR_SPH_INDEX 24
167 #define DMA_CH_CR_SPH_WIDTH 1
168 #define DMA_CH_IER_AIE_INDEX 14
169 #define DMA_CH_IER_AIE_WIDTH 1
170 #define DMA_CH_IER_FBEE_INDEX 12
171 #define DMA_CH_IER_FBEE_WIDTH 1
172 #define DMA_CH_IER_NIE_INDEX 15
173 #define DMA_CH_IER_NIE_WIDTH 1
174 #define DMA_CH_IER_RBUE_INDEX 7
175 #define DMA_CH_IER_RBUE_WIDTH 1
176 #define DMA_CH_IER_RIE_INDEX 6
177 #define DMA_CH_IER_RIE_WIDTH 1
178 #define DMA_CH_IER_RSE_INDEX 8
179 #define DMA_CH_IER_RSE_WIDTH 1
180 #define DMA_CH_IER_TBUE_INDEX 2
181 #define DMA_CH_IER_TBUE_WIDTH 1
182 #define DMA_CH_IER_TIE_INDEX 0
183 #define DMA_CH_IER_TIE_WIDTH 1
184 #define DMA_CH_IER_TXSE_INDEX 1
185 #define DMA_CH_IER_TXSE_WIDTH 1
186 #define DMA_CH_RCR_PBL_INDEX 16
187 #define DMA_CH_RCR_PBL_WIDTH 6
188 #define DMA_CH_RCR_RBSZ_INDEX 1
189 #define DMA_CH_RCR_RBSZ_WIDTH 14
190 #define DMA_CH_RCR_SR_INDEX 0
191 #define DMA_CH_RCR_SR_WIDTH 1
192 #define DMA_CH_RIWT_RWT_INDEX 0
193 #define DMA_CH_RIWT_RWT_WIDTH 8
194 #define DMA_CH_SR_FBE_INDEX 12
195 #define DMA_CH_SR_FBE_WIDTH 1
196 #define DMA_CH_SR_RBU_INDEX 7
197 #define DMA_CH_SR_RBU_WIDTH 1
198 #define DMA_CH_SR_RI_INDEX 6
199 #define DMA_CH_SR_RI_WIDTH 1
200 #define DMA_CH_SR_RPS_INDEX 8
201 #define DMA_CH_SR_RPS_WIDTH 1
202 #define DMA_CH_SR_TBU_INDEX 2
203 #define DMA_CH_SR_TBU_WIDTH 1
204 #define DMA_CH_SR_TI_INDEX 0
205 #define DMA_CH_SR_TI_WIDTH 1
206 #define DMA_CH_SR_TPS_INDEX 1
207 #define DMA_CH_SR_TPS_WIDTH 1
208 #define DMA_CH_TCR_OSP_INDEX 4
209 #define DMA_CH_TCR_OSP_WIDTH 1
210 #define DMA_CH_TCR_PBL_INDEX 16
211 #define DMA_CH_TCR_PBL_WIDTH 6
212 #define DMA_CH_TCR_ST_INDEX 0
213 #define DMA_CH_TCR_ST_WIDTH 1
214 #define DMA_CH_TCR_TSE_INDEX 12
215 #define DMA_CH_TCR_TSE_WIDTH 1
217 /* DMA channel register values */
218 #define DMA_OSP_DISABLE 0x00
219 #define DMA_OSP_ENABLE 0x01
224 #define DMA_PBL_16 16
225 #define DMA_PBL_32 32
226 #define DMA_PBL_64 64 /* 8 x 8 */
227 #define DMA_PBL_128 128 /* 8 x 16 */
228 #define DMA_PBL_256 256 /* 8 x 32 */
229 #define DMA_PBL_X8_DISABLE 0x00
230 #define DMA_PBL_X8_ENABLE 0x01
232 /* MAC register offsets */
233 #define MAC_TCR 0x0000
234 #define MAC_RCR 0x0004
235 #define MAC_PFR 0x0008
236 #define MAC_WTR 0x000c
237 #define MAC_HTR0 0x0010
238 #define MAC_VLANTR 0x0050
239 #define MAC_VLANHTR 0x0058
240 #define MAC_VLANIR 0x0060
241 #define MAC_IVLANIR 0x0064
242 #define MAC_RETMR 0x006c
243 #define MAC_Q0TFCR 0x0070
244 #define MAC_RFCR 0x0090
245 #define MAC_RQC0R 0x00a0
246 #define MAC_RQC1R 0x00a4
247 #define MAC_RQC2R 0x00a8
248 #define MAC_RQC3R 0x00ac
249 #define MAC_ISR 0x00b0
250 #define MAC_IER 0x00b4
251 #define MAC_RTSR 0x00b8
252 #define MAC_PMTCSR 0x00c0
253 #define MAC_RWKPFR 0x00c4
254 #define MAC_LPICSR 0x00d0
255 #define MAC_LPITCR 0x00d4
256 #define MAC_VR 0x0110
257 #define MAC_DR 0x0114
258 #define MAC_HWF0R 0x011c
259 #define MAC_HWF1R 0x0120
260 #define MAC_HWF2R 0x0124
261 #define MAC_MDIOSCAR 0x0200
262 #define MAC_MDIOSCCDR 0x0204
263 #define MAC_MDIOISR 0x0214
264 #define MAC_MDIOIER 0x0218
265 #define MAC_MDIOCL22R 0x0220
266 #define MAC_GPIOCR 0x0278
267 #define MAC_GPIOSR 0x027c
268 #define MAC_MACA0HR 0x0300
269 #define MAC_MACA0LR 0x0304
270 #define MAC_MACA1HR 0x0308
271 #define MAC_MACA1LR 0x030c
272 #define MAC_RSSCR 0x0c80
273 #define MAC_RSSAR 0x0c88
274 #define MAC_RSSDR 0x0c8c
275 #define MAC_TSCR 0x0d00
276 #define MAC_SSIR 0x0d04
277 #define MAC_STSR 0x0d08
278 #define MAC_STNR 0x0d0c
279 #define MAC_STSUR 0x0d10
280 #define MAC_STNUR 0x0d14
281 #define MAC_TSAR 0x0d18
282 #define MAC_TSSR 0x0d20
283 #define MAC_TXSNR 0x0d30
284 #define MAC_TXSSR 0x0d34
286 #define MAC_QTFCR_INC 4
287 #define MAC_MACA_INC 4
288 #define MAC_HTR_INC 4
290 #define MAC_RQC2_INC 4
291 #define MAC_RQC2_Q_PER_REG 4
293 /* MAC register entry bit positions and sizes */
294 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18
295 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
296 #define MAC_HWF0R_ARPOFFSEL_INDEX 9
297 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1
298 #define MAC_HWF0R_EEESEL_INDEX 13
299 #define MAC_HWF0R_EEESEL_WIDTH 1
300 #define MAC_HWF0R_GMIISEL_INDEX 1
301 #define MAC_HWF0R_GMIISEL_WIDTH 1
302 #define MAC_HWF0R_MGKSEL_INDEX 7
303 #define MAC_HWF0R_MGKSEL_WIDTH 1
304 #define MAC_HWF0R_MMCSEL_INDEX 8
305 #define MAC_HWF0R_MMCSEL_WIDTH 1
306 #define MAC_HWF0R_RWKSEL_INDEX 6
307 #define MAC_HWF0R_RWKSEL_WIDTH 1
308 #define MAC_HWF0R_RXCOESEL_INDEX 16
309 #define MAC_HWF0R_RXCOESEL_WIDTH 1
310 #define MAC_HWF0R_SAVLANINS_INDEX 27
311 #define MAC_HWF0R_SAVLANINS_WIDTH 1
312 #define MAC_HWF0R_SMASEL_INDEX 5
313 #define MAC_HWF0R_SMASEL_WIDTH 1
314 #define MAC_HWF0R_TSSEL_INDEX 12
315 #define MAC_HWF0R_TSSEL_WIDTH 1
316 #define MAC_HWF0R_TSSTSSEL_INDEX 25
317 #define MAC_HWF0R_TSSTSSEL_WIDTH 2
318 #define MAC_HWF0R_TXCOESEL_INDEX 14
319 #define MAC_HWF0R_TXCOESEL_WIDTH 1
320 #define MAC_HWF0R_VLHASH_INDEX 4
321 #define MAC_HWF0R_VLHASH_WIDTH 1
322 #define MAC_HWF1R_ADDR64_INDEX 14
323 #define MAC_HWF1R_ADDR64_WIDTH 2
324 #define MAC_HWF1R_ADVTHWORD_INDEX 13
325 #define MAC_HWF1R_ADVTHWORD_WIDTH 1
326 #define MAC_HWF1R_DBGMEMA_INDEX 19
327 #define MAC_HWF1R_DBGMEMA_WIDTH 1
328 #define MAC_HWF1R_DCBEN_INDEX 16
329 #define MAC_HWF1R_DCBEN_WIDTH 1
330 #define MAC_HWF1R_HASHTBLSZ_INDEX 24
331 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3
332 #define MAC_HWF1R_L3L4FNUM_INDEX 27
333 #define MAC_HWF1R_L3L4FNUM_WIDTH 4
334 #define MAC_HWF1R_NUMTC_INDEX 21
335 #define MAC_HWF1R_NUMTC_WIDTH 3
336 #define MAC_HWF1R_RSSEN_INDEX 20
337 #define MAC_HWF1R_RSSEN_WIDTH 1
338 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0
339 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5
340 #define MAC_HWF1R_SPHEN_INDEX 17
341 #define MAC_HWF1R_SPHEN_WIDTH 1
342 #define MAC_HWF1R_TSOEN_INDEX 18
343 #define MAC_HWF1R_TSOEN_WIDTH 1
344 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6
345 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5
346 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28
347 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3
348 #define MAC_HWF2R_PPSOUTNUM_INDEX 24
349 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3
350 #define MAC_HWF2R_RXCHCNT_INDEX 12
351 #define MAC_HWF2R_RXCHCNT_WIDTH 4
352 #define MAC_HWF2R_RXQCNT_INDEX 0
353 #define MAC_HWF2R_RXQCNT_WIDTH 4
354 #define MAC_HWF2R_TXCHCNT_INDEX 18
355 #define MAC_HWF2R_TXCHCNT_WIDTH 4
356 #define MAC_HWF2R_TXQCNT_INDEX 6
357 #define MAC_HWF2R_TXQCNT_WIDTH 4
358 #define MAC_IER_TSIE_INDEX 12
359 #define MAC_IER_TSIE_WIDTH 1
360 #define MAC_ISR_MMCRXIS_INDEX 9
361 #define MAC_ISR_MMCRXIS_WIDTH 1
362 #define MAC_ISR_MMCTXIS_INDEX 10
363 #define MAC_ISR_MMCTXIS_WIDTH 1
364 #define MAC_ISR_PMTIS_INDEX 4
365 #define MAC_ISR_PMTIS_WIDTH 1
366 #define MAC_ISR_SMI_INDEX 1
367 #define MAC_ISR_SMI_WIDTH 1
368 #define MAC_ISR_LSI_INDEX 0
369 #define MAC_ISR_LSI_WIDTH 1
370 #define MAC_ISR_LS_INDEX 24
371 #define MAC_ISR_LS_WIDTH 2
372 #define MAC_ISR_TSIS_INDEX 12
373 #define MAC_ISR_TSIS_WIDTH 1
374 #define MAC_MACA1HR_AE_INDEX 31
375 #define MAC_MACA1HR_AE_WIDTH 1
376 #define MAC_MDIOIER_SNGLCOMPIE_INDEX 12
377 #define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1
378 #define MAC_MDIOISR_SNGLCOMPINT_INDEX 12
379 #define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1
380 #define MAC_MDIOSCAR_DA_INDEX 21
381 #define MAC_MDIOSCAR_DA_WIDTH 5
382 #define MAC_MDIOSCAR_PA_INDEX 16
383 #define MAC_MDIOSCAR_PA_WIDTH 5
384 #define MAC_MDIOSCAR_RA_INDEX 0
385 #define MAC_MDIOSCAR_RA_WIDTH 16
386 #define MAC_MDIOSCAR_REG_INDEX 0
387 #define MAC_MDIOSCAR_REG_WIDTH 21
388 #define MAC_MDIOSCCDR_BUSY_INDEX 22
389 #define MAC_MDIOSCCDR_BUSY_WIDTH 1
390 #define MAC_MDIOSCCDR_CMD_INDEX 16
391 #define MAC_MDIOSCCDR_CMD_WIDTH 2
392 #define MAC_MDIOSCCDR_CR_INDEX 19
393 #define MAC_MDIOSCCDR_CR_WIDTH 3
394 #define MAC_MDIOSCCDR_DATA_INDEX 0
395 #define MAC_MDIOSCCDR_DATA_WIDTH 16
396 #define MAC_MDIOSCCDR_SADDR_INDEX 18
397 #define MAC_MDIOSCCDR_SADDR_WIDTH 1
398 #define MAC_PFR_HMC_INDEX 2
399 #define MAC_PFR_HMC_WIDTH 1
400 #define MAC_PFR_HPF_INDEX 10
401 #define MAC_PFR_HPF_WIDTH 1
402 #define MAC_PFR_HUC_INDEX 1
403 #define MAC_PFR_HUC_WIDTH 1
404 #define MAC_PFR_PM_INDEX 4
405 #define MAC_PFR_PM_WIDTH 1
406 #define MAC_PFR_PR_INDEX 0
407 #define MAC_PFR_PR_WIDTH 1
408 #define MAC_PFR_VTFE_INDEX 16
409 #define MAC_PFR_VTFE_WIDTH 1
410 #define MAC_PMTCSR_MGKPKTEN_INDEX 1
411 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1
412 #define MAC_PMTCSR_PWRDWN_INDEX 0
413 #define MAC_PMTCSR_PWRDWN_WIDTH 1
414 #define MAC_PMTCSR_RWKFILTRST_INDEX 31
415 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1
416 #define MAC_PMTCSR_RWKPKTEN_INDEX 2
417 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1
418 #define MAC_Q0TFCR_PT_INDEX 16
419 #define MAC_Q0TFCR_PT_WIDTH 16
420 #define MAC_Q0TFCR_TFE_INDEX 1
421 #define MAC_Q0TFCR_TFE_WIDTH 1
422 #define MAC_RCR_ACS_INDEX 1
423 #define MAC_RCR_ACS_WIDTH 1
424 #define MAC_RCR_CST_INDEX 2
425 #define MAC_RCR_CST_WIDTH 1
426 #define MAC_RCR_DCRCC_INDEX 3
427 #define MAC_RCR_DCRCC_WIDTH 1
428 #define MAC_RCR_HDSMS_INDEX 12
429 #define MAC_RCR_HDSMS_WIDTH 3
430 #define MAC_RCR_IPC_INDEX 9
431 #define MAC_RCR_IPC_WIDTH 1
432 #define MAC_RCR_JE_INDEX 8
433 #define MAC_RCR_JE_WIDTH 1
434 #define MAC_RCR_LM_INDEX 10
435 #define MAC_RCR_LM_WIDTH 1
436 #define MAC_RCR_RE_INDEX 0
437 #define MAC_RCR_RE_WIDTH 1
438 #define MAC_RFCR_PFCE_INDEX 8
439 #define MAC_RFCR_PFCE_WIDTH 1
440 #define MAC_RFCR_RFE_INDEX 0
441 #define MAC_RFCR_RFE_WIDTH 1
442 #define MAC_RFCR_UP_INDEX 1
443 #define MAC_RFCR_UP_WIDTH 1
444 #define MAC_RQC0R_RXQ0EN_INDEX 0
445 #define MAC_RQC0R_RXQ0EN_WIDTH 2
446 #define MAC_RSSAR_ADDRT_INDEX 2
447 #define MAC_RSSAR_ADDRT_WIDTH 1
448 #define MAC_RSSAR_CT_INDEX 1
449 #define MAC_RSSAR_CT_WIDTH 1
450 #define MAC_RSSAR_OB_INDEX 0
451 #define MAC_RSSAR_OB_WIDTH 1
452 #define MAC_RSSAR_RSSIA_INDEX 8
453 #define MAC_RSSAR_RSSIA_WIDTH 8
454 #define MAC_RSSCR_IP2TE_INDEX 1
455 #define MAC_RSSCR_IP2TE_WIDTH 1
456 #define MAC_RSSCR_RSSE_INDEX 0
457 #define MAC_RSSCR_RSSE_WIDTH 1
458 #define MAC_RSSCR_TCP4TE_INDEX 2
459 #define MAC_RSSCR_TCP4TE_WIDTH 1
460 #define MAC_RSSCR_UDP4TE_INDEX 3
461 #define MAC_RSSCR_UDP4TE_WIDTH 1
462 #define MAC_RSSDR_DMCH_INDEX 0
463 #define MAC_RSSDR_DMCH_WIDTH 4
464 #define MAC_SSIR_SNSINC_INDEX 8
465 #define MAC_SSIR_SNSINC_WIDTH 8
466 #define MAC_SSIR_SSINC_INDEX 16
467 #define MAC_SSIR_SSINC_WIDTH 8
468 #define MAC_TCR_SS_INDEX 29
469 #define MAC_TCR_SS_WIDTH 2
470 #define MAC_TCR_TE_INDEX 0
471 #define MAC_TCR_TE_WIDTH 1
472 #define MAC_TSCR_AV8021ASMEN_INDEX 28
473 #define MAC_TSCR_AV8021ASMEN_WIDTH 1
474 #define MAC_TSCR_SNAPTYPSEL_INDEX 16
475 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2
476 #define MAC_TSCR_TSADDREG_INDEX 5
477 #define MAC_TSCR_TSADDREG_WIDTH 1
478 #define MAC_TSCR_TSCFUPDT_INDEX 1
479 #define MAC_TSCR_TSCFUPDT_WIDTH 1
480 #define MAC_TSCR_TSCTRLSSR_INDEX 9
481 #define MAC_TSCR_TSCTRLSSR_WIDTH 1
482 #define MAC_TSCR_TSENA_INDEX 0
483 #define MAC_TSCR_TSENA_WIDTH 1
484 #define MAC_TSCR_TSENALL_INDEX 8
485 #define MAC_TSCR_TSENALL_WIDTH 1
486 #define MAC_TSCR_TSEVNTENA_INDEX 14
487 #define MAC_TSCR_TSEVNTENA_WIDTH 1
488 #define MAC_TSCR_TSINIT_INDEX 2
489 #define MAC_TSCR_TSINIT_WIDTH 1
490 #define MAC_TSCR_TSIPENA_INDEX 11
491 #define MAC_TSCR_TSIPENA_WIDTH 1
492 #define MAC_TSCR_TSIPV4ENA_INDEX 13
493 #define MAC_TSCR_TSIPV4ENA_WIDTH 1
494 #define MAC_TSCR_TSIPV6ENA_INDEX 12
495 #define MAC_TSCR_TSIPV6ENA_WIDTH 1
496 #define MAC_TSCR_TSMSTRENA_INDEX 15
497 #define MAC_TSCR_TSMSTRENA_WIDTH 1
498 #define MAC_TSCR_TSVER2ENA_INDEX 10
499 #define MAC_TSCR_TSVER2ENA_WIDTH 1
500 #define MAC_TSCR_TXTSSTSM_INDEX 24
501 #define MAC_TSCR_TXTSSTSM_WIDTH 1
502 #define MAC_TSSR_TXTSC_INDEX 15
503 #define MAC_TSSR_TXTSC_WIDTH 1
504 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31
505 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1
506 #define MAC_VLANHTR_VLHT_INDEX 0
507 #define MAC_VLANHTR_VLHT_WIDTH 16
508 #define MAC_VLANIR_VLTI_INDEX 20
509 #define MAC_VLANIR_VLTI_WIDTH 1
510 #define MAC_VLANIR_CSVL_INDEX 19
511 #define MAC_VLANIR_CSVL_WIDTH 1
512 #define MAC_VLANTR_DOVLTC_INDEX 20
513 #define MAC_VLANTR_DOVLTC_WIDTH 1
514 #define MAC_VLANTR_ERSVLM_INDEX 19
515 #define MAC_VLANTR_ERSVLM_WIDTH 1
516 #define MAC_VLANTR_ESVL_INDEX 18
517 #define MAC_VLANTR_ESVL_WIDTH 1
518 #define MAC_VLANTR_ETV_INDEX 16
519 #define MAC_VLANTR_ETV_WIDTH 1
520 #define MAC_VLANTR_EVLS_INDEX 21
521 #define MAC_VLANTR_EVLS_WIDTH 2
522 #define MAC_VLANTR_EVLRXS_INDEX 24
523 #define MAC_VLANTR_EVLRXS_WIDTH 1
524 #define MAC_VLANTR_VL_INDEX 0
525 #define MAC_VLANTR_VL_WIDTH 16
526 #define MAC_VLANTR_VTHM_INDEX 25
527 #define MAC_VLANTR_VTHM_WIDTH 1
528 #define MAC_VLANTR_VTIM_INDEX 17
529 #define MAC_VLANTR_VTIM_WIDTH 1
530 #define MAC_VR_DEVID_INDEX 8
531 #define MAC_VR_DEVID_WIDTH 8
532 #define MAC_VR_SNPSVER_INDEX 0
533 #define MAC_VR_SNPSVER_WIDTH 8
534 #define MAC_VR_USERVER_INDEX 16
535 #define MAC_VR_USERVER_WIDTH 8
537 /* MMC register offsets */
538 #define MMC_CR 0x0800
539 #define MMC_RISR 0x0804
540 #define MMC_TISR 0x0808
541 #define MMC_RIER 0x080c
542 #define MMC_TIER 0x0810
543 #define MMC_TXOCTETCOUNT_GB_LO 0x0814
544 #define MMC_TXOCTETCOUNT_GB_HI 0x0818
545 #define MMC_TXFRAMECOUNT_GB_LO 0x081c
546 #define MMC_TXFRAMECOUNT_GB_HI 0x0820
547 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824
548 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828
549 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c
550 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830
551 #define MMC_TX64OCTETS_GB_LO 0x0834
552 #define MMC_TX64OCTETS_GB_HI 0x0838
553 #define MMC_TX65TO127OCTETS_GB_LO 0x083c
554 #define MMC_TX65TO127OCTETS_GB_HI 0x0840
555 #define MMC_TX128TO255OCTETS_GB_LO 0x0844
556 #define MMC_TX128TO255OCTETS_GB_HI 0x0848
557 #define MMC_TX256TO511OCTETS_GB_LO 0x084c
558 #define MMC_TX256TO511OCTETS_GB_HI 0x0850
559 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854
560 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858
561 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
562 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860
563 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864
564 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868
565 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
566 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870
567 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
568 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878
569 #define MMC_TXUNDERFLOWERROR_LO 0x087c
570 #define MMC_TXUNDERFLOWERROR_HI 0x0880
571 #define MMC_TXOCTETCOUNT_G_LO 0x0884
572 #define MMC_TXOCTETCOUNT_G_HI 0x0888
573 #define MMC_TXFRAMECOUNT_G_LO 0x088c
574 #define MMC_TXFRAMECOUNT_G_HI 0x0890
575 #define MMC_TXPAUSEFRAMES_LO 0x0894
576 #define MMC_TXPAUSEFRAMES_HI 0x0898
577 #define MMC_TXVLANFRAMES_G_LO 0x089c
578 #define MMC_TXVLANFRAMES_G_HI 0x08a0
579 #define MMC_RXFRAMECOUNT_GB_LO 0x0900
580 #define MMC_RXFRAMECOUNT_GB_HI 0x0904
581 #define MMC_RXOCTETCOUNT_GB_LO 0x0908
582 #define MMC_RXOCTETCOUNT_GB_HI 0x090c
583 #define MMC_RXOCTETCOUNT_G_LO 0x0910
584 #define MMC_RXOCTETCOUNT_G_HI 0x0914
585 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918
586 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c
587 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920
588 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924
589 #define MMC_RXCRCERROR_LO 0x0928
590 #define MMC_RXCRCERROR_HI 0x092c
591 #define MMC_RXRUNTERROR 0x0930
592 #define MMC_RXJABBERERROR 0x0934
593 #define MMC_RXUNDERSIZE_G 0x0938
594 #define MMC_RXOVERSIZE_G 0x093c
595 #define MMC_RX64OCTETS_GB_LO 0x0940
596 #define MMC_RX64OCTETS_GB_HI 0x0944
597 #define MMC_RX65TO127OCTETS_GB_LO 0x0948
598 #define MMC_RX65TO127OCTETS_GB_HI 0x094c
599 #define MMC_RX128TO255OCTETS_GB_LO 0x0950
600 #define MMC_RX128TO255OCTETS_GB_HI 0x0954
601 #define MMC_RX256TO511OCTETS_GB_LO 0x0958
602 #define MMC_RX256TO511OCTETS_GB_HI 0x095c
603 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960
604 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964
605 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
606 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c
607 #define MMC_RXUNICASTFRAMES_G_LO 0x0970
608 #define MMC_RXUNICASTFRAMES_G_HI 0x0974
609 #define MMC_RXLENGTHERROR_LO 0x0978
610 #define MMC_RXLENGTHERROR_HI 0x097c
611 #define MMC_RXOUTOFRANGETYPE_LO 0x0980
612 #define MMC_RXOUTOFRANGETYPE_HI 0x0984
613 #define MMC_RXPAUSEFRAMES_LO 0x0988
614 #define MMC_RXPAUSEFRAMES_HI 0x098c
615 #define MMC_RXFIFOOVERFLOW_LO 0x0990
616 #define MMC_RXFIFOOVERFLOW_HI 0x0994
617 #define MMC_RXVLANFRAMES_GB_LO 0x0998
618 #define MMC_RXVLANFRAMES_GB_HI 0x099c
619 #define MMC_RXWATCHDOGERROR 0x09a0
621 /* MMC register entry bit positions and sizes */
622 #define MMC_CR_CR_INDEX 0
623 #define MMC_CR_CR_WIDTH 1
624 #define MMC_CR_CSR_INDEX 1
625 #define MMC_CR_CSR_WIDTH 1
626 #define MMC_CR_ROR_INDEX 2
627 #define MMC_CR_ROR_WIDTH 1
628 #define MMC_CR_MCF_INDEX 3
629 #define MMC_CR_MCF_WIDTH 1
630 #define MMC_CR_MCT_INDEX 4
631 #define MMC_CR_MCT_WIDTH 2
632 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0
633 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23
634 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0
635 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1
636 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1
637 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1
638 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2
639 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1
640 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3
641 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1
642 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4
643 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1
644 #define MMC_RISR_RXCRCERROR_INDEX 5
645 #define MMC_RISR_RXCRCERROR_WIDTH 1
646 #define MMC_RISR_RXRUNTERROR_INDEX 6
647 #define MMC_RISR_RXRUNTERROR_WIDTH 1
648 #define MMC_RISR_RXJABBERERROR_INDEX 7
649 #define MMC_RISR_RXJABBERERROR_WIDTH 1
650 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8
651 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1
652 #define MMC_RISR_RXOVERSIZE_G_INDEX 9
653 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1
654 #define MMC_RISR_RX64OCTETS_GB_INDEX 10
655 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1
656 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11
657 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1
658 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12
659 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1
660 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13
661 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1
662 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14
663 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1
664 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15
665 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1
666 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16
667 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1
668 #define MMC_RISR_RXLENGTHERROR_INDEX 17
669 #define MMC_RISR_RXLENGTHERROR_WIDTH 1
670 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18
671 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1
672 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19
673 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1
674 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20
675 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1
676 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21
677 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1
678 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22
679 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1
680 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0
681 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18
682 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0
683 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1
684 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1
685 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1
686 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2
687 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1
688 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3
689 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1
690 #define MMC_TISR_TX64OCTETS_GB_INDEX 4
691 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1
692 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5
693 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1
694 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6
695 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1
696 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7
697 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1
698 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8
699 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1
700 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9
701 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1
702 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10
703 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1
704 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11
705 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1
706 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12
707 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1
708 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13
709 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1
710 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14
711 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1
712 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15
713 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1
714 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16
715 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1
716 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17
717 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1
719 /* MTL register offsets */
720 #define MTL_OMR 0x1000
721 #define MTL_FDCR 0x1008
722 #define MTL_FDSR 0x100c
723 #define MTL_FDDR 0x1010
724 #define MTL_ISR 0x1020
725 #define MTL_RQDCM0R 0x1030
726 #define MTL_TCPM0R 0x1040
727 #define MTL_TCPM1R 0x1044
729 #define MTL_RQDCM_INC 4
730 #define MTL_RQDCM_Q_PER_REG 4
731 #define MTL_TCPM_INC 4
732 #define MTL_TCPM_TC_PER_REG 4
734 /* MTL register entry bit positions and sizes */
735 #define MTL_OMR_ETSALG_INDEX 5
736 #define MTL_OMR_ETSALG_WIDTH 2
737 #define MTL_OMR_RAA_INDEX 2
738 #define MTL_OMR_RAA_WIDTH 1
740 /* MTL queue register offsets
741 * Multiple queues can be active. The first queue has registers
742 * that begin at 0x1100. Each subsequent queue has registers that
743 * are accessed using an offset of 0x80 from the previous queue.
745 #define MTL_Q_BASE 0x1100
746 #define MTL_Q_INC 0x80
748 #define MTL_Q_TQOMR 0x00
749 #define MTL_Q_TQUR 0x04
750 #define MTL_Q_TQDR 0x08
751 #define MTL_Q_RQOMR 0x40
752 #define MTL_Q_RQMPOCR 0x44
753 #define MTL_Q_RQDR 0x48
754 #define MTL_Q_RQFCR 0x50
755 #define MTL_Q_IER 0x70
756 #define MTL_Q_ISR 0x74
758 /* MTL queue register entry bit positions and sizes */
759 #define MTL_Q_RQDR_PRXQ_INDEX 16
760 #define MTL_Q_RQDR_PRXQ_WIDTH 14
761 #define MTL_Q_RQDR_RXQSTS_INDEX 4
762 #define MTL_Q_RQDR_RXQSTS_WIDTH 2
763 #define MTL_Q_RQFCR_RFA_INDEX 1
764 #define MTL_Q_RQFCR_RFA_WIDTH 6
765 #define MTL_Q_RQFCR_RFD_INDEX 17
766 #define MTL_Q_RQFCR_RFD_WIDTH 6
767 #define MTL_Q_RQOMR_EHFC_INDEX 7
768 #define MTL_Q_RQOMR_EHFC_WIDTH 1
769 #define MTL_Q_RQOMR_RQS_INDEX 16
770 #define MTL_Q_RQOMR_RQS_WIDTH 9
771 #define MTL_Q_RQOMR_RSF_INDEX 5
772 #define MTL_Q_RQOMR_RSF_WIDTH 1
773 #define MTL_Q_RQOMR_RTC_INDEX 0
774 #define MTL_Q_RQOMR_RTC_WIDTH 2
775 #define MTL_Q_TQDR_TRCSTS_INDEX 1
776 #define MTL_Q_TQDR_TRCSTS_WIDTH 2
777 #define MTL_Q_TQDR_TXQSTS_INDEX 4
778 #define MTL_Q_TQDR_TXQSTS_WIDTH 1
779 #define MTL_Q_TQOMR_FTQ_INDEX 0
780 #define MTL_Q_TQOMR_FTQ_WIDTH 1
781 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8
782 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3
783 #define MTL_Q_TQOMR_TQS_INDEX 16
784 #define MTL_Q_TQOMR_TQS_WIDTH 10
785 #define MTL_Q_TQOMR_TSF_INDEX 1
786 #define MTL_Q_TQOMR_TSF_WIDTH 1
787 #define MTL_Q_TQOMR_TTC_INDEX 4
788 #define MTL_Q_TQOMR_TTC_WIDTH 3
789 #define MTL_Q_TQOMR_TXQEN_INDEX 2
790 #define MTL_Q_TQOMR_TXQEN_WIDTH 2
792 /* MTL queue register value */
793 #define MTL_RSF_DISABLE 0x00
794 #define MTL_RSF_ENABLE 0x01
795 #define MTL_TSF_DISABLE 0x00
796 #define MTL_TSF_ENABLE 0x01
798 #define MTL_RX_THRESHOLD_64 0x00
799 #define MTL_RX_THRESHOLD_96 0x02
800 #define MTL_RX_THRESHOLD_128 0x03
801 #define MTL_TX_THRESHOLD_32 0x01
802 #define MTL_TX_THRESHOLD_64 0x00
803 #define MTL_TX_THRESHOLD_96 0x02
804 #define MTL_TX_THRESHOLD_128 0x03
805 #define MTL_TX_THRESHOLD_192 0x04
806 #define MTL_TX_THRESHOLD_256 0x05
807 #define MTL_TX_THRESHOLD_384 0x06
808 #define MTL_TX_THRESHOLD_512 0x07
810 #define MTL_ETSALG_WRR 0x00
811 #define MTL_ETSALG_WFQ 0x01
812 #define MTL_ETSALG_DWRR 0x02
813 #define MTL_RAA_SP 0x00
814 #define MTL_RAA_WSP 0x01
816 #define MTL_Q_DISABLED 0x00
817 #define MTL_Q_ENABLED 0x02
819 /* MTL traffic class register offsets
820 * Multiple traffic classes can be active. The first class has registers
821 * that begin at 0x1100. Each subsequent queue has registers that
822 * are accessed using an offset of 0x80 from the previous queue.
824 #define MTL_TC_BASE MTL_Q_BASE
825 #define MTL_TC_INC MTL_Q_INC
827 #define MTL_TC_ETSCR 0x10
828 #define MTL_TC_ETSSR 0x14
829 #define MTL_TC_QWR 0x18
831 /* MTL traffic class register entry bit positions and sizes */
832 #define MTL_TC_ETSCR_TSA_INDEX 0
833 #define MTL_TC_ETSCR_TSA_WIDTH 2
834 #define MTL_TC_QWR_QW_INDEX 0
835 #define MTL_TC_QWR_QW_WIDTH 21
837 /* MTL traffic class register value */
838 #define MTL_TSA_SP 0x00
839 #define MTL_TSA_ETS 0x02
841 /* PCS register offsets */
842 #define PCS_V1_WINDOW_SELECT 0x03fc
843 #define PCS_V2_WINDOW_DEF 0x9060
844 #define PCS_V2_WINDOW_SELECT 0x9064
846 /* PCS register entry bit positions and sizes */
847 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
848 #define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14
849 #define PCS_V2_WINDOW_DEF_SIZE_INDEX 2
850 #define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4
852 /* SerDes integration register offsets */
853 #define SIR0_KR_RT_1 0x002c
854 #define SIR0_STATUS 0x0040
855 #define SIR1_SPEED 0x0000
857 /* SerDes integration register entry bit positions and sizes */
858 #define SIR0_KR_RT_1_RESET_INDEX 11
859 #define SIR0_KR_RT_1_RESET_WIDTH 1
860 #define SIR0_STATUS_RX_READY_INDEX 0
861 #define SIR0_STATUS_RX_READY_WIDTH 1
862 #define SIR0_STATUS_TX_READY_INDEX 8
863 #define SIR0_STATUS_TX_READY_WIDTH 1
864 #define SIR1_SPEED_CDR_RATE_INDEX 12
865 #define SIR1_SPEED_CDR_RATE_WIDTH 4
866 #define SIR1_SPEED_DATARATE_INDEX 4
867 #define SIR1_SPEED_DATARATE_WIDTH 2
868 #define SIR1_SPEED_PLLSEL_INDEX 3
869 #define SIR1_SPEED_PLLSEL_WIDTH 1
870 #define SIR1_SPEED_RATECHANGE_INDEX 6
871 #define SIR1_SPEED_RATECHANGE_WIDTH 1
872 #define SIR1_SPEED_TXAMP_INDEX 8
873 #define SIR1_SPEED_TXAMP_WIDTH 4
874 #define SIR1_SPEED_WORDMODE_INDEX 0
875 #define SIR1_SPEED_WORDMODE_WIDTH 3
877 /* SerDes RxTx register offsets */
878 #define RXTX_REG6 0x0018
879 #define RXTX_REG20 0x0050
880 #define RXTX_REG22 0x0058
881 #define RXTX_REG114 0x01c8
882 #define RXTX_REG129 0x0204
884 /* SerDes RxTx register entry bit positions and sizes */
885 #define RXTX_REG6_RESETB_RXD_INDEX 8
886 #define RXTX_REG6_RESETB_RXD_WIDTH 1
887 #define RXTX_REG20_BLWC_ENA_INDEX 2
888 #define RXTX_REG20_BLWC_ENA_WIDTH 1
889 #define RXTX_REG114_PQ_REG_INDEX 9
890 #define RXTX_REG114_PQ_REG_WIDTH 7
891 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14
892 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2
894 /* MAC Control register offsets */
895 #define XP_PROP_0 0x0000
896 #define XP_PROP_1 0x0004
897 #define XP_PROP_2 0x0008
898 #define XP_PROP_3 0x000c
899 #define XP_PROP_4 0x0010
900 #define XP_PROP_5 0x0014
901 #define XP_MAC_ADDR_LO 0x0020
902 #define XP_MAC_ADDR_HI 0x0024
903 #define XP_ECC_ISR 0x0030
904 #define XP_ECC_IER 0x0034
905 #define XP_ECC_CNT0 0x003c
906 #define XP_ECC_CNT1 0x0040
907 #define XP_DRIVER_INT_REQ 0x0060
908 #define XP_DRIVER_INT_RO 0x0064
909 #define XP_DRIVER_SCRATCH_0 0x0068
910 #define XP_DRIVER_SCRATCH_1 0x006c
911 #define XP_INT_EN 0x0078
912 #define XP_I2C_MUTEX 0x0080
913 #define XP_MDIO_MUTEX 0x0084
915 /* MAC Control register entry bit positions and sizes */
916 #define XP_DRIVER_INT_REQ_REQUEST_INDEX 0
917 #define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1
918 #define XP_DRIVER_INT_RO_STATUS_INDEX 0
919 #define XP_DRIVER_INT_RO_STATUS_WIDTH 1
920 #define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0
921 #define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8
922 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8
923 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8
924 #define XP_ECC_CNT0_RX_DED_INDEX 24
925 #define XP_ECC_CNT0_RX_DED_WIDTH 8
926 #define XP_ECC_CNT0_RX_SEC_INDEX 16
927 #define XP_ECC_CNT0_RX_SEC_WIDTH 8
928 #define XP_ECC_CNT0_TX_DED_INDEX 8
929 #define XP_ECC_CNT0_TX_DED_WIDTH 8
930 #define XP_ECC_CNT0_TX_SEC_INDEX 0
931 #define XP_ECC_CNT0_TX_SEC_WIDTH 8
932 #define XP_ECC_CNT1_DESC_DED_INDEX 8
933 #define XP_ECC_CNT1_DESC_DED_WIDTH 8
934 #define XP_ECC_CNT1_DESC_SEC_INDEX 0
935 #define XP_ECC_CNT1_DESC_SEC_WIDTH 8
936 #define XP_ECC_IER_DESC_DED_INDEX 0
937 #define XP_ECC_IER_DESC_DED_WIDTH 1
938 #define XP_ECC_IER_DESC_SEC_INDEX 1
939 #define XP_ECC_IER_DESC_SEC_WIDTH 1
940 #define XP_ECC_IER_RX_DED_INDEX 2
941 #define XP_ECC_IER_RX_DED_WIDTH 1
942 #define XP_ECC_IER_RX_SEC_INDEX 3
943 #define XP_ECC_IER_RX_SEC_WIDTH 1
944 #define XP_ECC_IER_TX_DED_INDEX 4
945 #define XP_ECC_IER_TX_DED_WIDTH 1
946 #define XP_ECC_IER_TX_SEC_INDEX 5
947 #define XP_ECC_IER_TX_SEC_WIDTH 1
948 #define XP_ECC_ISR_DESC_DED_INDEX 0
949 #define XP_ECC_ISR_DESC_DED_WIDTH 1
950 #define XP_ECC_ISR_DESC_SEC_INDEX 1
951 #define XP_ECC_ISR_DESC_SEC_WIDTH 1
952 #define XP_ECC_ISR_RX_DED_INDEX 2
953 #define XP_ECC_ISR_RX_DED_WIDTH 1
954 #define XP_ECC_ISR_RX_SEC_INDEX 3
955 #define XP_ECC_ISR_RX_SEC_WIDTH 1
956 #define XP_ECC_ISR_TX_DED_INDEX 4
957 #define XP_ECC_ISR_TX_DED_WIDTH 1
958 #define XP_ECC_ISR_TX_SEC_INDEX 5
959 #define XP_ECC_ISR_TX_SEC_WIDTH 1
960 #define XP_I2C_MUTEX_BUSY_INDEX 31
961 #define XP_I2C_MUTEX_BUSY_WIDTH 1
962 #define XP_I2C_MUTEX_ID_INDEX 29
963 #define XP_I2C_MUTEX_ID_WIDTH 2
964 #define XP_I2C_MUTEX_ACTIVE_INDEX 0
965 #define XP_I2C_MUTEX_ACTIVE_WIDTH 1
966 #define XP_MAC_ADDR_HI_VALID_INDEX 31
967 #define XP_MAC_ADDR_HI_VALID_WIDTH 1
968 #define XP_PROP_0_CONN_TYPE_INDEX 28
969 #define XP_PROP_0_CONN_TYPE_WIDTH 3
970 #define XP_PROP_0_MDIO_ADDR_INDEX 16
971 #define XP_PROP_0_MDIO_ADDR_WIDTH 5
972 #define XP_PROP_0_PORT_ID_INDEX 0
973 #define XP_PROP_0_PORT_ID_WIDTH 8
974 #define XP_PROP_0_PORT_MODE_INDEX 8
975 #define XP_PROP_0_PORT_MODE_WIDTH 4
976 #define XP_PROP_0_PORT_SPEEDS_INDEX 23
977 #define XP_PROP_0_PORT_SPEEDS_WIDTH 4
978 #define XP_PROP_1_MAX_RX_DMA_INDEX 24
979 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5
980 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8
981 #define XP_PROP_1_MAX_RX_QUEUES_WIDTH 5
982 #define XP_PROP_1_MAX_TX_DMA_INDEX 16
983 #define XP_PROP_1_MAX_TX_DMA_WIDTH 5
984 #define XP_PROP_1_MAX_TX_QUEUES_INDEX 0
985 #define XP_PROP_1_MAX_TX_QUEUES_WIDTH 5
986 #define XP_PROP_2_RX_FIFO_SIZE_INDEX 16
987 #define XP_PROP_2_RX_FIFO_SIZE_WIDTH 16
988 #define XP_PROP_2_TX_FIFO_SIZE_INDEX 0
989 #define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16
990 #define XP_PROP_3_GPIO_MASK_INDEX 28
991 #define XP_PROP_3_GPIO_MASK_WIDTH 4
992 #define XP_PROP_3_GPIO_MOD_ABS_INDEX 20
993 #define XP_PROP_3_GPIO_MOD_ABS_WIDTH 4
994 #define XP_PROP_3_GPIO_RATE_SELECT_INDEX 16
995 #define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 4
996 #define XP_PROP_3_GPIO_RX_LOS_INDEX 24
997 #define XP_PROP_3_GPIO_RX_LOS_WIDTH 4
998 #define XP_PROP_3_GPIO_TX_FAULT_INDEX 12
999 #define XP_PROP_3_GPIO_TX_FAULT_WIDTH 4
1000 #define XP_PROP_3_GPIO_ADDR_INDEX 8
1001 #define XP_PROP_3_GPIO_ADDR_WIDTH 3
1002 #define XP_PROP_3_MDIO_RESET_INDEX 0
1003 #define XP_PROP_3_MDIO_RESET_WIDTH 2
1004 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 8
1005 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 3
1006 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 12
1007 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 4
1008 #define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 4
1009 #define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 2
1010 #define XP_PROP_4_MUX_ADDR_HI_INDEX 8
1011 #define XP_PROP_4_MUX_ADDR_HI_WIDTH 5
1012 #define XP_PROP_4_MUX_ADDR_LO_INDEX 0
1013 #define XP_PROP_4_MUX_ADDR_LO_WIDTH 3
1014 #define XP_PROP_4_MUX_CHAN_INDEX 4
1015 #define XP_PROP_4_MUX_CHAN_WIDTH 3
1016 #define XP_PROP_4_REDRV_ADDR_INDEX 16
1017 #define XP_PROP_4_REDRV_ADDR_WIDTH 7
1018 #define XP_PROP_4_REDRV_IF_INDEX 23
1019 #define XP_PROP_4_REDRV_IF_WIDTH 1
1020 #define XP_PROP_4_REDRV_LANE_INDEX 24
1021 #define XP_PROP_4_REDRV_LANE_WIDTH 3
1022 #define XP_PROP_4_REDRV_MODEL_INDEX 28
1023 #define XP_PROP_4_REDRV_MODEL_WIDTH 3
1024 #define XP_PROP_4_REDRV_PRESENT_INDEX 31
1025 #define XP_PROP_4_REDRV_PRESENT_WIDTH 1
1027 /* I2C Control register offsets */
1028 #define IC_CON 0x0000
1029 #define IC_TAR 0x0004
1030 #define IC_DATA_CMD 0x0010
1031 #define IC_INTR_STAT 0x002c
1032 #define IC_INTR_MASK 0x0030
1033 #define IC_RAW_INTR_STAT 0x0034
1034 #define IC_CLR_INTR 0x0040
1035 #define IC_CLR_TX_ABRT 0x0054
1036 #define IC_CLR_STOP_DET 0x0060
1037 #define IC_ENABLE 0x006c
1038 #define IC_TXFLR 0x0074
1039 #define IC_RXFLR 0x0078
1040 #define IC_TX_ABRT_SOURCE 0x0080
1041 #define IC_ENABLE_STATUS 0x009c
1042 #define IC_COMP_PARAM_1 0x00f4
1044 /* I2C Control register entry bit positions and sizes */
1045 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2
1046 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2
1047 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8
1048 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8
1049 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16
1050 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8
1051 #define IC_CON_MASTER_MODE_INDEX 0
1052 #define IC_CON_MASTER_MODE_WIDTH 1
1053 #define IC_CON_RESTART_EN_INDEX 5
1054 #define IC_CON_RESTART_EN_WIDTH 1
1055 #define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9
1056 #define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1
1057 #define IC_CON_SLAVE_DISABLE_INDEX 6
1058 #define IC_CON_SLAVE_DISABLE_WIDTH 1
1059 #define IC_CON_SPEED_INDEX 1
1060 #define IC_CON_SPEED_WIDTH 2
1061 #define IC_DATA_CMD_CMD_INDEX 8
1062 #define IC_DATA_CMD_CMD_WIDTH 1
1063 #define IC_DATA_CMD_STOP_INDEX 9
1064 #define IC_DATA_CMD_STOP_WIDTH 1
1065 #define IC_ENABLE_ABORT_INDEX 1
1066 #define IC_ENABLE_ABORT_WIDTH 1
1067 #define IC_ENABLE_EN_INDEX 0
1068 #define IC_ENABLE_EN_WIDTH 1
1069 #define IC_ENABLE_STATUS_EN_INDEX 0
1070 #define IC_ENABLE_STATUS_EN_WIDTH 1
1071 #define IC_INTR_MASK_TX_EMPTY_INDEX 4
1072 #define IC_INTR_MASK_TX_EMPTY_WIDTH 1
1073 #define IC_RAW_INTR_STAT_RX_FULL_INDEX 2
1074 #define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1
1075 #define IC_RAW_INTR_STAT_STOP_DET_INDEX 9
1076 #define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1
1077 #define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6
1078 #define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1
1079 #define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4
1080 #define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
1082 /* I2C Control register value */
1083 #define IC_TX_ABRT_7B_ADDR_NOACK 0x0001
1084 #define IC_TX_ABRT_ARB_LOST 0x1000
1086 /* Descriptor/Packet entry bit positions and sizes */
1087 #define RX_PACKET_ERRORS_CRC_INDEX 2
1088 #define RX_PACKET_ERRORS_CRC_WIDTH 1
1089 #define RX_PACKET_ERRORS_FRAME_INDEX 3
1090 #define RX_PACKET_ERRORS_FRAME_WIDTH 1
1091 #define RX_PACKET_ERRORS_LENGTH_INDEX 0
1092 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1
1093 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1
1094 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1
1096 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0
1097 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1
1098 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1
1099 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1100 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2
1101 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1
1102 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3
1103 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1
1104 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4
1105 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1
1106 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5
1107 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1
1108 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6
1109 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1
1111 #define RX_NORMAL_DESC0_OVT_INDEX 0
1112 #define RX_NORMAL_DESC0_OVT_WIDTH 16
1113 #define RX_NORMAL_DESC2_HL_INDEX 0
1114 #define RX_NORMAL_DESC2_HL_WIDTH 10
1115 #define RX_NORMAL_DESC3_CDA_INDEX 27
1116 #define RX_NORMAL_DESC3_CDA_WIDTH 1
1117 #define RX_NORMAL_DESC3_CTXT_INDEX 30
1118 #define RX_NORMAL_DESC3_CTXT_WIDTH 1
1119 #define RX_NORMAL_DESC3_ES_INDEX 15
1120 #define RX_NORMAL_DESC3_ES_WIDTH 1
1121 #define RX_NORMAL_DESC3_ETLT_INDEX 16
1122 #define RX_NORMAL_DESC3_ETLT_WIDTH 4
1123 #define RX_NORMAL_DESC3_FD_INDEX 29
1124 #define RX_NORMAL_DESC3_FD_WIDTH 1
1125 #define RX_NORMAL_DESC3_INTE_INDEX 30
1126 #define RX_NORMAL_DESC3_INTE_WIDTH 1
1127 #define RX_NORMAL_DESC3_L34T_INDEX 20
1128 #define RX_NORMAL_DESC3_L34T_WIDTH 4
1129 #define RX_NORMAL_DESC3_LD_INDEX 28
1130 #define RX_NORMAL_DESC3_LD_WIDTH 1
1131 #define RX_NORMAL_DESC3_OWN_INDEX 31
1132 #define RX_NORMAL_DESC3_OWN_WIDTH 1
1133 #define RX_NORMAL_DESC3_PL_INDEX 0
1134 #define RX_NORMAL_DESC3_PL_WIDTH 14
1135 #define RX_NORMAL_DESC3_RSV_INDEX 26
1136 #define RX_NORMAL_DESC3_RSV_WIDTH 1
1138 #define RX_DESC3_L34T_IPV4_TCP 1
1139 #define RX_DESC3_L34T_IPV4_UDP 2
1140 #define RX_DESC3_L34T_IPV4_ICMP 3
1141 #define RX_DESC3_L34T_IPV6_TCP 9
1142 #define RX_DESC3_L34T_IPV6_UDP 10
1143 #define RX_DESC3_L34T_IPV6_ICMP 11
1145 #define RX_CONTEXT_DESC3_TSA_INDEX 4
1146 #define RX_CONTEXT_DESC3_TSA_WIDTH 1
1147 #define RX_CONTEXT_DESC3_TSD_INDEX 6
1148 #define RX_CONTEXT_DESC3_TSD_WIDTH 1
1150 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
1151 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1
1152 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1
1153 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1
1154 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2
1155 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1156 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3
1157 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1
1159 #define TX_CONTEXT_DESC2_MSS_INDEX 0
1160 #define TX_CONTEXT_DESC2_MSS_WIDTH 15
1161 #define TX_CONTEXT_DESC3_CTXT_INDEX 30
1162 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1
1163 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26
1164 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1
1165 #define TX_CONTEXT_DESC3_VLTV_INDEX 16
1166 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1
1167 #define TX_CONTEXT_DESC3_VT_INDEX 0
1168 #define TX_CONTEXT_DESC3_VT_WIDTH 16
1170 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0
1171 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14
1172 #define TX_NORMAL_DESC2_IC_INDEX 31
1173 #define TX_NORMAL_DESC2_IC_WIDTH 1
1174 #define TX_NORMAL_DESC2_TTSE_INDEX 30
1175 #define TX_NORMAL_DESC2_TTSE_WIDTH 1
1176 #define TX_NORMAL_DESC2_VTIR_INDEX 14
1177 #define TX_NORMAL_DESC2_VTIR_WIDTH 2
1178 #define TX_NORMAL_DESC3_CIC_INDEX 16
1179 #define TX_NORMAL_DESC3_CIC_WIDTH 2
1180 #define TX_NORMAL_DESC3_CPC_INDEX 26
1181 #define TX_NORMAL_DESC3_CPC_WIDTH 2
1182 #define TX_NORMAL_DESC3_CTXT_INDEX 30
1183 #define TX_NORMAL_DESC3_CTXT_WIDTH 1
1184 #define TX_NORMAL_DESC3_FD_INDEX 29
1185 #define TX_NORMAL_DESC3_FD_WIDTH 1
1186 #define TX_NORMAL_DESC3_FL_INDEX 0
1187 #define TX_NORMAL_DESC3_FL_WIDTH 15
1188 #define TX_NORMAL_DESC3_LD_INDEX 28
1189 #define TX_NORMAL_DESC3_LD_WIDTH 1
1190 #define TX_NORMAL_DESC3_OWN_INDEX 31
1191 #define TX_NORMAL_DESC3_OWN_WIDTH 1
1192 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19
1193 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4
1194 #define TX_NORMAL_DESC3_TCPPL_INDEX 0
1195 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18
1196 #define TX_NORMAL_DESC3_TSE_INDEX 18
1197 #define TX_NORMAL_DESC3_TSE_WIDTH 1
1199 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2
1201 /* MDIO undefined or vendor specific registers */
1202 #ifndef MDIO_PMA_10GBR_PMD_CTRL
1203 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
1206 #ifndef MDIO_PMA_10GBR_FECCTRL
1207 #define MDIO_PMA_10GBR_FECCTRL 0x00ab
1210 #ifndef MDIO_PCS_DIG_CTRL
1211 #define MDIO_PCS_DIG_CTRL 0x8000
1215 #define MDIO_AN_XNP 0x0016
1219 #define MDIO_AN_LPX 0x0019
1222 #ifndef MDIO_AN_COMP_STAT
1223 #define MDIO_AN_COMP_STAT 0x0030
1226 #ifndef MDIO_AN_INTMASK
1227 #define MDIO_AN_INTMASK 0x8001
1231 #define MDIO_AN_INT 0x8002
1234 #ifndef MDIO_VEND2_AN_ADVERTISE
1235 #define MDIO_VEND2_AN_ADVERTISE 0x0004
1238 #ifndef MDIO_VEND2_AN_LP_ABILITY
1239 #define MDIO_VEND2_AN_LP_ABILITY 0x0005
1242 #ifndef MDIO_VEND2_AN_CTRL
1243 #define MDIO_VEND2_AN_CTRL 0x8001
1246 #ifndef MDIO_VEND2_AN_STAT
1247 #define MDIO_VEND2_AN_STAT 0x8002
1250 #ifndef MDIO_CTRL1_SPEED1G
1251 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
1254 #ifndef MDIO_VEND2_CTRL1_AN_ENABLE
1255 #define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12)
1258 #ifndef MDIO_VEND2_CTRL1_AN_RESTART
1259 #define MDIO_VEND2_CTRL1_AN_RESTART BIT(9)
1262 #ifndef MDIO_VEND2_CTRL1_SS6
1263 #define MDIO_VEND2_CTRL1_SS6 BIT(6)
1266 #ifndef MDIO_VEND2_CTRL1_SS13
1267 #define MDIO_VEND2_CTRL1_SS13 BIT(13)
1270 /* MDIO mask values */
1271 #define AXGBE_AN_CL73_INT_CMPLT BIT(0)
1272 #define AXGBE_AN_CL73_INC_LINK BIT(1)
1273 #define AXGBE_AN_CL73_PG_RCV BIT(2)
1274 #define AXGBE_AN_CL73_INT_MASK 0x07
1276 #define AXGBE_XNP_MCF_NULL_MESSAGE 0x001
1277 #define AXGBE_XNP_ACK_PROCESSED BIT(12)
1278 #define AXGBE_XNP_MP_FORMATTED BIT(13)
1279 #define AXGBE_XNP_NP_EXCHANGE BIT(15)
1281 #define AXGBE_KR_TRAINING_START BIT(0)
1282 #define AXGBE_KR_TRAINING_ENABLE BIT(1)
1284 #define AXGBE_PCS_CL37_BP BIT(12)
1286 #define AXGBE_AN_CL37_INT_CMPLT BIT(0)
1287 #define AXGBE_AN_CL37_INT_MASK 0x01
1289 #define AXGBE_AN_CL37_HD_MASK 0x40
1290 #define AXGBE_AN_CL37_FD_MASK 0x20
1292 #define AXGBE_AN_CL37_PCS_MODE_MASK 0x06
1293 #define AXGBE_AN_CL37_PCS_MODE_BASEX 0x00
1294 #define AXGBE_AN_CL37_PCS_MODE_SGMII 0x04
1295 #define AXGBE_AN_CL37_TX_CONFIG_MASK 0x08
1300 #define rmb() rte_rmb() /* dpdk rte provided rmb */
1301 #define wmb() rte_wmb() /* dpdk rte provided wmb */
1307 typedef unsigned char u8;
1308 typedef unsigned short u16;
1309 typedef unsigned int u32;
1310 typedef unsigned long long u64;
1311 typedef unsigned long long dma_addr_t;
1313 static inline uint32_t low32_value(uint64_t addr)
1315 return (addr) & 0x0ffffffff;
1318 static inline uint32_t high32_value(uint64_t addr)
1320 return (addr >> 32) & 0x0ffffffff;
1325 /* Bit setting and getting macros
1326 * The get macro will extract the current bit field value from within
1329 * The set macro will clear the current bit field value within the
1330 * variable and then set the bit field of the variable to the
1333 #define GET_BITS(_var, _index, _width) \
1334 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1336 #define SET_BITS(_var, _index, _width, _val) \
1338 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1339 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1342 #define GET_BITS_LE(_var, _index, _width) \
1343 ((rte_le_to_cpu_32((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1345 #define SET_BITS_LE(_var, _index, _width, _val) \
1347 (_var) &= rte_cpu_to_le_32(~(((0x1 << (_width)) - 1) << (_index)));\
1348 (_var) |= rte_cpu_to_le_32((((_val) & \
1349 ((0x1 << (_width)) - 1)) << (_index))); \
1352 /* Bit setting and getting macros based on register fields
1353 * The get macro uses the bit field definitions formed using the input
1354 * names to extract the current bit field value from within the
1357 * The set macro uses the bit field definitions formed using the input
1358 * names to set the bit field of the variable to the specified value
1360 #define AXGMAC_GET_BITS(_var, _prefix, _field) \
1362 _prefix##_##_field##_INDEX, \
1363 _prefix##_##_field##_WIDTH)
1365 #define AXGMAC_SET_BITS(_var, _prefix, _field, _val) \
1367 _prefix##_##_field##_INDEX, \
1368 _prefix##_##_field##_WIDTH, (_val))
1370 #define AXGMAC_GET_BITS_LE(_var, _prefix, _field) \
1371 GET_BITS_LE((_var), \
1372 _prefix##_##_field##_INDEX, \
1373 _prefix##_##_field##_WIDTH)
1375 #define AXGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \
1376 SET_BITS_LE((_var), \
1377 _prefix##_##_field##_INDEX, \
1378 _prefix##_##_field##_WIDTH, (_val))
1380 /* Macros for reading or writing registers
1381 * The ioread macros will get bit fields or full values using the
1382 * register definitions formed using the input names
1384 * The iowrite macros will set bit fields or full values using the
1385 * register definitions formed using the input names
1387 #define AXGMAC_IOREAD(_pdata, _reg) \
1388 rte_read32((void *)((_pdata)->xgmac_regs + (_reg)))
1390 #define AXGMAC_IOREAD_BITS(_pdata, _reg, _field) \
1391 GET_BITS(AXGMAC_IOREAD((_pdata), _reg), \
1392 _reg##_##_field##_INDEX, \
1393 _reg##_##_field##_WIDTH)
1395 #define AXGMAC_IOWRITE(_pdata, _reg, _val) \
1396 rte_write32((_val), (void *)((_pdata)->xgmac_regs + (_reg)))
1398 #define AXGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1400 u32 reg_val = AXGMAC_IOREAD((_pdata), _reg); \
1402 _reg##_##_field##_INDEX, \
1403 _reg##_##_field##_WIDTH, (_val)); \
1404 AXGMAC_IOWRITE((_pdata), _reg, reg_val); \
1407 /* Macros for reading or writing MTL queue or traffic class registers
1408 * Similar to the standard read and write macros except that the
1409 * base register value is calculated by the queue or traffic class number
1411 #define AXGMAC_MTL_IOREAD(_pdata, _n, _reg) \
1412 rte_read32((void *)((_pdata)->xgmac_regs + \
1413 MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg)))
1415 #define AXGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
1416 GET_BITS(AXGMAC_MTL_IOREAD((_pdata), (_n), (_reg)), \
1417 _reg##_##_field##_INDEX, \
1418 _reg##_##_field##_WIDTH)
1420 #define AXGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
1421 rte_write32((_val), (void *)((_pdata)->xgmac_regs + \
1422 MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg)))
1424 #define AXGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
1426 u32 reg_val = AXGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
1428 _reg##_##_field##_INDEX, \
1429 _reg##_##_field##_WIDTH, (_val)); \
1430 AXGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
1433 /* Macros for reading or writing DMA channel registers
1434 * Similar to the standard read and write macros except that the
1435 * base register value is obtained from the ring
1437 #define AXGMAC_DMA_IOREAD(_channel, _reg) \
1438 rte_read32((void *)((_channel)->dma_regs + (_reg)))
1440 #define AXGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
1441 GET_BITS(AXGMAC_DMA_IOREAD((_channel), _reg), \
1442 _reg##_##_field##_INDEX, \
1443 _reg##_##_field##_WIDTH)
1445 #define AXGMAC_DMA_IOWRITE(_channel, _reg, _val) \
1446 rte_write32((_val), (void *)((_channel)->dma_regs + (_reg)))
1448 #define AXGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
1450 u32 reg_val = AXGMAC_DMA_IOREAD((_channel), _reg); \
1452 _reg##_##_field##_INDEX, \
1453 _reg##_##_field##_WIDTH, (_val)); \
1454 AXGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
1457 /* Macros for building, reading or writing register values or bits
1458 * within the register values of XPCS registers.
1460 #define XPCS_GET_BITS(_var, _prefix, _field) \
1462 _prefix##_##_field##_INDEX, \
1463 _prefix##_##_field##_WIDTH)
1465 #define XPCS_SET_BITS(_var, _prefix, _field, _val) \
1467 _prefix##_##_field##_INDEX, \
1468 _prefix##_##_field##_WIDTH, (_val))
1470 #define XPCS32_IOWRITE(_pdata, _off, _val) \
1471 rte_write32(_val, (void *)((_pdata)->xpcs_regs + (_off)))
1473 #define XPCS32_IOREAD(_pdata, _off) \
1474 rte_read32((void *)((_pdata)->xpcs_regs + (_off)))
1476 #define XPCS16_IOWRITE(_pdata, _off, _val) \
1477 rte_write16(_val, (void *)((_pdata)->xpcs_regs + (_off)))
1479 #define XPCS16_IOREAD(_pdata, _off) \
1480 rte_read16((void *)((_pdata)->xpcs_regs + (_off)))
1482 /* Macros for building, reading or writing register values or bits
1483 * within the register values of SerDes integration registers.
1485 #define XSIR_GET_BITS(_var, _prefix, _field) \
1487 _prefix##_##_field##_INDEX, \
1488 _prefix##_##_field##_WIDTH)
1490 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \
1492 _prefix##_##_field##_INDEX, \
1493 _prefix##_##_field##_WIDTH, (_val))
1495 #define XSIR0_IOREAD(_pdata, _reg) \
1496 rte_read16((void *)((_pdata)->sir0_regs + (_reg)))
1498 #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \
1499 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \
1500 _reg##_##_field##_INDEX, \
1501 _reg##_##_field##_WIDTH)
1503 #define XSIR0_IOWRITE(_pdata, _reg, _val) \
1504 rte_write16((_val), (void *)((_pdata)->sir0_regs + (_reg)))
1506 #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1508 u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \
1510 _reg##_##_field##_INDEX, \
1511 _reg##_##_field##_WIDTH, (_val)); \
1512 XSIR0_IOWRITE((_pdata), _reg, reg_val); \
1515 #define XSIR1_IOREAD(_pdata, _reg) \
1516 rte_read16((void *)((_pdata)->sir1_regs + _reg))
1518 #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \
1519 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \
1520 _reg##_##_field##_INDEX, \
1521 _reg##_##_field##_WIDTH)
1523 #define XSIR1_IOWRITE(_pdata, _reg, _val) \
1524 rte_write16((_val), (void *)((_pdata)->sir1_regs + (_reg)))
1526 #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1528 u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \
1530 _reg##_##_field##_INDEX, \
1531 _reg##_##_field##_WIDTH, (_val)); \
1532 XSIR1_IOWRITE((_pdata), _reg, reg_val); \
1535 /* Macros for building, reading or writing register values or bits
1536 * within the register values of SerDes RxTx registers.
1538 #define XRXTX_IOREAD(_pdata, _reg) \
1539 rte_read16((void *)((_pdata)->rxtx_regs + (_reg)))
1541 #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \
1542 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \
1543 _reg##_##_field##_INDEX, \
1544 _reg##_##_field##_WIDTH)
1546 #define XRXTX_IOWRITE(_pdata, _reg, _val) \
1547 rte_write16((_val), (void *)((_pdata)->rxtx_regs + (_reg)))
1549 #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1551 u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \
1553 _reg##_##_field##_INDEX, \
1554 _reg##_##_field##_WIDTH, (_val)); \
1555 XRXTX_IOWRITE((_pdata), _reg, reg_val); \
1558 /* Macros for building, reading or writing register values or bits
1559 * within the register values of MAC Control registers.
1561 #define XP_GET_BITS(_var, _prefix, _field) \
1563 _prefix##_##_field##_INDEX, \
1564 _prefix##_##_field##_WIDTH)
1566 #define XP_SET_BITS(_var, _prefix, _field, _val) \
1568 _prefix##_##_field##_INDEX, \
1569 _prefix##_##_field##_WIDTH, (_val))
1571 #define XP_IOREAD(_pdata, _reg) \
1572 rte_read32((void *)((_pdata)->xprop_regs + (_reg)))
1574 #define XP_IOREAD_BITS(_pdata, _reg, _field) \
1575 GET_BITS(XP_IOREAD((_pdata), (_reg)), \
1576 _reg##_##_field##_INDEX, \
1577 _reg##_##_field##_WIDTH)
1579 #define XP_IOWRITE(_pdata, _reg, _val) \
1580 rte_write32((_val), (void *)((_pdata)->xprop_regs + (_reg)))
1582 #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1584 u32 reg_val = XP_IOREAD((_pdata), (_reg)); \
1586 _reg##_##_field##_INDEX, \
1587 _reg##_##_field##_WIDTH, (_val)); \
1588 XP_IOWRITE((_pdata), (_reg), reg_val); \
1591 /* Macros for building, reading or writing register values or bits
1592 * within the register values of I2C Control registers.
1594 #define XI2C_GET_BITS(_var, _prefix, _field) \
1596 _prefix##_##_field##_INDEX, \
1597 _prefix##_##_field##_WIDTH)
1599 #define XI2C_SET_BITS(_var, _prefix, _field, _val) \
1601 _prefix##_##_field##_INDEX, \
1602 _prefix##_##_field##_WIDTH, (_val))
1604 #define XI2C_IOREAD(_pdata, _reg) \
1605 rte_read32((void *)((_pdata)->xi2c_regs + (_reg)))
1607 #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \
1608 GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \
1609 _reg##_##_field##_INDEX, \
1610 _reg##_##_field##_WIDTH)
1612 #define XI2C_IOWRITE(_pdata, _reg, _val) \
1613 rte_write32((_val), (void *)((_pdata)->xi2c_regs + (_reg)))
1615 #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1617 u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \
1619 _reg##_##_field##_INDEX, \
1620 _reg##_##_field##_WIDTH, (_val)); \
1621 XI2C_IOWRITE((_pdata), (_reg), reg_val); \
1624 /* Macros for building, reading or writing register values or bits
1625 * using MDIO. Different from above because of the use of standardized
1626 * Linux include values. No shifting is performed with the bit
1627 * operations, everything works on mask values.
1629 #define XMDIO_READ(_pdata, _mmd, _reg) \
1630 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
1631 MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))
1633 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \
1634 (XMDIO_READ((_pdata), _mmd, _reg) & _mask)
1636 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \
1637 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \
1638 MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))
1640 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \
1642 u32 mmd_val = XMDIO_READ((_pdata), (_mmd), (_reg)); \
1643 mmd_val &= ~(_mask); \
1644 mmd_val |= (_val); \
1645 XMDIO_WRITE((_pdata), (_mmd), (_reg), (mmd_val)); \
1649 * time_after(a,b) returns true if the time a is after time b.
1651 * Do this with "<0" and ">=0" to only test the sign of the result. A
1652 * good compiler would generate better code (and a really good compiler
1653 * wouldn't care). Gcc is currently neither.
1655 #define time_after(a, b) ((long)((b) - (a)) < 0)
1656 #define time_before(a, b) time_after(b, a)
1658 #define time_after_eq(a, b) ((long)((a) - (b)) >= 0)
1659 #define time_before_eq(a, b) time_after_eq(b, a)
1661 /*---bitmap support apis---*/
1662 static inline int axgbe_test_bit(int nr, volatile unsigned long *addr)
1667 res = ((*addr) & (1UL << nr)) != 0;
1672 static inline void axgbe_set_bit(unsigned int nr, volatile unsigned long *addr)
1674 __sync_fetch_and_or(addr, (1UL << nr));
1677 static inline void axgbe_clear_bit(int nr, volatile unsigned long *addr)
1679 __sync_fetch_and_and(addr, ~(1UL << nr));
1682 static inline int axgbe_test_and_clear_bit(int nr, volatile unsigned long *addr)
1684 unsigned long mask = (1UL << nr);
1686 return __sync_fetch_and_and(addr, ~mask) & mask;
1689 static inline unsigned long msecs_to_timer_cycles(unsigned int m)
1691 return rte_get_timer_hz() * (m / 1000);
1694 #endif /* __AXGBE_COMMON_H__ */