1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #ifndef __AXGBE_COMMON_H__
7 #define __AXGBE_COMMON_H__
9 #include "axgbe_logs.h"
13 #include <sys/queue.h>
24 #include <rte_bitops.h>
25 #include <rte_byteorder.h>
26 #include <rte_memory.h>
27 #include <rte_malloc.h>
28 #include <rte_hexdump.h>
30 #include <rte_debug.h>
31 #include <rte_branch_prediction.h>
33 #include <rte_memzone.h>
34 #include <rte_ether.h>
35 #include <rte_ethdev.h>
37 #include <rte_errno.h>
38 #include <ethdev_pci.h>
39 #include <rte_common.h>
40 #include <rte_cycles.h>
43 #define BIT(nr) (1 << (nr))
45 #define ARRAY_SIZE(arr) RTE_DIM(arr)
49 #define NSEC_PER_SEC 1000000000L
51 /* DMA register offsets */
53 #define DMA_SBMR 0x3004
54 #define DMA_ISR 0x3008
55 #define DMA_AXIARCR 0x3010
56 #define DMA_AXIAWCR 0x3018
57 #define DMA_AXIAWRCR 0x301c
58 #define DMA_DSR0 0x3020
59 #define DMA_DSR1 0x3024
60 #define EDMA_TX_CONTROL 0x3040
61 #define EDMA_RX_CONTROL 0x3044
63 /* DMA register entry bit positions and sizes */
64 #define DMA_AXIARCR_DRC_INDEX 0
65 #define DMA_AXIARCR_DRC_WIDTH 4
66 #define DMA_AXIARCR_DRD_INDEX 4
67 #define DMA_AXIARCR_DRD_WIDTH 2
68 #define DMA_AXIARCR_TEC_INDEX 8
69 #define DMA_AXIARCR_TEC_WIDTH 4
70 #define DMA_AXIARCR_TED_INDEX 12
71 #define DMA_AXIARCR_TED_WIDTH 2
72 #define DMA_AXIARCR_THC_INDEX 16
73 #define DMA_AXIARCR_THC_WIDTH 4
74 #define DMA_AXIARCR_THD_INDEX 20
75 #define DMA_AXIARCR_THD_WIDTH 2
76 #define DMA_AXIAWCR_DWC_INDEX 0
77 #define DMA_AXIAWCR_DWC_WIDTH 4
78 #define DMA_AXIAWCR_DWD_INDEX 4
79 #define DMA_AXIAWCR_DWD_WIDTH 2
80 #define DMA_AXIAWCR_RPC_INDEX 8
81 #define DMA_AXIAWCR_RPC_WIDTH 4
82 #define DMA_AXIAWCR_RPD_INDEX 12
83 #define DMA_AXIAWCR_RPD_WIDTH 2
84 #define DMA_AXIAWCR_RHC_INDEX 16
85 #define DMA_AXIAWCR_RHC_WIDTH 4
86 #define DMA_AXIAWCR_RHD_INDEX 20
87 #define DMA_AXIAWCR_RHD_WIDTH 2
88 #define DMA_AXIAWCR_RDC_INDEX 24
89 #define DMA_AXIAWCR_RDC_WIDTH 4
90 #define DMA_AXIAWCR_RDD_INDEX 28
91 #define DMA_AXIAWCR_RDD_WIDTH 2
92 #define DMA_AXIAWRCR_TDWC_INDEX 0
93 #define DMA_AXIAWRCR_TDWC_WIDTH 4
94 #define DMA_AXIAWRCR_TDWD_INDEX 4
95 #define DMA_AXIAWRCR_TDWD_WIDTH 4
96 #define DMA_AXIAWRCR_RDRC_INDEX 8
97 #define DMA_AXIAWRCR_RDRC_WIDTH 4
98 #define DMA_ISR_MACIS_INDEX 17
99 #define DMA_ISR_MACIS_WIDTH 1
100 #define DMA_ISR_MTLIS_INDEX 16
101 #define DMA_ISR_MTLIS_WIDTH 1
102 #define DMA_MR_INTM_INDEX 12
103 #define DMA_MR_INTM_WIDTH 2
104 #define DMA_MR_SWR_INDEX 0
105 #define DMA_MR_SWR_WIDTH 1
106 #define DMA_SBMR_WR_OSR_INDEX 24
107 #define DMA_SBMR_WR_OSR_WIDTH 6
108 #define DMA_SBMR_RD_OSR_INDEX 16
109 #define DMA_SBMR_RD_OSR_WIDTH 6
110 #define DMA_SBMR_AAL_INDEX 12
111 #define DMA_SBMR_AAL_WIDTH 1
112 #define DMA_SBMR_EAME_INDEX 11
113 #define DMA_SBMR_EAME_WIDTH 1
114 #define DMA_SBMR_BLEN_256_INDEX 7
115 #define DMA_SBMR_BLEN_256_WIDTH 1
116 #define DMA_SBMR_BLEN_32_INDEX 4
117 #define DMA_SBMR_BLEN_32_WIDTH 1
118 #define DMA_SBMR_UNDEF_INDEX 0
119 #define DMA_SBMR_UNDEF_WIDTH 1
121 /* DMA register values */
122 #define DMA_DSR_RPS_WIDTH 4
123 #define DMA_DSR_TPS_WIDTH 4
124 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
125 #define DMA_DSR0_RPS_START 8
126 #define DMA_DSR0_TPS_START 12
127 #define DMA_DSRX_FIRST_QUEUE 3
128 #define DMA_DSRX_INC 4
129 #define DMA_DSRX_QPR 4
130 #define DMA_DSRX_RPS_START 0
131 #define DMA_DSRX_TPS_START 4
132 #define DMA_TPS_STOPPED 0x00
133 #define DMA_TPS_SUSPENDED 0x06
135 /* DMA channel register offsets
136 * Multiple channels can be active. The first channel has registers
137 * that begin at 0x3100. Each subsequent channel has registers that
138 * are accessed using an offset of 0x80 from the previous channel.
140 #define DMA_CH_BASE 0x3100
141 #define DMA_CH_INC 0x80
143 #define DMA_CH_CR 0x00
144 #define DMA_CH_TCR 0x04
145 #define DMA_CH_RCR 0x08
146 #define DMA_CH_TDLR_HI 0x10
147 #define DMA_CH_TDLR_LO 0x14
148 #define DMA_CH_RDLR_HI 0x18
149 #define DMA_CH_RDLR_LO 0x1c
150 #define DMA_CH_TDTR_LO 0x24
151 #define DMA_CH_RDTR_LO 0x2c
152 #define DMA_CH_TDRLR 0x30
153 #define DMA_CH_RDRLR 0x34
154 #define DMA_CH_IER 0x38
155 #define DMA_CH_RIWT 0x3c
156 #define DMA_CH_CATDR_LO 0x44
157 #define DMA_CH_CARDR_LO 0x4c
158 #define DMA_CH_CATBR_HI 0x50
159 #define DMA_CH_CATBR_LO 0x54
160 #define DMA_CH_CARBR_HI 0x58
161 #define DMA_CH_CARBR_LO 0x5c
162 #define DMA_CH_SR 0x60
164 /* DMA channel register entry bit positions and sizes */
165 #define DMA_CH_CR_PBLX8_INDEX 16
166 #define DMA_CH_CR_PBLX8_WIDTH 1
167 #define DMA_CH_CR_SPH_INDEX 24
168 #define DMA_CH_CR_SPH_WIDTH 1
169 #define DMA_CH_IER_AIE_INDEX 14
170 #define DMA_CH_IER_AIE_WIDTH 1
171 #define DMA_CH_IER_FBEE_INDEX 12
172 #define DMA_CH_IER_FBEE_WIDTH 1
173 #define DMA_CH_IER_NIE_INDEX 15
174 #define DMA_CH_IER_NIE_WIDTH 1
175 #define DMA_CH_IER_RBUE_INDEX 7
176 #define DMA_CH_IER_RBUE_WIDTH 1
177 #define DMA_CH_IER_RIE_INDEX 6
178 #define DMA_CH_IER_RIE_WIDTH 1
179 #define DMA_CH_IER_RSE_INDEX 8
180 #define DMA_CH_IER_RSE_WIDTH 1
181 #define DMA_CH_IER_TBUE_INDEX 2
182 #define DMA_CH_IER_TBUE_WIDTH 1
183 #define DMA_CH_IER_TIE_INDEX 0
184 #define DMA_CH_IER_TIE_WIDTH 1
185 #define DMA_CH_IER_TXSE_INDEX 1
186 #define DMA_CH_IER_TXSE_WIDTH 1
187 #define DMA_CH_RCR_PBL_INDEX 16
188 #define DMA_CH_RCR_PBL_WIDTH 6
189 #define DMA_CH_RCR_RBSZ_INDEX 1
190 #define DMA_CH_RCR_RBSZ_WIDTH 14
191 #define DMA_CH_RCR_SR_INDEX 0
192 #define DMA_CH_RCR_SR_WIDTH 1
193 #define DMA_CH_RIWT_RWT_INDEX 0
194 #define DMA_CH_RIWT_RWT_WIDTH 8
195 #define DMA_CH_SR_FBE_INDEX 12
196 #define DMA_CH_SR_FBE_WIDTH 1
197 #define DMA_CH_SR_RBU_INDEX 7
198 #define DMA_CH_SR_RBU_WIDTH 1
199 #define DMA_CH_SR_RI_INDEX 6
200 #define DMA_CH_SR_RI_WIDTH 1
201 #define DMA_CH_SR_RPS_INDEX 8
202 #define DMA_CH_SR_RPS_WIDTH 1
203 #define DMA_CH_SR_TBU_INDEX 2
204 #define DMA_CH_SR_TBU_WIDTH 1
205 #define DMA_CH_SR_TI_INDEX 0
206 #define DMA_CH_SR_TI_WIDTH 1
207 #define DMA_CH_SR_TPS_INDEX 1
208 #define DMA_CH_SR_TPS_WIDTH 1
209 #define DMA_CH_TCR_OSP_INDEX 4
210 #define DMA_CH_TCR_OSP_WIDTH 1
211 #define DMA_CH_TCR_PBL_INDEX 16
212 #define DMA_CH_TCR_PBL_WIDTH 6
213 #define DMA_CH_TCR_ST_INDEX 0
214 #define DMA_CH_TCR_ST_WIDTH 1
215 #define DMA_CH_TCR_TSE_INDEX 12
216 #define DMA_CH_TCR_TSE_WIDTH 1
218 /* DMA channel register values */
219 #define DMA_OSP_DISABLE 0x00
220 #define DMA_OSP_ENABLE 0x01
225 #define DMA_PBL_16 16
226 #define DMA_PBL_32 32
227 #define DMA_PBL_64 64 /* 8 x 8 */
228 #define DMA_PBL_128 128 /* 8 x 16 */
229 #define DMA_PBL_256 256 /* 8 x 32 */
230 #define DMA_PBL_X8_DISABLE 0x00
231 #define DMA_PBL_X8_ENABLE 0x01
233 /* MAC register offsets */
234 #define MAC_TCR 0x0000
235 #define MAC_RCR 0x0004
236 #define MAC_PFR 0x0008
237 #define MAC_WTR 0x000c
238 #define MAC_HTR0 0x0010
239 #define MAC_VLANTR 0x0050
240 #define MAC_VLANHTR 0x0058
241 #define MAC_VLANIR 0x0060
242 #define MAC_IVLANIR 0x0064
243 #define MAC_RETMR 0x006c
244 #define MAC_Q0TFCR 0x0070
245 #define MAC_RFCR 0x0090
246 #define MAC_RQC0R 0x00a0
247 #define MAC_RQC1R 0x00a4
248 #define MAC_RQC2R 0x00a8
249 #define MAC_RQC3R 0x00ac
250 #define MAC_ISR 0x00b0
251 #define MAC_IER 0x00b4
252 #define MAC_RTSR 0x00b8
253 #define MAC_PMTCSR 0x00c0
254 #define MAC_RWKPFR 0x00c4
255 #define MAC_LPICSR 0x00d0
256 #define MAC_LPITCR 0x00d4
257 #define MAC_VR 0x0110
258 #define MAC_DR 0x0114
259 #define MAC_HWF0R 0x011c
260 #define MAC_HWF1R 0x0120
261 #define MAC_HWF2R 0x0124
262 #define MAC_HWF3R 0x0128
263 #define MAC_MDIOSCAR 0x0200
264 #define MAC_MDIOSCCDR 0x0204
265 #define MAC_MDIOISR 0x0214
266 #define MAC_MDIOIER 0x0218
267 #define MAC_MDIOCL22R 0x0220
268 #define MAC_GPIOCR 0x0278
269 #define MAC_GPIOSR 0x027c
270 #define MAC_MACA0HR 0x0300
271 #define MAC_MACA0LR 0x0304
272 #define MAC_MACA1HR 0x0308
273 #define MAC_MACA1LR 0x030c
274 #define MAC_RSSCR 0x0c80
275 #define MAC_RSSAR 0x0c88
276 #define MAC_RSSDR 0x0c8c
277 #define MAC_TSCR 0x0d00
278 #define MAC_SSIR 0x0d04
279 #define MAC_STSR 0x0d08
280 #define MAC_STNR 0x0d0c
281 #define MAC_STSUR 0x0d10
282 #define MAC_STNUR 0x0d14
283 #define MAC_TSAR 0x0d18
284 #define MAC_TSSR 0x0d20
285 #define MAC_TXSNR 0x0d30
286 #define MAC_TXSSR 0x0d34
288 /*VLAN control bit mask*/
289 #define AXGBE_VLNCTRL_MASK 0x0000FFFF
290 #define VLAN_PRIO_MASK 0xe000 /* Priority Code Point */
291 #define VLAN_PRIO_SHIFT 13
292 #define VLAN_CFI_MASK 0x1000 /* Canonical Format Indicator */
293 #define VLAN_TAG_PRESENT VLAN_CFI_MASK
294 #define VLAN_VID_MASK 0x0fff /* VLAN Identifier */
295 #define VLAN_N_VID 4096
296 #define VLAN_TABLE_SIZE 64
297 #define VLAN_TABLE_BIT(vlan_id) (1UL << ((vlan_id) & 0x3F))
298 #define VLAN_TABLE_IDX(vlan_id) ((vlan_id) >> 6)
299 #define RX_CVLAN_TAG_PRESENT 9
301 #define MAC_QTFCR_INC 4
302 #define MAC_MACA_INC 4
303 #define MAC_HTR_INC 4
305 #define MAC_RQC2_INC 4
306 #define MAC_RQC2_Q_PER_REG 4
308 #define MAC_MACAHR(i) (MAC_MACA0HR + ((i) * 8))
309 #define MAC_MACALR(i) (MAC_MACA0LR + ((i) * 8))
311 #define MAC_HTR(i) (MAC_HTR0 + ((i) * MAC_HTR_INC))
313 /* MAC register entry bit positions and sizes */
314 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18
315 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
316 #define MAC_HWF0R_ARPOFFSEL_INDEX 9
317 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1
318 #define MAC_HWF0R_EEESEL_INDEX 13
319 #define MAC_HWF0R_EEESEL_WIDTH 1
320 #define MAC_HWF0R_GMIISEL_INDEX 1
321 #define MAC_HWF0R_GMIISEL_WIDTH 1
322 #define MAC_HWF0R_MGKSEL_INDEX 7
323 #define MAC_HWF0R_MGKSEL_WIDTH 1
324 #define MAC_HWF0R_MMCSEL_INDEX 8
325 #define MAC_HWF0R_MMCSEL_WIDTH 1
326 #define MAC_HWF0R_RWKSEL_INDEX 6
327 #define MAC_HWF0R_RWKSEL_WIDTH 1
328 #define MAC_HWF0R_RXCOESEL_INDEX 16
329 #define MAC_HWF0R_RXCOESEL_WIDTH 1
330 #define MAC_HWF0R_SAVLANINS_INDEX 27
331 #define MAC_HWF0R_SAVLANINS_WIDTH 1
332 #define MAC_HWF0R_SMASEL_INDEX 5
333 #define MAC_HWF0R_SMASEL_WIDTH 1
334 #define MAC_HWF0R_TSSEL_INDEX 12
335 #define MAC_HWF0R_TSSEL_WIDTH 1
336 #define MAC_HWF0R_TSSTSSEL_INDEX 25
337 #define MAC_HWF0R_TSSTSSEL_WIDTH 2
338 #define MAC_HWF0R_TXCOESEL_INDEX 14
339 #define MAC_HWF0R_TXCOESEL_WIDTH 1
340 #define MAC_HWF0R_VLHASH_INDEX 4
341 #define MAC_HWF0R_VLHASH_WIDTH 1
342 #define MAC_HWF1R_ADDR64_INDEX 14
343 #define MAC_HWF1R_ADDR64_WIDTH 2
344 #define MAC_HWF1R_ADVTHWORD_INDEX 13
345 #define MAC_HWF1R_ADVTHWORD_WIDTH 1
346 #define MAC_HWF1R_DBGMEMA_INDEX 19
347 #define MAC_HWF1R_DBGMEMA_WIDTH 1
348 #define MAC_HWF1R_DCBEN_INDEX 16
349 #define MAC_HWF1R_DCBEN_WIDTH 1
350 #define MAC_HWF1R_HASHTBLSZ_INDEX 24
351 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3
352 #define MAC_HWF1R_L3L4FNUM_INDEX 27
353 #define MAC_HWF1R_L3L4FNUM_WIDTH 4
354 #define MAC_HWF1R_NUMTC_INDEX 21
355 #define MAC_HWF1R_NUMTC_WIDTH 3
356 #define MAC_HWF1R_RSSEN_INDEX 20
357 #define MAC_HWF1R_RSSEN_WIDTH 1
358 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0
359 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5
360 #define MAC_HWF1R_SPHEN_INDEX 17
361 #define MAC_HWF1R_SPHEN_WIDTH 1
362 #define MAC_HWF1R_TSOEN_INDEX 18
363 #define MAC_HWF1R_TSOEN_WIDTH 1
364 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6
365 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5
366 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28
367 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3
368 #define MAC_HWF2R_PPSOUTNUM_INDEX 24
369 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3
370 #define MAC_HWF2R_RXCHCNT_INDEX 12
371 #define MAC_HWF2R_RXCHCNT_WIDTH 4
372 #define MAC_HWF2R_RXQCNT_INDEX 0
373 #define MAC_HWF2R_RXQCNT_WIDTH 4
374 #define MAC_HWF2R_TXCHCNT_INDEX 18
375 #define MAC_HWF2R_TXCHCNT_WIDTH 4
376 #define MAC_HWF2R_TXQCNT_INDEX 6
377 #define MAC_HWF2R_TXQCNT_WIDTH 4
378 #define MAC_HWF3R_CBTISEL_INDEX 4
379 #define MAC_HWF3R_CBTISEL_WIDTH 1
380 #define MAC_HWF3R_NRVF_INDEX 0
381 #define MAC_HWF3R_NRVF_WIDTH 3
382 #define MAC_IER_TSIE_INDEX 12
383 #define MAC_IER_TSIE_WIDTH 1
384 #define MAC_ISR_MMCRXIS_INDEX 9
385 #define MAC_ISR_MMCRXIS_WIDTH 1
386 #define MAC_ISR_MMCTXIS_INDEX 10
387 #define MAC_ISR_MMCTXIS_WIDTH 1
388 #define MAC_ISR_PMTIS_INDEX 4
389 #define MAC_ISR_PMTIS_WIDTH 1
390 #define MAC_ISR_SMI_INDEX 1
391 #define MAC_ISR_SMI_WIDTH 1
392 #define MAC_ISR_LSI_INDEX 0
393 #define MAC_ISR_LSI_WIDTH 1
394 #define MAC_ISR_LS_INDEX 24
395 #define MAC_ISR_LS_WIDTH 2
396 #define MAC_ISR_TSIS_INDEX 12
397 #define MAC_ISR_TSIS_WIDTH 1
398 #define MAC_MACA1HR_AE_INDEX 31
399 #define MAC_MACA1HR_AE_WIDTH 1
400 #define MAC_MDIOIER_SNGLCOMPIE_INDEX 12
401 #define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1
402 #define MAC_MDIOISR_SNGLCOMPINT_INDEX 12
403 #define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1
404 #define MAC_MDIOSCAR_DA_INDEX 21
405 #define MAC_MDIOSCAR_DA_WIDTH 5
406 #define MAC_MDIOSCAR_PA_INDEX 16
407 #define MAC_MDIOSCAR_PA_WIDTH 5
408 #define MAC_MDIOSCAR_RA_INDEX 0
409 #define MAC_MDIOSCAR_RA_WIDTH 16
410 #define MAC_MDIOSCAR_REG_INDEX 0
411 #define MAC_MDIOSCAR_REG_WIDTH 21
412 #define MAC_MDIOSCCDR_BUSY_INDEX 22
413 #define MAC_MDIOSCCDR_BUSY_WIDTH 1
414 #define MAC_MDIOSCCDR_CMD_INDEX 16
415 #define MAC_MDIOSCCDR_CMD_WIDTH 2
416 #define MAC_MDIOSCCDR_CR_INDEX 19
417 #define MAC_MDIOSCCDR_CR_WIDTH 3
418 #define MAC_MDIOSCCDR_DATA_INDEX 0
419 #define MAC_MDIOSCCDR_DATA_WIDTH 16
420 #define MAC_MDIOSCCDR_SADDR_INDEX 18
421 #define MAC_MDIOSCCDR_SADDR_WIDTH 1
422 #define MAC_PFR_HMC_INDEX 2
423 #define MAC_PFR_HMC_WIDTH 1
424 #define MAC_PFR_HPF_INDEX 10
425 #define MAC_PFR_HPF_WIDTH 1
426 #define MAC_PFR_HUC_INDEX 1
427 #define MAC_PFR_HUC_WIDTH 1
428 #define MAC_PFR_PM_INDEX 4
429 #define MAC_PFR_PM_WIDTH 1
430 #define MAC_PFR_PR_INDEX 0
431 #define MAC_PFR_PR_WIDTH 1
432 #define MAC_PFR_VTFE_INDEX 16
433 #define MAC_PFR_VTFE_WIDTH 1
434 #define MAC_PMTCSR_MGKPKTEN_INDEX 1
435 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1
436 #define MAC_PMTCSR_PWRDWN_INDEX 0
437 #define MAC_PMTCSR_PWRDWN_WIDTH 1
438 #define MAC_PMTCSR_RWKFILTRST_INDEX 31
439 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1
440 #define MAC_PMTCSR_RWKPKTEN_INDEX 2
441 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1
442 #define MAC_Q0TFCR_PT_INDEX 16
443 #define MAC_Q0TFCR_PT_WIDTH 16
444 #define MAC_Q0TFCR_TFE_INDEX 1
445 #define MAC_Q0TFCR_TFE_WIDTH 1
446 #define MAC_RCR_ACS_INDEX 1
447 #define MAC_RCR_ACS_WIDTH 1
448 #define MAC_RCR_CST_INDEX 2
449 #define MAC_RCR_CST_WIDTH 1
450 #define MAC_RCR_DCRCC_INDEX 3
451 #define MAC_RCR_DCRCC_WIDTH 1
452 #define MAC_RCR_HDSMS_INDEX 12
453 #define MAC_RCR_HDSMS_WIDTH 3
454 #define MAC_RCR_IPC_INDEX 9
455 #define MAC_RCR_IPC_WIDTH 1
456 #define MAC_RCR_JE_INDEX 8
457 #define MAC_RCR_JE_WIDTH 1
458 #define MAC_RCR_LM_INDEX 10
459 #define MAC_RCR_LM_WIDTH 1
460 #define MAC_RCR_RE_INDEX 0
461 #define MAC_RCR_RE_WIDTH 1
462 #define MAC_RFCR_PFCE_INDEX 8
463 #define MAC_RFCR_PFCE_WIDTH 1
464 #define MAC_RFCR_RFE_INDEX 0
465 #define MAC_RFCR_RFE_WIDTH 1
466 #define MAC_RFCR_UP_INDEX 1
467 #define MAC_RFCR_UP_WIDTH 1
468 #define MAC_RQC0R_RXQ0EN_INDEX 0
469 #define MAC_RQC0R_RXQ0EN_WIDTH 2
470 #define MAC_RSSAR_ADDRT_INDEX 2
471 #define MAC_RSSAR_ADDRT_WIDTH 1
472 #define MAC_RSSAR_CT_INDEX 1
473 #define MAC_RSSAR_CT_WIDTH 1
474 #define MAC_RSSAR_OB_INDEX 0
475 #define MAC_RSSAR_OB_WIDTH 1
476 #define MAC_RSSAR_RSSIA_INDEX 8
477 #define MAC_RSSAR_RSSIA_WIDTH 8
478 #define MAC_RSSCR_IP2TE_INDEX 1
479 #define MAC_RSSCR_IP2TE_WIDTH 1
480 #define MAC_RSSCR_RSSE_INDEX 0
481 #define MAC_RSSCR_RSSE_WIDTH 1
482 #define MAC_RSSCR_TCP4TE_INDEX 2
483 #define MAC_RSSCR_TCP4TE_WIDTH 1
484 #define MAC_RSSCR_UDP4TE_INDEX 3
485 #define MAC_RSSCR_UDP4TE_WIDTH 1
486 #define MAC_RSSDR_DMCH_INDEX 0
487 #define MAC_RSSDR_DMCH_WIDTH 4
488 #define MAC_SSIR_SNSINC_INDEX 8
489 #define MAC_SSIR_SNSINC_WIDTH 8
490 #define MAC_SSIR_SSINC_INDEX 16
491 #define MAC_SSIR_SSINC_WIDTH 8
492 #define MAC_TCR_SS_INDEX 29
493 #define MAC_TCR_SS_WIDTH 2
494 #define MAC_TCR_TE_INDEX 0
495 #define MAC_TCR_TE_WIDTH 1
496 #define MAC_TSCR_AV8021ASMEN_INDEX 28
497 #define MAC_TSCR_AV8021ASMEN_WIDTH 1
498 #define MAC_TSCR_SNAPTYPSEL_INDEX 16
499 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2
500 #define MAC_TSCR_TSADDREG_INDEX 5
501 #define MAC_TSCR_TSADDREG_WIDTH 1
502 #define MAC_TSCR_TSCFUPDT_INDEX 1
503 #define MAC_TSCR_TSCFUPDT_WIDTH 1
504 #define MAC_TSCR_TSCTRLSSR_INDEX 9
505 #define MAC_TSCR_TSCTRLSSR_WIDTH 1
506 #define MAC_TSCR_TSENA_INDEX 0
507 #define MAC_TSCR_TSENA_WIDTH 1
508 #define MAC_TSCR_TSENALL_INDEX 8
509 #define MAC_TSCR_TSENALL_WIDTH 1
510 #define MAC_TSCR_TSEVNTENA_INDEX 14
511 #define MAC_TSCR_TSEVNTENA_WIDTH 1
512 #define MAC_TSCR_TSINIT_INDEX 2
513 #define MAC_TSCR_TSINIT_WIDTH 1
514 #define MAC_TSCR_TSUPDT_INDEX 3
515 #define MAC_TSCR_TSUPDT_WIDTH 1
516 #define MAC_TSCR_TSIPENA_INDEX 11
517 #define MAC_TSCR_TSIPENA_WIDTH 1
518 #define MAC_TSCR_TSIPV4ENA_INDEX 13
519 #define MAC_TSCR_TSIPV4ENA_WIDTH 1
520 #define MAC_TSCR_TSIPV6ENA_INDEX 12
521 #define MAC_TSCR_TSIPV6ENA_WIDTH 1
522 #define MAC_TSCR_TSMSTRENA_INDEX 15
523 #define MAC_TSCR_TSMSTRENA_WIDTH 1
524 #define MAC_TSCR_TSVER2ENA_INDEX 10
525 #define MAC_TSCR_TSVER2ENA_WIDTH 1
526 #define MAC_TSCR_TXTSSTSM_INDEX 24
527 #define MAC_TSCR_TXTSSTSM_WIDTH 1
528 #define MAC_TSSR_TXTSC_INDEX 15
529 #define MAC_TSSR_TXTSC_WIDTH 1
530 #define MAC_STNUR_ADDSUB_INDEX 31
531 #define MAC_STNUR_ADDSUB_WIDTH 1
532 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31
533 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1
534 #define MAC_VLANHTR_VLHT_INDEX 0
535 #define MAC_VLANHTR_VLHT_WIDTH 16
536 #define MAC_VLANIR_VLTI_INDEX 20
537 #define MAC_VLANIR_VLTI_WIDTH 1
538 #define MAC_VLANIR_CSVL_INDEX 19
539 #define MAC_VLANIR_CSVL_WIDTH 1
540 #define MAC_VLANIR_VLC_INDEX 16
541 #define MAC_VLANIR_VLC_WIDTH 2
542 #define MAC_VLANTR_DOVLTC_INDEX 20
543 #define MAC_VLANTR_DOVLTC_WIDTH 1
544 #define MAC_VLANTR_ERSVLM_INDEX 19
545 #define MAC_VLANTR_ERSVLM_WIDTH 1
546 #define MAC_VLANTR_ESVL_INDEX 18
547 #define MAC_VLANTR_ESVL_WIDTH 1
548 #define MAC_VLANTR_ETV_INDEX 16
549 #define MAC_VLANTR_ETV_WIDTH 1
550 #define MAC_VLANTR_EVLS_INDEX 21
551 #define MAC_VLANTR_EVLS_WIDTH 2
552 #define MAC_VLANTR_EIVLS_INDEX 21
553 #define MAC_VLANTR_EIVLS_WIDTH 2
554 #define MAC_VLANTR_EVLRXS_INDEX 24
555 #define MAC_VLANTR_EVLRXS_WIDTH 1
556 #define MAC_VLANTR_EIVLRXS_INDEX 31
557 #define MAC_VLANTR_EIVLRXS_WIDTH 1
558 #define MAC_VLANTR_VL_INDEX 0
559 #define MAC_VLANTR_VL_WIDTH 16
560 #define MAC_VLANTR_VTHM_INDEX 25
561 #define MAC_VLANTR_VTHM_WIDTH 1
562 #define MAC_VLANTR_EDVLP_INDEX 26
563 #define MAC_VLANTR_EDVLP_WIDTH 1
564 #define MAC_VLANTR_VTIM_INDEX 17
565 #define MAC_VLANTR_VTIM_WIDTH 1
566 #define MAC_VR_DEVID_INDEX 8
567 #define MAC_VR_DEVID_WIDTH 8
568 #define MAC_VR_SNPSVER_INDEX 0
569 #define MAC_VR_SNPSVER_WIDTH 8
570 #define MAC_VR_USERVER_INDEX 16
571 #define MAC_VR_USERVER_WIDTH 8
572 #define MAC_VLANIR_VLT_INDEX 0
573 #define MAC_VLANIR_VLT_WIDTH 16
574 #define MAC_VLANTR_ERIVLT_INDEX 27
575 #define MAC_VLANTR_ERIVLT_WIDTH 1
578 /* MMC register offsets */
579 #define MMC_CR 0x0800
580 #define MMC_RISR 0x0804
581 #define MMC_TISR 0x0808
582 #define MMC_RIER 0x080c
583 #define MMC_TIER 0x0810
584 #define MMC_TXOCTETCOUNT_GB_LO 0x0814
585 #define MMC_TXOCTETCOUNT_GB_HI 0x0818
586 #define MMC_TXFRAMECOUNT_GB_LO 0x081c
587 #define MMC_TXFRAMECOUNT_GB_HI 0x0820
588 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824
589 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828
590 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c
591 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830
592 #define MMC_TX64OCTETS_GB_LO 0x0834
593 #define MMC_TX64OCTETS_GB_HI 0x0838
594 #define MMC_TX65TO127OCTETS_GB_LO 0x083c
595 #define MMC_TX65TO127OCTETS_GB_HI 0x0840
596 #define MMC_TX128TO255OCTETS_GB_LO 0x0844
597 #define MMC_TX128TO255OCTETS_GB_HI 0x0848
598 #define MMC_TX256TO511OCTETS_GB_LO 0x084c
599 #define MMC_TX256TO511OCTETS_GB_HI 0x0850
600 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854
601 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858
602 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
603 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860
604 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864
605 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868
606 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
607 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870
608 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
609 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878
610 #define MMC_TXUNDERFLOWERROR_LO 0x087c
611 #define MMC_TXUNDERFLOWERROR_HI 0x0880
612 #define MMC_TXOCTETCOUNT_G_LO 0x0884
613 #define MMC_TXOCTETCOUNT_G_HI 0x0888
614 #define MMC_TXFRAMECOUNT_G_LO 0x088c
615 #define MMC_TXFRAMECOUNT_G_HI 0x0890
616 #define MMC_TXPAUSEFRAMES_LO 0x0894
617 #define MMC_TXPAUSEFRAMES_HI 0x0898
618 #define MMC_TXVLANFRAMES_G_LO 0x089c
619 #define MMC_TXVLANFRAMES_G_HI 0x08a0
620 #define MMC_RXFRAMECOUNT_GB_LO 0x0900
621 #define MMC_RXFRAMECOUNT_GB_HI 0x0904
622 #define MMC_RXOCTETCOUNT_GB_LO 0x0908
623 #define MMC_RXOCTETCOUNT_GB_HI 0x090c
624 #define MMC_RXOCTETCOUNT_G_LO 0x0910
625 #define MMC_RXOCTETCOUNT_G_HI 0x0914
626 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918
627 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c
628 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920
629 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924
630 #define MMC_RXCRCERROR_LO 0x0928
631 #define MMC_RXCRCERROR_HI 0x092c
632 #define MMC_RXRUNTERROR 0x0930
633 #define MMC_RXJABBERERROR 0x0934
634 #define MMC_RXUNDERSIZE_G 0x0938
635 #define MMC_RXOVERSIZE_G 0x093c
636 #define MMC_RX64OCTETS_GB_LO 0x0940
637 #define MMC_RX64OCTETS_GB_HI 0x0944
638 #define MMC_RX65TO127OCTETS_GB_LO 0x0948
639 #define MMC_RX65TO127OCTETS_GB_HI 0x094c
640 #define MMC_RX128TO255OCTETS_GB_LO 0x0950
641 #define MMC_RX128TO255OCTETS_GB_HI 0x0954
642 #define MMC_RX256TO511OCTETS_GB_LO 0x0958
643 #define MMC_RX256TO511OCTETS_GB_HI 0x095c
644 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960
645 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964
646 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
647 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c
648 #define MMC_RXUNICASTFRAMES_G_LO 0x0970
649 #define MMC_RXUNICASTFRAMES_G_HI 0x0974
650 #define MMC_RXLENGTHERROR_LO 0x0978
651 #define MMC_RXLENGTHERROR_HI 0x097c
652 #define MMC_RXOUTOFRANGETYPE_LO 0x0980
653 #define MMC_RXOUTOFRANGETYPE_HI 0x0984
654 #define MMC_RXPAUSEFRAMES_LO 0x0988
655 #define MMC_RXPAUSEFRAMES_HI 0x098c
656 #define MMC_RXFIFOOVERFLOW_LO 0x0990
657 #define MMC_RXFIFOOVERFLOW_HI 0x0994
658 #define MMC_RXVLANFRAMES_GB_LO 0x0998
659 #define MMC_RXVLANFRAMES_GB_HI 0x099c
660 #define MMC_RXWATCHDOGERROR 0x09a0
662 /* MMC register entry bit positions and sizes */
663 #define MMC_CR_CR_INDEX 0
664 #define MMC_CR_CR_WIDTH 1
665 #define MMC_CR_CSR_INDEX 1
666 #define MMC_CR_CSR_WIDTH 1
667 #define MMC_CR_ROR_INDEX 2
668 #define MMC_CR_ROR_WIDTH 1
669 #define MMC_CR_MCF_INDEX 3
670 #define MMC_CR_MCF_WIDTH 1
671 #define MMC_CR_MCT_INDEX 4
672 #define MMC_CR_MCT_WIDTH 2
673 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0
674 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23
675 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0
676 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1
677 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1
678 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1
679 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2
680 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1
681 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3
682 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1
683 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4
684 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1
685 #define MMC_RISR_RXCRCERROR_INDEX 5
686 #define MMC_RISR_RXCRCERROR_WIDTH 1
687 #define MMC_RISR_RXRUNTERROR_INDEX 6
688 #define MMC_RISR_RXRUNTERROR_WIDTH 1
689 #define MMC_RISR_RXJABBERERROR_INDEX 7
690 #define MMC_RISR_RXJABBERERROR_WIDTH 1
691 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8
692 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1
693 #define MMC_RISR_RXOVERSIZE_G_INDEX 9
694 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1
695 #define MMC_RISR_RX64OCTETS_GB_INDEX 10
696 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1
697 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11
698 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1
699 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12
700 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1
701 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13
702 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1
703 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14
704 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1
705 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15
706 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1
707 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16
708 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1
709 #define MMC_RISR_RXLENGTHERROR_INDEX 17
710 #define MMC_RISR_RXLENGTHERROR_WIDTH 1
711 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18
712 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1
713 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19
714 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1
715 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20
716 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1
717 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21
718 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1
719 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22
720 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1
721 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0
722 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18
723 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0
724 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1
725 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1
726 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1
727 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2
728 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1
729 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3
730 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1
731 #define MMC_TISR_TX64OCTETS_GB_INDEX 4
732 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1
733 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5
734 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1
735 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6
736 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1
737 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7
738 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1
739 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8
740 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1
741 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9
742 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1
743 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10
744 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1
745 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11
746 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1
747 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12
748 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1
749 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13
750 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1
751 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14
752 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1
753 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15
754 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1
755 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16
756 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1
757 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17
758 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1
760 /* MTL register offsets */
761 #define MTL_OMR 0x1000
762 #define MTL_FDCR 0x1008
763 #define MTL_FDSR 0x100c
764 #define MTL_FDDR 0x1010
765 #define MTL_ISR 0x1020
766 #define MTL_RQDCM0R 0x1030
767 #define MTL_TCPM0R 0x1040
768 #define MTL_TCPM1R 0x1044
770 #define MTL_RQDCM_INC 4
771 #define MTL_RQDCM_Q_PER_REG 4
772 #define MTL_TCPM_INC 4
773 #define MTL_TCPM_TC_PER_REG 4
775 /* MTL register entry bit positions and sizes */
776 #define MTL_OMR_ETSALG_INDEX 5
777 #define MTL_OMR_ETSALG_WIDTH 2
778 #define MTL_OMR_RAA_INDEX 2
779 #define MTL_OMR_RAA_WIDTH 1
781 /* MTL queue register offsets
782 * Multiple queues can be active. The first queue has registers
783 * that begin at 0x1100. Each subsequent queue has registers that
784 * are accessed using an offset of 0x80 from the previous queue.
786 #define MTL_Q_BASE 0x1100
787 #define MTL_Q_INC 0x80
789 #define MTL_Q_TQOMR 0x00
790 #define MTL_Q_TQUR 0x04
791 #define MTL_Q_TQDR 0x08
792 #define MTL_Q_RQOMR 0x40
793 #define MTL_Q_RQMPOCR 0x44
794 #define MTL_Q_RQDR 0x48
795 #define MTL_Q_RQFCR 0x50
796 #define MTL_Q_IER 0x70
797 #define MTL_Q_ISR 0x74
799 /* MTL queue register entry bit positions and sizes */
800 #define MTL_Q_RQDR_PRXQ_INDEX 16
801 #define MTL_Q_RQDR_PRXQ_WIDTH 14
802 #define MTL_Q_RQDR_RXQSTS_INDEX 4
803 #define MTL_Q_RQDR_RXQSTS_WIDTH 2
804 #define MTL_Q_RQFCR_RFA_INDEX 1
805 #define MTL_Q_RQFCR_RFA_WIDTH 6
806 #define MTL_Q_RQFCR_RFD_INDEX 17
807 #define MTL_Q_RQFCR_RFD_WIDTH 6
808 #define MTL_Q_RQOMR_EHFC_INDEX 7
809 #define MTL_Q_RQOMR_EHFC_WIDTH 1
810 #define MTL_Q_RQOMR_RQS_INDEX 16
811 #define MTL_Q_RQOMR_RQS_WIDTH 9
812 #define MTL_Q_RQOMR_RSF_INDEX 5
813 #define MTL_Q_RQOMR_RSF_WIDTH 1
814 #define MTL_Q_RQOMR_RTC_INDEX 0
815 #define MTL_Q_RQOMR_RTC_WIDTH 2
816 #define MTL_Q_TQDR_TRCSTS_INDEX 1
817 #define MTL_Q_TQDR_TRCSTS_WIDTH 2
818 #define MTL_Q_TQDR_TXQSTS_INDEX 4
819 #define MTL_Q_TQDR_TXQSTS_WIDTH 1
820 #define MTL_Q_TQOMR_FTQ_INDEX 0
821 #define MTL_Q_TQOMR_FTQ_WIDTH 1
822 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8
823 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3
824 #define MTL_Q_TQOMR_TQS_INDEX 16
825 #define MTL_Q_TQOMR_TQS_WIDTH 10
826 #define MTL_Q_TQOMR_TSF_INDEX 1
827 #define MTL_Q_TQOMR_TSF_WIDTH 1
828 #define MTL_Q_TQOMR_TTC_INDEX 4
829 #define MTL_Q_TQOMR_TTC_WIDTH 3
830 #define MTL_Q_TQOMR_TXQEN_INDEX 2
831 #define MTL_Q_TQOMR_TXQEN_WIDTH 2
833 /* MTL queue register value */
834 #define MTL_RSF_DISABLE 0x00
835 #define MTL_RSF_ENABLE 0x01
836 #define MTL_TSF_DISABLE 0x00
837 #define MTL_TSF_ENABLE 0x01
839 #define MTL_RX_THRESHOLD_64 0x00
840 #define MTL_RX_THRESHOLD_96 0x02
841 #define MTL_RX_THRESHOLD_128 0x03
842 #define MTL_TX_THRESHOLD_32 0x01
843 #define MTL_TX_THRESHOLD_64 0x00
844 #define MTL_TX_THRESHOLD_96 0x02
845 #define MTL_TX_THRESHOLD_128 0x03
846 #define MTL_TX_THRESHOLD_192 0x04
847 #define MTL_TX_THRESHOLD_256 0x05
848 #define MTL_TX_THRESHOLD_384 0x06
849 #define MTL_TX_THRESHOLD_512 0x07
851 #define MTL_ETSALG_WRR 0x00
852 #define MTL_ETSALG_WFQ 0x01
853 #define MTL_ETSALG_DWRR 0x02
854 #define MTL_RAA_SP 0x00
855 #define MTL_RAA_WSP 0x01
857 #define MTL_Q_DISABLED 0x00
858 #define MTL_Q_ENABLED 0x02
860 /* MTL traffic class register offsets
861 * Multiple traffic classes can be active. The first class has registers
862 * that begin at 0x1100. Each subsequent queue has registers that
863 * are accessed using an offset of 0x80 from the previous queue.
865 #define MTL_TC_BASE MTL_Q_BASE
866 #define MTL_TC_INC MTL_Q_INC
868 #define MTL_TC_ETSCR 0x10
869 #define MTL_TC_ETSSR 0x14
870 #define MTL_TC_QWR 0x18
872 /* MTL traffic class register entry bit positions and sizes */
873 #define MTL_TC_ETSCR_TSA_INDEX 0
874 #define MTL_TC_ETSCR_TSA_WIDTH 2
875 #define MTL_TC_QWR_QW_INDEX 0
876 #define MTL_TC_QWR_QW_WIDTH 21
877 #define MTL_TCPM0R_PSTC0_INDEX 0
878 #define MTL_TCPM0R_PSTC0_WIDTH 8
879 #define MTL_TCPM0R_PSTC1_INDEX 8
880 #define MTL_TCPM0R_PSTC1_WIDTH 8
881 #define MTL_TCPM0R_PSTC2_INDEX 16
882 #define MTL_TCPM0R_PSTC2_WIDTH 8
883 #define MTL_TCPM0R_PSTC3_INDEX 24
884 #define MTL_TCPM0R_PSTC3_WIDTH 8
885 #define MTL_TCPM1R_PSTC4_INDEX 0
886 #define MTL_TCPM1R_PSTC4_WIDTH 8
887 #define MTL_TCPM1R_PSTC5_INDEX 8
888 #define MTL_TCPM1R_PSTC5_WIDTH 8
889 #define MTL_TCPM1R_PSTC6_INDEX 16
890 #define MTL_TCPM1R_PSTC6_WIDTH 8
891 #define MTL_TCPM1R_PSTC7_INDEX 24
892 #define MTL_TCPM1R_PSTC7_WIDTH 8
894 /* MTL traffic class register value */
895 #define MTL_TSA_SP 0x00
896 #define MTL_TSA_ETS 0x02
898 /* PCS register offsets */
899 #define PCS_V1_WINDOW_SELECT 0x03fc
900 #define PCS_V2_WINDOW_DEF 0x9060
901 #define PCS_V2_WINDOW_SELECT 0x9064
902 #define PCS_V2_RV_WINDOW_DEF 0x1060
903 #define PCS_V2_RV_WINDOW_SELECT 0x1064
904 #define PCS_V2_YC_WINDOW_DEF 0x18060
905 #define PCS_V2_YC_WINDOW_SELECT 0x18064
907 /* PCS register entry bit positions and sizes */
908 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
909 #define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14
910 #define PCS_V2_WINDOW_DEF_SIZE_INDEX 2
911 #define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4
913 /* SerDes integration register offsets */
914 #define SIR0_KR_RT_1 0x002c
915 #define SIR0_STATUS 0x0040
916 #define SIR1_SPEED 0x0000
918 /* SerDes integration register entry bit positions and sizes */
919 #define SIR0_KR_RT_1_RESET_INDEX 11
920 #define SIR0_KR_RT_1_RESET_WIDTH 1
921 #define SIR0_STATUS_RX_READY_INDEX 0
922 #define SIR0_STATUS_RX_READY_WIDTH 1
923 #define SIR0_STATUS_TX_READY_INDEX 8
924 #define SIR0_STATUS_TX_READY_WIDTH 1
925 #define SIR1_SPEED_CDR_RATE_INDEX 12
926 #define SIR1_SPEED_CDR_RATE_WIDTH 4
927 #define SIR1_SPEED_DATARATE_INDEX 4
928 #define SIR1_SPEED_DATARATE_WIDTH 2
929 #define SIR1_SPEED_PLLSEL_INDEX 3
930 #define SIR1_SPEED_PLLSEL_WIDTH 1
931 #define SIR1_SPEED_RATECHANGE_INDEX 6
932 #define SIR1_SPEED_RATECHANGE_WIDTH 1
933 #define SIR1_SPEED_TXAMP_INDEX 8
934 #define SIR1_SPEED_TXAMP_WIDTH 4
935 #define SIR1_SPEED_WORDMODE_INDEX 0
936 #define SIR1_SPEED_WORDMODE_WIDTH 3
938 /* SerDes RxTx register offsets */
939 #define RXTX_REG6 0x0018
940 #define RXTX_REG20 0x0050
941 #define RXTX_REG22 0x0058
942 #define RXTX_REG114 0x01c8
943 #define RXTX_REG129 0x0204
945 /* SerDes RxTx register entry bit positions and sizes */
946 #define RXTX_REG6_RESETB_RXD_INDEX 8
947 #define RXTX_REG6_RESETB_RXD_WIDTH 1
948 #define RXTX_REG20_BLWC_ENA_INDEX 2
949 #define RXTX_REG20_BLWC_ENA_WIDTH 1
950 #define RXTX_REG114_PQ_REG_INDEX 9
951 #define RXTX_REG114_PQ_REG_WIDTH 7
952 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14
953 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2
955 /* MAC Control register offsets */
956 #define XP_PROP_0 0x0000
957 #define XP_PROP_1 0x0004
958 #define XP_PROP_2 0x0008
959 #define XP_PROP_3 0x000c
960 #define XP_PROP_4 0x0010
961 #define XP_PROP_5 0x0014
962 #define XP_MAC_ADDR_LO 0x0020
963 #define XP_MAC_ADDR_HI 0x0024
964 #define XP_ECC_ISR 0x0030
965 #define XP_ECC_IER 0x0034
966 #define XP_ECC_CNT0 0x003c
967 #define XP_ECC_CNT1 0x0040
968 #define XP_DRIVER_INT_REQ 0x0060
969 #define XP_DRIVER_INT_RO 0x0064
970 #define XP_DRIVER_SCRATCH_0 0x0068
971 #define XP_DRIVER_SCRATCH_1 0x006c
972 #define XP_INT_EN 0x0078
973 #define XP_I2C_MUTEX 0x0080
974 #define XP_MDIO_MUTEX 0x0084
976 /* MAC Control register entry bit positions and sizes */
977 #define XP_DRIVER_INT_REQ_REQUEST_INDEX 0
978 #define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1
979 #define XP_DRIVER_INT_RO_STATUS_INDEX 0
980 #define XP_DRIVER_INT_RO_STATUS_WIDTH 1
981 #define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0
982 #define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8
983 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8
984 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8
985 #define XP_ECC_CNT0_RX_DED_INDEX 24
986 #define XP_ECC_CNT0_RX_DED_WIDTH 8
987 #define XP_ECC_CNT0_RX_SEC_INDEX 16
988 #define XP_ECC_CNT0_RX_SEC_WIDTH 8
989 #define XP_ECC_CNT0_TX_DED_INDEX 8
990 #define XP_ECC_CNT0_TX_DED_WIDTH 8
991 #define XP_ECC_CNT0_TX_SEC_INDEX 0
992 #define XP_ECC_CNT0_TX_SEC_WIDTH 8
993 #define XP_ECC_CNT1_DESC_DED_INDEX 8
994 #define XP_ECC_CNT1_DESC_DED_WIDTH 8
995 #define XP_ECC_CNT1_DESC_SEC_INDEX 0
996 #define XP_ECC_CNT1_DESC_SEC_WIDTH 8
997 #define XP_ECC_IER_DESC_DED_INDEX 0
998 #define XP_ECC_IER_DESC_DED_WIDTH 1
999 #define XP_ECC_IER_DESC_SEC_INDEX 1
1000 #define XP_ECC_IER_DESC_SEC_WIDTH 1
1001 #define XP_ECC_IER_RX_DED_INDEX 2
1002 #define XP_ECC_IER_RX_DED_WIDTH 1
1003 #define XP_ECC_IER_RX_SEC_INDEX 3
1004 #define XP_ECC_IER_RX_SEC_WIDTH 1
1005 #define XP_ECC_IER_TX_DED_INDEX 4
1006 #define XP_ECC_IER_TX_DED_WIDTH 1
1007 #define XP_ECC_IER_TX_SEC_INDEX 5
1008 #define XP_ECC_IER_TX_SEC_WIDTH 1
1009 #define XP_ECC_ISR_DESC_DED_INDEX 0
1010 #define XP_ECC_ISR_DESC_DED_WIDTH 1
1011 #define XP_ECC_ISR_DESC_SEC_INDEX 1
1012 #define XP_ECC_ISR_DESC_SEC_WIDTH 1
1013 #define XP_ECC_ISR_RX_DED_INDEX 2
1014 #define XP_ECC_ISR_RX_DED_WIDTH 1
1015 #define XP_ECC_ISR_RX_SEC_INDEX 3
1016 #define XP_ECC_ISR_RX_SEC_WIDTH 1
1017 #define XP_ECC_ISR_TX_DED_INDEX 4
1018 #define XP_ECC_ISR_TX_DED_WIDTH 1
1019 #define XP_ECC_ISR_TX_SEC_INDEX 5
1020 #define XP_ECC_ISR_TX_SEC_WIDTH 1
1021 #define XP_I2C_MUTEX_BUSY_INDEX 31
1022 #define XP_I2C_MUTEX_BUSY_WIDTH 1
1023 #define XP_I2C_MUTEX_ID_INDEX 29
1024 #define XP_I2C_MUTEX_ID_WIDTH 2
1025 #define XP_I2C_MUTEX_ACTIVE_INDEX 0
1026 #define XP_I2C_MUTEX_ACTIVE_WIDTH 1
1027 #define XP_MAC_ADDR_HI_VALID_INDEX 31
1028 #define XP_MAC_ADDR_HI_VALID_WIDTH 1
1029 #define XP_PROP_0_CONN_TYPE_INDEX 28
1030 #define XP_PROP_0_CONN_TYPE_WIDTH 3
1031 #define XP_PROP_0_MDIO_ADDR_INDEX 16
1032 #define XP_PROP_0_MDIO_ADDR_WIDTH 5
1033 #define XP_PROP_0_PORT_ID_INDEX 0
1034 #define XP_PROP_0_PORT_ID_WIDTH 8
1035 #define XP_PROP_0_PORT_MODE_INDEX 8
1036 #define XP_PROP_0_PORT_MODE_WIDTH 4
1037 #define XP_PROP_0_PORT_SPEEDS_INDEX 22
1038 #define XP_PROP_0_PORT_SPEEDS_WIDTH 5
1039 #define XP_PROP_1_MAX_RX_DMA_INDEX 24
1040 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5
1041 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8
1042 #define XP_PROP_1_MAX_RX_QUEUES_WIDTH 5
1043 #define XP_PROP_1_MAX_TX_DMA_INDEX 16
1044 #define XP_PROP_1_MAX_TX_DMA_WIDTH 5
1045 #define XP_PROP_1_MAX_TX_QUEUES_INDEX 0
1046 #define XP_PROP_1_MAX_TX_QUEUES_WIDTH 5
1047 #define XP_PROP_2_RX_FIFO_SIZE_INDEX 16
1048 #define XP_PROP_2_RX_FIFO_SIZE_WIDTH 16
1049 #define XP_PROP_2_TX_FIFO_SIZE_INDEX 0
1050 #define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16
1051 #define XP_PROP_3_GPIO_MASK_INDEX 28
1052 #define XP_PROP_3_GPIO_MASK_WIDTH 4
1053 #define XP_PROP_3_GPIO_MOD_ABS_INDEX 20
1054 #define XP_PROP_3_GPIO_MOD_ABS_WIDTH 4
1055 #define XP_PROP_3_GPIO_RATE_SELECT_INDEX 16
1056 #define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 4
1057 #define XP_PROP_3_GPIO_RX_LOS_INDEX 24
1058 #define XP_PROP_3_GPIO_RX_LOS_WIDTH 4
1059 #define XP_PROP_3_GPIO_TX_FAULT_INDEX 12
1060 #define XP_PROP_3_GPIO_TX_FAULT_WIDTH 4
1061 #define XP_PROP_3_GPIO_ADDR_INDEX 8
1062 #define XP_PROP_3_GPIO_ADDR_WIDTH 3
1063 #define XP_PROP_3_MDIO_RESET_INDEX 0
1064 #define XP_PROP_3_MDIO_RESET_WIDTH 2
1065 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 8
1066 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 3
1067 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 12
1068 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 4
1069 #define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 4
1070 #define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 2
1071 #define XP_PROP_4_MUX_ADDR_HI_INDEX 8
1072 #define XP_PROP_4_MUX_ADDR_HI_WIDTH 5
1073 #define XP_PROP_4_MUX_ADDR_LO_INDEX 0
1074 #define XP_PROP_4_MUX_ADDR_LO_WIDTH 3
1075 #define XP_PROP_4_MUX_CHAN_INDEX 4
1076 #define XP_PROP_4_MUX_CHAN_WIDTH 3
1077 #define XP_PROP_4_REDRV_ADDR_INDEX 16
1078 #define XP_PROP_4_REDRV_ADDR_WIDTH 7
1079 #define XP_PROP_4_REDRV_IF_INDEX 23
1080 #define XP_PROP_4_REDRV_IF_WIDTH 1
1081 #define XP_PROP_4_REDRV_LANE_INDEX 24
1082 #define XP_PROP_4_REDRV_LANE_WIDTH 3
1083 #define XP_PROP_4_REDRV_MODEL_INDEX 28
1084 #define XP_PROP_4_REDRV_MODEL_WIDTH 3
1085 #define XP_PROP_4_REDRV_PRESENT_INDEX 31
1086 #define XP_PROP_4_REDRV_PRESENT_WIDTH 1
1088 /* I2C Control register offsets */
1089 #define IC_CON 0x0000
1090 #define IC_TAR 0x0004
1091 #define IC_DATA_CMD 0x0010
1092 #define IC_INTR_STAT 0x002c
1093 #define IC_INTR_MASK 0x0030
1094 #define IC_RAW_INTR_STAT 0x0034
1095 #define IC_CLR_INTR 0x0040
1096 #define IC_CLR_TX_ABRT 0x0054
1097 #define IC_CLR_STOP_DET 0x0060
1098 #define IC_ENABLE 0x006c
1099 #define IC_TXFLR 0x0074
1100 #define IC_RXFLR 0x0078
1101 #define IC_TX_ABRT_SOURCE 0x0080
1102 #define IC_ENABLE_STATUS 0x009c
1103 #define IC_COMP_PARAM_1 0x00f4
1105 /* I2C Control register entry bit positions and sizes */
1106 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2
1107 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2
1108 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8
1109 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8
1110 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16
1111 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8
1112 #define IC_CON_MASTER_MODE_INDEX 0
1113 #define IC_CON_MASTER_MODE_WIDTH 1
1114 #define IC_CON_RESTART_EN_INDEX 5
1115 #define IC_CON_RESTART_EN_WIDTH 1
1116 #define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9
1117 #define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1
1118 #define IC_CON_SLAVE_DISABLE_INDEX 6
1119 #define IC_CON_SLAVE_DISABLE_WIDTH 1
1120 #define IC_CON_SPEED_INDEX 1
1121 #define IC_CON_SPEED_WIDTH 2
1122 #define IC_DATA_CMD_CMD_INDEX 8
1123 #define IC_DATA_CMD_CMD_WIDTH 1
1124 #define IC_DATA_CMD_STOP_INDEX 9
1125 #define IC_DATA_CMD_STOP_WIDTH 1
1126 #define IC_ENABLE_ABORT_INDEX 1
1127 #define IC_ENABLE_ABORT_WIDTH 1
1128 #define IC_ENABLE_EN_INDEX 0
1129 #define IC_ENABLE_EN_WIDTH 1
1130 #define IC_ENABLE_STATUS_EN_INDEX 0
1131 #define IC_ENABLE_STATUS_EN_WIDTH 1
1132 #define IC_INTR_MASK_TX_EMPTY_INDEX 4
1133 #define IC_INTR_MASK_TX_EMPTY_WIDTH 1
1134 #define IC_RAW_INTR_STAT_RX_FULL_INDEX 2
1135 #define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1
1136 #define IC_RAW_INTR_STAT_STOP_DET_INDEX 9
1137 #define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1
1138 #define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6
1139 #define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1
1140 #define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4
1141 #define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
1143 /* I2C Control register value */
1144 #define IC_TX_ABRT_7B_ADDR_NOACK 0x0001
1145 #define IC_TX_ABRT_ARB_LOST 0x1000
1147 /* Descriptor/Packet entry bit positions and sizes */
1148 #define RX_PACKET_ERRORS_CRC_INDEX 2
1149 #define RX_PACKET_ERRORS_CRC_WIDTH 1
1150 #define RX_PACKET_ERRORS_FRAME_INDEX 3
1151 #define RX_PACKET_ERRORS_FRAME_WIDTH 1
1152 #define RX_PACKET_ERRORS_LENGTH_INDEX 0
1153 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1
1154 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1
1155 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1
1157 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0
1158 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1
1159 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1
1160 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1161 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2
1162 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1
1163 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3
1164 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1
1165 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4
1166 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1
1167 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5
1168 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1
1169 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6
1170 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1
1172 #define RX_NORMAL_DESC0_OVT_INDEX 0
1173 #define RX_NORMAL_DESC0_OVT_WIDTH 16
1174 #define RX_NORMAL_DESC2_HL_INDEX 0
1175 #define RX_NORMAL_DESC2_HL_WIDTH 10
1176 #define RX_NORMAL_DESC3_CDA_INDEX 27
1177 #define RX_NORMAL_DESC3_CDA_WIDTH 1
1178 #define RX_NORMAL_DESC3_CTXT_INDEX 30
1179 #define RX_NORMAL_DESC3_CTXT_WIDTH 1
1180 #define RX_NORMAL_DESC3_ES_INDEX 15
1181 #define RX_NORMAL_DESC3_ES_WIDTH 1
1182 #define RX_NORMAL_DESC3_ETLT_INDEX 16
1183 #define RX_NORMAL_DESC3_ETLT_WIDTH 4
1184 #define RX_NORMAL_DESC3_FD_INDEX 29
1185 #define RX_NORMAL_DESC3_FD_WIDTH 1
1186 #define RX_NORMAL_DESC3_INTE_INDEX 30
1187 #define RX_NORMAL_DESC3_INTE_WIDTH 1
1188 #define RX_NORMAL_DESC3_L34T_INDEX 20
1189 #define RX_NORMAL_DESC3_L34T_WIDTH 4
1190 #define RX_NORMAL_DESC3_LD_INDEX 28
1191 #define RX_NORMAL_DESC3_LD_WIDTH 1
1192 #define RX_NORMAL_DESC3_OWN_INDEX 31
1193 #define RX_NORMAL_DESC3_OWN_WIDTH 1
1194 #define RX_NORMAL_DESC3_PL_INDEX 0
1195 #define RX_NORMAL_DESC3_PL_WIDTH 14
1196 #define RX_NORMAL_DESC3_RSV_INDEX 26
1197 #define RX_NORMAL_DESC3_RSV_WIDTH 1
1198 #define RX_NORMAL_DESC3_LD_INDEX 28
1199 #define RX_NORMAL_DESC3_LD_WIDTH 1
1201 #define RX_DESC3_L34T_IPV4_TCP 1
1202 #define RX_DESC3_L34T_IPV4_UDP 2
1203 #define RX_DESC3_L34T_IPV4_ICMP 3
1204 #define RX_DESC3_L34T_IPV6_TCP 9
1205 #define RX_DESC3_L34T_IPV6_UDP 10
1206 #define RX_DESC3_L34T_IPV6_ICMP 11
1208 #define RX_CONTEXT_DESC3_TSA_INDEX 4
1209 #define RX_CONTEXT_DESC3_TSA_WIDTH 1
1210 #define RX_CONTEXT_DESC3_TSD_INDEX 6
1211 #define RX_CONTEXT_DESC3_TSD_WIDTH 1
1212 #define RX_CONTEXT_DESC3_PMT_INDEX 0
1213 #define RX_CONTEXT_DESC3_PMT_WIDTH 4
1215 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
1216 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1
1217 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1
1218 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1
1219 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2
1220 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1221 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3
1222 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1
1224 #define TX_CONTEXT_DESC2_MSS_INDEX 0
1225 #define TX_CONTEXT_DESC2_MSS_WIDTH 15
1226 #define TX_CONTEXT_DESC3_CTXT_INDEX 30
1227 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1
1228 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26
1229 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1
1230 #define TX_CONTEXT_DESC3_VLTV_INDEX 16
1231 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1
1232 #define TX_CONTEXT_DESC3_VT_INDEX 0
1233 #define TX_CONTEXT_DESC3_VT_WIDTH 16
1235 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0
1236 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14
1237 #define TX_NORMAL_DESC2_IC_INDEX 31
1238 #define TX_NORMAL_DESC2_IC_WIDTH 1
1239 #define TX_NORMAL_DESC2_TTSE_INDEX 30
1240 #define TX_NORMAL_DESC2_TTSE_WIDTH 1
1241 #define TX_NORMAL_DESC2_VTIR_INDEX 14
1242 #define TX_NORMAL_DESC2_VTIR_WIDTH 2
1243 #define TX_NORMAL_DESC3_CIC_INDEX 16
1244 #define TX_NORMAL_DESC3_CIC_WIDTH 2
1245 #define TX_NORMAL_DESC3_CPC_INDEX 26
1246 #define TX_NORMAL_DESC3_CPC_WIDTH 2
1247 #define TX_NORMAL_DESC3_CTXT_INDEX 30
1248 #define TX_NORMAL_DESC3_CTXT_WIDTH 1
1249 #define TX_NORMAL_DESC3_FD_INDEX 29
1250 #define TX_NORMAL_DESC3_FD_WIDTH 1
1251 #define TX_NORMAL_DESC3_FL_INDEX 0
1252 #define TX_NORMAL_DESC3_FL_WIDTH 15
1253 #define TX_NORMAL_DESC3_LD_INDEX 28
1254 #define TX_NORMAL_DESC3_LD_WIDTH 1
1255 #define TX_NORMAL_DESC3_OWN_INDEX 31
1256 #define TX_NORMAL_DESC3_OWN_WIDTH 1
1257 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19
1258 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4
1259 #define TX_NORMAL_DESC3_TCPPL_INDEX 0
1260 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18
1261 #define TX_NORMAL_DESC3_TSE_INDEX 18
1262 #define TX_NORMAL_DESC3_TSE_WIDTH 1
1264 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2
1266 /* MDIO undefined or vendor specific registers */
1267 #ifndef MDIO_PMA_10GBR_PMD_CTRL
1268 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
1271 #ifndef MDIO_PMA_10GBR_FECCTRL
1272 #define MDIO_PMA_10GBR_FECCTRL 0x00ab
1275 #ifndef MDIO_PMA_RX_CTRL1
1276 #define MDIO_PMA_RX_CTRL1 0x8051
1279 #ifndef MDIO_PCS_DIG_CTRL
1280 #define MDIO_PCS_DIG_CTRL 0x8000
1283 #ifndef MDIO_PCS_DIGITAL_STAT
1284 #define MDIO_PCS_DIGITAL_STAT 0x8010
1288 #define MDIO_AN_XNP 0x0016
1292 #define MDIO_AN_LPX 0x0019
1295 #ifndef MDIO_AN_COMP_STAT
1296 #define MDIO_AN_COMP_STAT 0x0030
1299 #ifndef MDIO_AN_INTMASK
1300 #define MDIO_AN_INTMASK 0x8001
1304 #define MDIO_AN_INT 0x8002
1307 #ifndef MDIO_VEND2_AN_ADVERTISE
1308 #define MDIO_VEND2_AN_ADVERTISE 0x0004
1311 #ifndef MDIO_VEND2_AN_LP_ABILITY
1312 #define MDIO_VEND2_AN_LP_ABILITY 0x0005
1315 #ifndef MDIO_VEND2_AN_CTRL
1316 #define MDIO_VEND2_AN_CTRL 0x8001
1319 #ifndef MDIO_VEND2_AN_STAT
1320 #define MDIO_VEND2_AN_STAT 0x8002
1323 #ifndef MDIO_VEND2_PMA_CDR_CONTROL
1324 #define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
1327 #ifndef MDIO_VEND2_PMA_MISC_CTRL0
1328 #define MDIO_VEND2_PMA_MISC_CTRL0 0x8090
1332 #ifndef MDIO_CTRL1_SPEED1G
1333 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
1336 #ifndef MDIO_VEND2_CTRL1_AN_ENABLE
1337 #define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12)
1340 #ifndef MDIO_VEND2_CTRL1_AN_RESTART
1341 #define MDIO_VEND2_CTRL1_AN_RESTART BIT(9)
1344 #ifndef MDIO_VEND2_CTRL1_SS6
1345 #define MDIO_VEND2_CTRL1_SS6 BIT(6)
1348 #ifndef MDIO_VEND2_CTRL1_SS13
1349 #define MDIO_VEND2_CTRL1_SS13 BIT(13)
1352 /* MDIO mask values */
1353 #define AXGBE_AN_CL73_INT_CMPLT BIT(0)
1354 #define AXGBE_AN_CL73_INC_LINK BIT(1)
1355 #define AXGBE_AN_CL73_PG_RCV BIT(2)
1356 #define AXGBE_AN_CL73_INT_MASK 0x07
1358 #define AXGBE_XNP_MCF_NULL_MESSAGE 0x001
1359 #define AXGBE_XNP_ACK_PROCESSED BIT(12)
1360 #define AXGBE_XNP_MP_FORMATTED BIT(13)
1361 #define AXGBE_XNP_NP_EXCHANGE BIT(15)
1363 #define AXGBE_KR_TRAINING_START BIT(0)
1364 #define AXGBE_KR_TRAINING_ENABLE BIT(1)
1366 #define AXGBE_PCS_CL37_BP BIT(12)
1367 #define XGBE_PCS_PSEQ_STATE_MASK 0x1c
1368 #define XGBE_PCS_PSEQ_STATE_POWER_GOOD 0x10
1370 #define AXGBE_AN_CL37_INT_CMPLT BIT(0)
1371 #define AXGBE_AN_CL37_INT_MASK 0x01
1373 #define AXGBE_AN_CL37_HD_MASK 0x40
1374 #define AXGBE_AN_CL37_FD_MASK 0x20
1376 #define AXGBE_AN_CL37_PCS_MODE_MASK 0x06
1377 #define AXGBE_AN_CL37_PCS_MODE_BASEX 0x00
1378 #define AXGBE_AN_CL37_PCS_MODE_SGMII 0x04
1379 #define AXGBE_AN_CL37_TX_CONFIG_MASK 0x08
1380 #define AXGBE_AN_CL37_MII_CTRL_8BIT 0x0100
1382 #define AXGBE_PMA_CDR_TRACK_EN_MASK 0x01
1383 #define AXGBE_PMA_CDR_TRACK_EN_OFF 0x00
1384 #define AXGBE_PMA_CDR_TRACK_EN_ON 0x01
1389 #define rmb() rte_rmb() /* dpdk rte provided rmb */
1390 #define wmb() rte_wmb() /* dpdk rte provided wmb */
1396 typedef unsigned char u8;
1397 typedef unsigned short u16;
1398 typedef unsigned int u32;
1399 typedef unsigned long long u64;
1400 typedef unsigned long long dma_addr_t;
1402 static inline uint32_t low32_value(uint64_t addr)
1404 return (addr) & 0x0ffffffff;
1407 static inline uint32_t high32_value(uint64_t addr)
1409 return (addr >> 32) & 0x0ffffffff;
1412 #define XGBE_PMA_PLL_CTRL_MASK BIT(15)
1413 #define XGBE_PMA_PLL_CTRL_SET BIT(15)
1414 #define XGBE_PMA_PLL_CTRL_CLEAR 0x0000
1416 #define XGBE_PMA_RX_RST_0_MASK BIT(4)
1417 #define XGBE_PMA_RX_RST_0_RESET_ON 0x10
1418 #define XGBE_PMA_RX_RST_0_RESET_OFF 0x00
1422 /* Bit setting and getting macros
1423 * The get macro will extract the current bit field value from within
1426 * The set macro will clear the current bit field value within the
1427 * variable and then set the bit field of the variable to the
1430 #define GET_BITS(_var, _index, _width) \
1431 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1433 #define SET_BITS(_var, _index, _width, _val) \
1435 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1436 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1439 #define GET_BITS_LE(_var, _index, _width) \
1440 ((rte_le_to_cpu_32((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1442 #define SET_BITS_LE(_var, _index, _width, _val) \
1444 (_var) &= rte_cpu_to_le_32(~(((0x1U << (_width)) - 1) << (_index)));\
1445 (_var) |= rte_cpu_to_le_32((((_val) & \
1446 ((0x1U << (_width)) - 1)) << (_index))); \
1449 /* Bit setting and getting macros based on register fields
1450 * The get macro uses the bit field definitions formed using the input
1451 * names to extract the current bit field value from within the
1454 * The set macro uses the bit field definitions formed using the input
1455 * names to set the bit field of the variable to the specified value
1457 #define AXGMAC_GET_BITS(_var, _prefix, _field) \
1459 _prefix##_##_field##_INDEX, \
1460 _prefix##_##_field##_WIDTH)
1462 #define AXGMAC_SET_BITS(_var, _prefix, _field, _val) \
1464 _prefix##_##_field##_INDEX, \
1465 _prefix##_##_field##_WIDTH, (_val))
1467 #define AXGMAC_GET_BITS_LE(_var, _prefix, _field) \
1468 GET_BITS_LE((_var), \
1469 _prefix##_##_field##_INDEX, \
1470 _prefix##_##_field##_WIDTH)
1472 #define AXGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \
1473 SET_BITS_LE((_var), \
1474 _prefix##_##_field##_INDEX, \
1475 _prefix##_##_field##_WIDTH, (_val))
1477 /* Macros for reading or writing registers
1478 * The ioread macros will get bit fields or full values using the
1479 * register definitions formed using the input names
1481 * The iowrite macros will set bit fields or full values using the
1482 * register definitions formed using the input names
1484 #define AXGMAC_IOREAD(_pdata, _reg) \
1485 rte_read32((uint8_t *)((_pdata)->xgmac_regs) + (_reg))
1487 #define AXGMAC_IOREAD_BITS(_pdata, _reg, _field) \
1488 GET_BITS(AXGMAC_IOREAD((_pdata), _reg), \
1489 _reg##_##_field##_INDEX, \
1490 _reg##_##_field##_WIDTH)
1492 #define AXGMAC_IOWRITE(_pdata, _reg, _val) \
1493 rte_write32((_val), \
1494 (uint8_t *)((_pdata)->xgmac_regs) + (_reg))
1496 #define AXGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1498 u32 reg_val = AXGMAC_IOREAD((_pdata), _reg); \
1500 _reg##_##_field##_INDEX, \
1501 _reg##_##_field##_WIDTH, (_val)); \
1502 AXGMAC_IOWRITE((_pdata), _reg, reg_val); \
1505 /* Macros for reading or writing MTL queue or traffic class registers
1506 * Similar to the standard read and write macros except that the
1507 * base register value is calculated by the queue or traffic class number
1509 #define AXGMAC_MTL_IOREAD(_pdata, _n, _reg) \
1510 rte_read32((uint8_t *)((_pdata)->xgmac_regs) + \
1511 MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))
1513 #define AXGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
1514 GET_BITS(AXGMAC_MTL_IOREAD((_pdata), (_n), (_reg)), \
1515 _reg##_##_field##_INDEX, \
1516 _reg##_##_field##_WIDTH)
1518 #define AXGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
1519 rte_write32((_val), (uint8_t *)((_pdata)->xgmac_regs) +\
1520 MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))
1522 #define AXGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
1524 u32 reg_val = AXGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
1526 _reg##_##_field##_INDEX, \
1527 _reg##_##_field##_WIDTH, (_val)); \
1528 AXGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
1531 /* Macros for reading or writing DMA channel registers
1532 * Similar to the standard read and write macros except that the
1533 * base register value is obtained from the ring
1535 #define AXGMAC_DMA_IOREAD(_channel, _reg) \
1536 rte_read32((uint8_t *)((_channel)->dma_regs) + (_reg))
1538 #define AXGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
1539 GET_BITS(AXGMAC_DMA_IOREAD((_channel), _reg), \
1540 _reg##_##_field##_INDEX, \
1541 _reg##_##_field##_WIDTH)
1543 #define AXGMAC_DMA_IOWRITE(_channel, _reg, _val) \
1544 rte_write32((_val), \
1545 (uint8_t *)((_channel)->dma_regs) + (_reg))
1547 #define AXGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
1549 u32 reg_val = AXGMAC_DMA_IOREAD((_channel), _reg); \
1551 _reg##_##_field##_INDEX, \
1552 _reg##_##_field##_WIDTH, (_val)); \
1553 AXGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
1556 /* Macros for building, reading or writing register values or bits
1557 * within the register values of XPCS registers.
1559 #define XPCS_GET_BITS(_var, _prefix, _field) \
1561 _prefix##_##_field##_INDEX, \
1562 _prefix##_##_field##_WIDTH)
1564 #define XPCS_SET_BITS(_var, _prefix, _field, _val) \
1566 _prefix##_##_field##_INDEX, \
1567 _prefix##_##_field##_WIDTH, (_val))
1569 #define XPCS32_IOWRITE(_pdata, _off, _val) \
1571 (uint8_t *)((_pdata)->xpcs_regs) + (_off))
1573 #define XPCS32_IOREAD(_pdata, _off) \
1574 rte_read32((uint8_t *)((_pdata)->xpcs_regs) + (_off))
1576 #define XPCS16_IOWRITE(_pdata, _off, _val) \
1578 (uint8_t *)((_pdata)->xpcs_regs) + (_off))
1580 #define XPCS16_IOREAD(_pdata, _off) \
1581 rte_read16((uint8_t *)((_pdata)->xpcs_regs) + (_off))
1583 /* Macros for building, reading or writing register values or bits
1584 * within the register values of SerDes integration registers.
1586 #define XSIR_GET_BITS(_var, _prefix, _field) \
1588 _prefix##_##_field##_INDEX, \
1589 _prefix##_##_field##_WIDTH)
1591 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \
1593 _prefix##_##_field##_INDEX, \
1594 _prefix##_##_field##_WIDTH, (_val))
1596 #define XSIR0_IOREAD(_pdata, _reg) \
1597 rte_read16((uint8_t *)((_pdata)->sir0_regs) + (_reg))
1599 #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \
1600 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \
1601 _reg##_##_field##_INDEX, \
1602 _reg##_##_field##_WIDTH)
1604 #define XSIR0_IOWRITE(_pdata, _reg, _val) \
1605 rte_write16((_val), \
1606 (uint8_t *)((_pdata)->sir0_regs) + (_reg))
1608 #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1610 u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \
1612 _reg##_##_field##_INDEX, \
1613 _reg##_##_field##_WIDTH, (_val)); \
1614 XSIR0_IOWRITE((_pdata), _reg, reg_val); \
1617 #define XSIR1_IOREAD(_pdata, _reg) \
1618 rte_read16((uint8_t *)((_pdata)->sir1_regs) + _reg)
1620 #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \
1621 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \
1622 _reg##_##_field##_INDEX, \
1623 _reg##_##_field##_WIDTH)
1625 #define XSIR1_IOWRITE(_pdata, _reg, _val) \
1626 rte_write16((_val), \
1627 (uint8_t *)((_pdata)->sir1_regs) + (_reg))
1629 #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1631 u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \
1633 _reg##_##_field##_INDEX, \
1634 _reg##_##_field##_WIDTH, (_val)); \
1635 XSIR1_IOWRITE((_pdata), _reg, reg_val); \
1638 /* Macros for building, reading or writing register values or bits
1639 * within the register values of SerDes RxTx registers.
1641 #define XRXTX_IOREAD(_pdata, _reg) \
1642 rte_read16((uint8_t *)((_pdata)->rxtx_regs) + (_reg))
1644 #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \
1645 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \
1646 _reg##_##_field##_INDEX, \
1647 _reg##_##_field##_WIDTH)
1649 #define XRXTX_IOWRITE(_pdata, _reg, _val) \
1650 rte_write16((_val), \
1651 (uint8_t *)((_pdata)->rxtx_regs) + (_reg))
1653 #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1655 u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \
1657 _reg##_##_field##_INDEX, \
1658 _reg##_##_field##_WIDTH, (_val)); \
1659 XRXTX_IOWRITE((_pdata), _reg, reg_val); \
1662 /* Macros for building, reading or writing register values or bits
1663 * within the register values of MAC Control registers.
1665 #define XP_GET_BITS(_var, _prefix, _field) \
1667 _prefix##_##_field##_INDEX, \
1668 _prefix##_##_field##_WIDTH)
1670 #define XP_SET_BITS(_var, _prefix, _field, _val) \
1672 _prefix##_##_field##_INDEX, \
1673 _prefix##_##_field##_WIDTH, (_val))
1675 #define XP_IOREAD(_pdata, _reg) \
1676 rte_read32((uint8_t *)((_pdata)->xprop_regs) + (_reg))
1678 #define XP_IOREAD_BITS(_pdata, _reg, _field) \
1679 GET_BITS(XP_IOREAD((_pdata), (_reg)), \
1680 _reg##_##_field##_INDEX, \
1681 _reg##_##_field##_WIDTH)
1683 #define XP_IOWRITE(_pdata, _reg, _val) \
1684 rte_write32((_val), \
1685 (uint8_t *)((_pdata)->xprop_regs) + (_reg))
1687 #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1689 u32 reg_val = XP_IOREAD((_pdata), (_reg)); \
1691 _reg##_##_field##_INDEX, \
1692 _reg##_##_field##_WIDTH, (_val)); \
1693 XP_IOWRITE((_pdata), (_reg), reg_val); \
1696 /* Macros for building, reading or writing register values or bits
1697 * within the register values of I2C Control registers.
1699 #define XI2C_GET_BITS(_var, _prefix, _field) \
1701 _prefix##_##_field##_INDEX, \
1702 _prefix##_##_field##_WIDTH)
1704 #define XI2C_SET_BITS(_var, _prefix, _field, _val) \
1706 _prefix##_##_field##_INDEX, \
1707 _prefix##_##_field##_WIDTH, (_val))
1709 #define XI2C_IOREAD(_pdata, _reg) \
1710 rte_read32((uint8_t *)((_pdata)->xi2c_regs) + (_reg))
1712 #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \
1713 GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \
1714 _reg##_##_field##_INDEX, \
1715 _reg##_##_field##_WIDTH)
1717 #define XI2C_IOWRITE(_pdata, _reg, _val) \
1718 rte_write32((_val), \
1719 (uint8_t *)((_pdata)->xi2c_regs) + (_reg))
1721 #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1723 u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \
1725 _reg##_##_field##_INDEX, \
1726 _reg##_##_field##_WIDTH, (_val)); \
1727 XI2C_IOWRITE((_pdata), (_reg), reg_val); \
1730 /* Macros for building, reading or writing register values or bits
1731 * using MDIO. Different from above because of the use of standardized
1732 * Linux include values. No shifting is performed with the bit
1733 * operations, everything works on mask values.
1735 #define XMDIO_READ(_pdata, _mmd, _reg) \
1736 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
1737 MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))
1739 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \
1740 (XMDIO_READ((_pdata), _mmd, _reg) & _mask)
1742 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \
1743 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \
1744 MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))
1746 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \
1748 u32 mmd_val = XMDIO_READ((_pdata), (_mmd), (_reg)); \
1749 mmd_val &= ~(_mask); \
1750 mmd_val |= (_val); \
1751 XMDIO_WRITE((_pdata), (_mmd), (_reg), (mmd_val)); \
1755 * time_after(a,b) returns true if the time a is after time b.
1757 * Do this with "<0" and ">=0" to only test the sign of the result. A
1758 * good compiler would generate better code (and a really good compiler
1759 * wouldn't care). Gcc is currently neither.
1761 #define time_after(a, b) ((long)((b) - (a)) < 0)
1762 #define time_before(a, b) time_after(b, a)
1764 #define time_after_eq(a, b) ((long)((a) - (b)) >= 0)
1765 #define time_before_eq(a, b) time_after_eq(b, a)
1767 static inline unsigned long msecs_to_timer_cycles(unsigned int m)
1769 return rte_get_timer_hz() * (m / 1000);
1772 #endif /* __AXGBE_COMMON_H__ */