1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #ifndef __AXGBE_COMMON_H__
7 #define __AXGBE_COMMON_H__
9 #include "axgbe_logs.h"
13 #include <sys/queue.h>
24 #include <rte_bitops.h>
25 #include <rte_byteorder.h>
26 #include <rte_memory.h>
27 #include <rte_malloc.h>
28 #include <rte_hexdump.h>
30 #include <rte_debug.h>
31 #include <rte_branch_prediction.h>
33 #include <rte_memzone.h>
34 #include <rte_ether.h>
35 #include <rte_ethdev.h>
37 #include <rte_errno.h>
38 #include <rte_ethdev_pci.h>
39 #include <rte_common.h>
40 #include <rte_cycles.h>
43 #define BIT(nr) (1 << (nr))
45 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
50 /* DMA register offsets */
52 #define DMA_SBMR 0x3004
53 #define DMA_ISR 0x3008
54 #define DMA_AXIARCR 0x3010
55 #define DMA_AXIAWCR 0x3018
56 #define DMA_AXIAWRCR 0x301c
57 #define DMA_DSR0 0x3020
58 #define DMA_DSR1 0x3024
59 #define EDMA_TX_CONTROL 0x3040
60 #define EDMA_RX_CONTROL 0x3044
62 /* DMA register entry bit positions and sizes */
63 #define DMA_AXIARCR_DRC_INDEX 0
64 #define DMA_AXIARCR_DRC_WIDTH 4
65 #define DMA_AXIARCR_DRD_INDEX 4
66 #define DMA_AXIARCR_DRD_WIDTH 2
67 #define DMA_AXIARCR_TEC_INDEX 8
68 #define DMA_AXIARCR_TEC_WIDTH 4
69 #define DMA_AXIARCR_TED_INDEX 12
70 #define DMA_AXIARCR_TED_WIDTH 2
71 #define DMA_AXIARCR_THC_INDEX 16
72 #define DMA_AXIARCR_THC_WIDTH 4
73 #define DMA_AXIARCR_THD_INDEX 20
74 #define DMA_AXIARCR_THD_WIDTH 2
75 #define DMA_AXIAWCR_DWC_INDEX 0
76 #define DMA_AXIAWCR_DWC_WIDTH 4
77 #define DMA_AXIAWCR_DWD_INDEX 4
78 #define DMA_AXIAWCR_DWD_WIDTH 2
79 #define DMA_AXIAWCR_RPC_INDEX 8
80 #define DMA_AXIAWCR_RPC_WIDTH 4
81 #define DMA_AXIAWCR_RPD_INDEX 12
82 #define DMA_AXIAWCR_RPD_WIDTH 2
83 #define DMA_AXIAWCR_RHC_INDEX 16
84 #define DMA_AXIAWCR_RHC_WIDTH 4
85 #define DMA_AXIAWCR_RHD_INDEX 20
86 #define DMA_AXIAWCR_RHD_WIDTH 2
87 #define DMA_AXIAWCR_RDC_INDEX 24
88 #define DMA_AXIAWCR_RDC_WIDTH 4
89 #define DMA_AXIAWCR_RDD_INDEX 28
90 #define DMA_AXIAWCR_RDD_WIDTH 2
91 #define DMA_AXIAWRCR_TDWC_INDEX 0
92 #define DMA_AXIAWRCR_TDWC_WIDTH 4
93 #define DMA_AXIAWRCR_TDWD_INDEX 4
94 #define DMA_AXIAWRCR_TDWD_WIDTH 4
95 #define DMA_AXIAWRCR_RDRC_INDEX 8
96 #define DMA_AXIAWRCR_RDRC_WIDTH 4
97 #define DMA_ISR_MACIS_INDEX 17
98 #define DMA_ISR_MACIS_WIDTH 1
99 #define DMA_ISR_MTLIS_INDEX 16
100 #define DMA_ISR_MTLIS_WIDTH 1
101 #define DMA_MR_INTM_INDEX 12
102 #define DMA_MR_INTM_WIDTH 2
103 #define DMA_MR_SWR_INDEX 0
104 #define DMA_MR_SWR_WIDTH 1
105 #define DMA_SBMR_WR_OSR_INDEX 24
106 #define DMA_SBMR_WR_OSR_WIDTH 6
107 #define DMA_SBMR_RD_OSR_INDEX 16
108 #define DMA_SBMR_RD_OSR_WIDTH 6
109 #define DMA_SBMR_AAL_INDEX 12
110 #define DMA_SBMR_AAL_WIDTH 1
111 #define DMA_SBMR_EAME_INDEX 11
112 #define DMA_SBMR_EAME_WIDTH 1
113 #define DMA_SBMR_BLEN_256_INDEX 7
114 #define DMA_SBMR_BLEN_256_WIDTH 1
115 #define DMA_SBMR_BLEN_32_INDEX 4
116 #define DMA_SBMR_BLEN_32_WIDTH 1
117 #define DMA_SBMR_UNDEF_INDEX 0
118 #define DMA_SBMR_UNDEF_WIDTH 1
120 /* DMA register values */
121 #define DMA_DSR_RPS_WIDTH 4
122 #define DMA_DSR_TPS_WIDTH 4
123 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
124 #define DMA_DSR0_RPS_START 8
125 #define DMA_DSR0_TPS_START 12
126 #define DMA_DSRX_FIRST_QUEUE 3
127 #define DMA_DSRX_INC 4
128 #define DMA_DSRX_QPR 4
129 #define DMA_DSRX_RPS_START 0
130 #define DMA_DSRX_TPS_START 4
131 #define DMA_TPS_STOPPED 0x00
132 #define DMA_TPS_SUSPENDED 0x06
134 /* DMA channel register offsets
135 * Multiple channels can be active. The first channel has registers
136 * that begin at 0x3100. Each subsequent channel has registers that
137 * are accessed using an offset of 0x80 from the previous channel.
139 #define DMA_CH_BASE 0x3100
140 #define DMA_CH_INC 0x80
142 #define DMA_CH_CR 0x00
143 #define DMA_CH_TCR 0x04
144 #define DMA_CH_RCR 0x08
145 #define DMA_CH_TDLR_HI 0x10
146 #define DMA_CH_TDLR_LO 0x14
147 #define DMA_CH_RDLR_HI 0x18
148 #define DMA_CH_RDLR_LO 0x1c
149 #define DMA_CH_TDTR_LO 0x24
150 #define DMA_CH_RDTR_LO 0x2c
151 #define DMA_CH_TDRLR 0x30
152 #define DMA_CH_RDRLR 0x34
153 #define DMA_CH_IER 0x38
154 #define DMA_CH_RIWT 0x3c
155 #define DMA_CH_CATDR_LO 0x44
156 #define DMA_CH_CARDR_LO 0x4c
157 #define DMA_CH_CATBR_HI 0x50
158 #define DMA_CH_CATBR_LO 0x54
159 #define DMA_CH_CARBR_HI 0x58
160 #define DMA_CH_CARBR_LO 0x5c
161 #define DMA_CH_SR 0x60
163 /* DMA channel register entry bit positions and sizes */
164 #define DMA_CH_CR_PBLX8_INDEX 16
165 #define DMA_CH_CR_PBLX8_WIDTH 1
166 #define DMA_CH_CR_SPH_INDEX 24
167 #define DMA_CH_CR_SPH_WIDTH 1
168 #define DMA_CH_IER_AIE_INDEX 14
169 #define DMA_CH_IER_AIE_WIDTH 1
170 #define DMA_CH_IER_FBEE_INDEX 12
171 #define DMA_CH_IER_FBEE_WIDTH 1
172 #define DMA_CH_IER_NIE_INDEX 15
173 #define DMA_CH_IER_NIE_WIDTH 1
174 #define DMA_CH_IER_RBUE_INDEX 7
175 #define DMA_CH_IER_RBUE_WIDTH 1
176 #define DMA_CH_IER_RIE_INDEX 6
177 #define DMA_CH_IER_RIE_WIDTH 1
178 #define DMA_CH_IER_RSE_INDEX 8
179 #define DMA_CH_IER_RSE_WIDTH 1
180 #define DMA_CH_IER_TBUE_INDEX 2
181 #define DMA_CH_IER_TBUE_WIDTH 1
182 #define DMA_CH_IER_TIE_INDEX 0
183 #define DMA_CH_IER_TIE_WIDTH 1
184 #define DMA_CH_IER_TXSE_INDEX 1
185 #define DMA_CH_IER_TXSE_WIDTH 1
186 #define DMA_CH_RCR_PBL_INDEX 16
187 #define DMA_CH_RCR_PBL_WIDTH 6
188 #define DMA_CH_RCR_RBSZ_INDEX 1
189 #define DMA_CH_RCR_RBSZ_WIDTH 14
190 #define DMA_CH_RCR_SR_INDEX 0
191 #define DMA_CH_RCR_SR_WIDTH 1
192 #define DMA_CH_RIWT_RWT_INDEX 0
193 #define DMA_CH_RIWT_RWT_WIDTH 8
194 #define DMA_CH_SR_FBE_INDEX 12
195 #define DMA_CH_SR_FBE_WIDTH 1
196 #define DMA_CH_SR_RBU_INDEX 7
197 #define DMA_CH_SR_RBU_WIDTH 1
198 #define DMA_CH_SR_RI_INDEX 6
199 #define DMA_CH_SR_RI_WIDTH 1
200 #define DMA_CH_SR_RPS_INDEX 8
201 #define DMA_CH_SR_RPS_WIDTH 1
202 #define DMA_CH_SR_TBU_INDEX 2
203 #define DMA_CH_SR_TBU_WIDTH 1
204 #define DMA_CH_SR_TI_INDEX 0
205 #define DMA_CH_SR_TI_WIDTH 1
206 #define DMA_CH_SR_TPS_INDEX 1
207 #define DMA_CH_SR_TPS_WIDTH 1
208 #define DMA_CH_TCR_OSP_INDEX 4
209 #define DMA_CH_TCR_OSP_WIDTH 1
210 #define DMA_CH_TCR_PBL_INDEX 16
211 #define DMA_CH_TCR_PBL_WIDTH 6
212 #define DMA_CH_TCR_ST_INDEX 0
213 #define DMA_CH_TCR_ST_WIDTH 1
214 #define DMA_CH_TCR_TSE_INDEX 12
215 #define DMA_CH_TCR_TSE_WIDTH 1
217 /* DMA channel register values */
218 #define DMA_OSP_DISABLE 0x00
219 #define DMA_OSP_ENABLE 0x01
224 #define DMA_PBL_16 16
225 #define DMA_PBL_32 32
226 #define DMA_PBL_64 64 /* 8 x 8 */
227 #define DMA_PBL_128 128 /* 8 x 16 */
228 #define DMA_PBL_256 256 /* 8 x 32 */
229 #define DMA_PBL_X8_DISABLE 0x00
230 #define DMA_PBL_X8_ENABLE 0x01
232 /* MAC register offsets */
233 #define MAC_TCR 0x0000
234 #define MAC_RCR 0x0004
235 #define MAC_PFR 0x0008
236 #define MAC_WTR 0x000c
237 #define MAC_HTR0 0x0010
238 #define MAC_VLANTR 0x0050
239 #define MAC_VLANHTR 0x0058
240 #define MAC_VLANIR 0x0060
241 #define MAC_IVLANIR 0x0064
242 #define MAC_RETMR 0x006c
243 #define MAC_Q0TFCR 0x0070
244 #define MAC_RFCR 0x0090
245 #define MAC_RQC0R 0x00a0
246 #define MAC_RQC1R 0x00a4
247 #define MAC_RQC2R 0x00a8
248 #define MAC_RQC3R 0x00ac
249 #define MAC_ISR 0x00b0
250 #define MAC_IER 0x00b4
251 #define MAC_RTSR 0x00b8
252 #define MAC_PMTCSR 0x00c0
253 #define MAC_RWKPFR 0x00c4
254 #define MAC_LPICSR 0x00d0
255 #define MAC_LPITCR 0x00d4
256 #define MAC_VR 0x0110
257 #define MAC_DR 0x0114
258 #define MAC_HWF0R 0x011c
259 #define MAC_HWF1R 0x0120
260 #define MAC_HWF2R 0x0124
261 #define MAC_MDIOSCAR 0x0200
262 #define MAC_MDIOSCCDR 0x0204
263 #define MAC_MDIOISR 0x0214
264 #define MAC_MDIOIER 0x0218
265 #define MAC_MDIOCL22R 0x0220
266 #define MAC_GPIOCR 0x0278
267 #define MAC_GPIOSR 0x027c
268 #define MAC_MACA0HR 0x0300
269 #define MAC_MACA0LR 0x0304
270 #define MAC_MACA1HR 0x0308
271 #define MAC_MACA1LR 0x030c
272 #define MAC_RSSCR 0x0c80
273 #define MAC_RSSAR 0x0c88
274 #define MAC_RSSDR 0x0c8c
275 #define MAC_TSCR 0x0d00
276 #define MAC_SSIR 0x0d04
277 #define MAC_STSR 0x0d08
278 #define MAC_STNR 0x0d0c
279 #define MAC_STSUR 0x0d10
280 #define MAC_STNUR 0x0d14
281 #define MAC_TSAR 0x0d18
282 #define MAC_TSSR 0x0d20
283 #define MAC_TXSNR 0x0d30
284 #define MAC_TXSSR 0x0d34
286 #define MAC_QTFCR_INC 4
287 #define MAC_MACA_INC 4
288 #define MAC_HTR_INC 4
290 #define MAC_RQC2_INC 4
291 #define MAC_RQC2_Q_PER_REG 4
293 #define MAC_MACAHR(i) (MAC_MACA0HR + ((i) * 8))
294 #define MAC_MACALR(i) (MAC_MACA0LR + ((i) * 8))
296 #define MAC_HTR(i) (MAC_HTR0 + ((i) * MAC_HTR_INC))
298 /* MAC register entry bit positions and sizes */
299 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18
300 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
301 #define MAC_HWF0R_ARPOFFSEL_INDEX 9
302 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1
303 #define MAC_HWF0R_EEESEL_INDEX 13
304 #define MAC_HWF0R_EEESEL_WIDTH 1
305 #define MAC_HWF0R_GMIISEL_INDEX 1
306 #define MAC_HWF0R_GMIISEL_WIDTH 1
307 #define MAC_HWF0R_MGKSEL_INDEX 7
308 #define MAC_HWF0R_MGKSEL_WIDTH 1
309 #define MAC_HWF0R_MMCSEL_INDEX 8
310 #define MAC_HWF0R_MMCSEL_WIDTH 1
311 #define MAC_HWF0R_RWKSEL_INDEX 6
312 #define MAC_HWF0R_RWKSEL_WIDTH 1
313 #define MAC_HWF0R_RXCOESEL_INDEX 16
314 #define MAC_HWF0R_RXCOESEL_WIDTH 1
315 #define MAC_HWF0R_SAVLANINS_INDEX 27
316 #define MAC_HWF0R_SAVLANINS_WIDTH 1
317 #define MAC_HWF0R_SMASEL_INDEX 5
318 #define MAC_HWF0R_SMASEL_WIDTH 1
319 #define MAC_HWF0R_TSSEL_INDEX 12
320 #define MAC_HWF0R_TSSEL_WIDTH 1
321 #define MAC_HWF0R_TSSTSSEL_INDEX 25
322 #define MAC_HWF0R_TSSTSSEL_WIDTH 2
323 #define MAC_HWF0R_TXCOESEL_INDEX 14
324 #define MAC_HWF0R_TXCOESEL_WIDTH 1
325 #define MAC_HWF0R_VLHASH_INDEX 4
326 #define MAC_HWF0R_VLHASH_WIDTH 1
327 #define MAC_HWF1R_ADDR64_INDEX 14
328 #define MAC_HWF1R_ADDR64_WIDTH 2
329 #define MAC_HWF1R_ADVTHWORD_INDEX 13
330 #define MAC_HWF1R_ADVTHWORD_WIDTH 1
331 #define MAC_HWF1R_DBGMEMA_INDEX 19
332 #define MAC_HWF1R_DBGMEMA_WIDTH 1
333 #define MAC_HWF1R_DCBEN_INDEX 16
334 #define MAC_HWF1R_DCBEN_WIDTH 1
335 #define MAC_HWF1R_HASHTBLSZ_INDEX 24
336 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3
337 #define MAC_HWF1R_L3L4FNUM_INDEX 27
338 #define MAC_HWF1R_L3L4FNUM_WIDTH 4
339 #define MAC_HWF1R_NUMTC_INDEX 21
340 #define MAC_HWF1R_NUMTC_WIDTH 3
341 #define MAC_HWF1R_RSSEN_INDEX 20
342 #define MAC_HWF1R_RSSEN_WIDTH 1
343 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0
344 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5
345 #define MAC_HWF1R_SPHEN_INDEX 17
346 #define MAC_HWF1R_SPHEN_WIDTH 1
347 #define MAC_HWF1R_TSOEN_INDEX 18
348 #define MAC_HWF1R_TSOEN_WIDTH 1
349 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6
350 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5
351 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28
352 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3
353 #define MAC_HWF2R_PPSOUTNUM_INDEX 24
354 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3
355 #define MAC_HWF2R_RXCHCNT_INDEX 12
356 #define MAC_HWF2R_RXCHCNT_WIDTH 4
357 #define MAC_HWF2R_RXQCNT_INDEX 0
358 #define MAC_HWF2R_RXQCNT_WIDTH 4
359 #define MAC_HWF2R_TXCHCNT_INDEX 18
360 #define MAC_HWF2R_TXCHCNT_WIDTH 4
361 #define MAC_HWF2R_TXQCNT_INDEX 6
362 #define MAC_HWF2R_TXQCNT_WIDTH 4
363 #define MAC_IER_TSIE_INDEX 12
364 #define MAC_IER_TSIE_WIDTH 1
365 #define MAC_ISR_MMCRXIS_INDEX 9
366 #define MAC_ISR_MMCRXIS_WIDTH 1
367 #define MAC_ISR_MMCTXIS_INDEX 10
368 #define MAC_ISR_MMCTXIS_WIDTH 1
369 #define MAC_ISR_PMTIS_INDEX 4
370 #define MAC_ISR_PMTIS_WIDTH 1
371 #define MAC_ISR_SMI_INDEX 1
372 #define MAC_ISR_SMI_WIDTH 1
373 #define MAC_ISR_LSI_INDEX 0
374 #define MAC_ISR_LSI_WIDTH 1
375 #define MAC_ISR_LS_INDEX 24
376 #define MAC_ISR_LS_WIDTH 2
377 #define MAC_ISR_TSIS_INDEX 12
378 #define MAC_ISR_TSIS_WIDTH 1
379 #define MAC_MACA1HR_AE_INDEX 31
380 #define MAC_MACA1HR_AE_WIDTH 1
381 #define MAC_MDIOIER_SNGLCOMPIE_INDEX 12
382 #define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1
383 #define MAC_MDIOISR_SNGLCOMPINT_INDEX 12
384 #define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1
385 #define MAC_MDIOSCAR_DA_INDEX 21
386 #define MAC_MDIOSCAR_DA_WIDTH 5
387 #define MAC_MDIOSCAR_PA_INDEX 16
388 #define MAC_MDIOSCAR_PA_WIDTH 5
389 #define MAC_MDIOSCAR_RA_INDEX 0
390 #define MAC_MDIOSCAR_RA_WIDTH 16
391 #define MAC_MDIOSCAR_REG_INDEX 0
392 #define MAC_MDIOSCAR_REG_WIDTH 21
393 #define MAC_MDIOSCCDR_BUSY_INDEX 22
394 #define MAC_MDIOSCCDR_BUSY_WIDTH 1
395 #define MAC_MDIOSCCDR_CMD_INDEX 16
396 #define MAC_MDIOSCCDR_CMD_WIDTH 2
397 #define MAC_MDIOSCCDR_CR_INDEX 19
398 #define MAC_MDIOSCCDR_CR_WIDTH 3
399 #define MAC_MDIOSCCDR_DATA_INDEX 0
400 #define MAC_MDIOSCCDR_DATA_WIDTH 16
401 #define MAC_MDIOSCCDR_SADDR_INDEX 18
402 #define MAC_MDIOSCCDR_SADDR_WIDTH 1
403 #define MAC_PFR_HMC_INDEX 2
404 #define MAC_PFR_HMC_WIDTH 1
405 #define MAC_PFR_HPF_INDEX 10
406 #define MAC_PFR_HPF_WIDTH 1
407 #define MAC_PFR_HUC_INDEX 1
408 #define MAC_PFR_HUC_WIDTH 1
409 #define MAC_PFR_PM_INDEX 4
410 #define MAC_PFR_PM_WIDTH 1
411 #define MAC_PFR_PR_INDEX 0
412 #define MAC_PFR_PR_WIDTH 1
413 #define MAC_PFR_VTFE_INDEX 16
414 #define MAC_PFR_VTFE_WIDTH 1
415 #define MAC_PMTCSR_MGKPKTEN_INDEX 1
416 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1
417 #define MAC_PMTCSR_PWRDWN_INDEX 0
418 #define MAC_PMTCSR_PWRDWN_WIDTH 1
419 #define MAC_PMTCSR_RWKFILTRST_INDEX 31
420 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1
421 #define MAC_PMTCSR_RWKPKTEN_INDEX 2
422 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1
423 #define MAC_Q0TFCR_PT_INDEX 16
424 #define MAC_Q0TFCR_PT_WIDTH 16
425 #define MAC_Q0TFCR_TFE_INDEX 1
426 #define MAC_Q0TFCR_TFE_WIDTH 1
427 #define MAC_RCR_ACS_INDEX 1
428 #define MAC_RCR_ACS_WIDTH 1
429 #define MAC_RCR_CST_INDEX 2
430 #define MAC_RCR_CST_WIDTH 1
431 #define MAC_RCR_DCRCC_INDEX 3
432 #define MAC_RCR_DCRCC_WIDTH 1
433 #define MAC_RCR_HDSMS_INDEX 12
434 #define MAC_RCR_HDSMS_WIDTH 3
435 #define MAC_RCR_IPC_INDEX 9
436 #define MAC_RCR_IPC_WIDTH 1
437 #define MAC_RCR_JE_INDEX 8
438 #define MAC_RCR_JE_WIDTH 1
439 #define MAC_RCR_LM_INDEX 10
440 #define MAC_RCR_LM_WIDTH 1
441 #define MAC_RCR_RE_INDEX 0
442 #define MAC_RCR_RE_WIDTH 1
443 #define MAC_RFCR_PFCE_INDEX 8
444 #define MAC_RFCR_PFCE_WIDTH 1
445 #define MAC_RFCR_RFE_INDEX 0
446 #define MAC_RFCR_RFE_WIDTH 1
447 #define MAC_RFCR_UP_INDEX 1
448 #define MAC_RFCR_UP_WIDTH 1
449 #define MAC_RQC0R_RXQ0EN_INDEX 0
450 #define MAC_RQC0R_RXQ0EN_WIDTH 2
451 #define MAC_RSSAR_ADDRT_INDEX 2
452 #define MAC_RSSAR_ADDRT_WIDTH 1
453 #define MAC_RSSAR_CT_INDEX 1
454 #define MAC_RSSAR_CT_WIDTH 1
455 #define MAC_RSSAR_OB_INDEX 0
456 #define MAC_RSSAR_OB_WIDTH 1
457 #define MAC_RSSAR_RSSIA_INDEX 8
458 #define MAC_RSSAR_RSSIA_WIDTH 8
459 #define MAC_RSSCR_IP2TE_INDEX 1
460 #define MAC_RSSCR_IP2TE_WIDTH 1
461 #define MAC_RSSCR_RSSE_INDEX 0
462 #define MAC_RSSCR_RSSE_WIDTH 1
463 #define MAC_RSSCR_TCP4TE_INDEX 2
464 #define MAC_RSSCR_TCP4TE_WIDTH 1
465 #define MAC_RSSCR_UDP4TE_INDEX 3
466 #define MAC_RSSCR_UDP4TE_WIDTH 1
467 #define MAC_RSSDR_DMCH_INDEX 0
468 #define MAC_RSSDR_DMCH_WIDTH 4
469 #define MAC_SSIR_SNSINC_INDEX 8
470 #define MAC_SSIR_SNSINC_WIDTH 8
471 #define MAC_SSIR_SSINC_INDEX 16
472 #define MAC_SSIR_SSINC_WIDTH 8
473 #define MAC_TCR_SS_INDEX 29
474 #define MAC_TCR_SS_WIDTH 2
475 #define MAC_TCR_TE_INDEX 0
476 #define MAC_TCR_TE_WIDTH 1
477 #define MAC_TSCR_AV8021ASMEN_INDEX 28
478 #define MAC_TSCR_AV8021ASMEN_WIDTH 1
479 #define MAC_TSCR_SNAPTYPSEL_INDEX 16
480 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2
481 #define MAC_TSCR_TSADDREG_INDEX 5
482 #define MAC_TSCR_TSADDREG_WIDTH 1
483 #define MAC_TSCR_TSCFUPDT_INDEX 1
484 #define MAC_TSCR_TSCFUPDT_WIDTH 1
485 #define MAC_TSCR_TSCTRLSSR_INDEX 9
486 #define MAC_TSCR_TSCTRLSSR_WIDTH 1
487 #define MAC_TSCR_TSENA_INDEX 0
488 #define MAC_TSCR_TSENA_WIDTH 1
489 #define MAC_TSCR_TSENALL_INDEX 8
490 #define MAC_TSCR_TSENALL_WIDTH 1
491 #define MAC_TSCR_TSEVNTENA_INDEX 14
492 #define MAC_TSCR_TSEVNTENA_WIDTH 1
493 #define MAC_TSCR_TSINIT_INDEX 2
494 #define MAC_TSCR_TSINIT_WIDTH 1
495 #define MAC_TSCR_TSIPENA_INDEX 11
496 #define MAC_TSCR_TSIPENA_WIDTH 1
497 #define MAC_TSCR_TSIPV4ENA_INDEX 13
498 #define MAC_TSCR_TSIPV4ENA_WIDTH 1
499 #define MAC_TSCR_TSIPV6ENA_INDEX 12
500 #define MAC_TSCR_TSIPV6ENA_WIDTH 1
501 #define MAC_TSCR_TSMSTRENA_INDEX 15
502 #define MAC_TSCR_TSMSTRENA_WIDTH 1
503 #define MAC_TSCR_TSVER2ENA_INDEX 10
504 #define MAC_TSCR_TSVER2ENA_WIDTH 1
505 #define MAC_TSCR_TXTSSTSM_INDEX 24
506 #define MAC_TSCR_TXTSSTSM_WIDTH 1
507 #define MAC_TSSR_TXTSC_INDEX 15
508 #define MAC_TSSR_TXTSC_WIDTH 1
509 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31
510 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1
511 #define MAC_VLANHTR_VLHT_INDEX 0
512 #define MAC_VLANHTR_VLHT_WIDTH 16
513 #define MAC_VLANIR_VLTI_INDEX 20
514 #define MAC_VLANIR_VLTI_WIDTH 1
515 #define MAC_VLANIR_CSVL_INDEX 19
516 #define MAC_VLANIR_CSVL_WIDTH 1
517 #define MAC_VLANTR_DOVLTC_INDEX 20
518 #define MAC_VLANTR_DOVLTC_WIDTH 1
519 #define MAC_VLANTR_ERSVLM_INDEX 19
520 #define MAC_VLANTR_ERSVLM_WIDTH 1
521 #define MAC_VLANTR_ESVL_INDEX 18
522 #define MAC_VLANTR_ESVL_WIDTH 1
523 #define MAC_VLANTR_ETV_INDEX 16
524 #define MAC_VLANTR_ETV_WIDTH 1
525 #define MAC_VLANTR_EVLS_INDEX 21
526 #define MAC_VLANTR_EVLS_WIDTH 2
527 #define MAC_VLANTR_EVLRXS_INDEX 24
528 #define MAC_VLANTR_EVLRXS_WIDTH 1
529 #define MAC_VLANTR_VL_INDEX 0
530 #define MAC_VLANTR_VL_WIDTH 16
531 #define MAC_VLANTR_VTHM_INDEX 25
532 #define MAC_VLANTR_VTHM_WIDTH 1
533 #define MAC_VLANTR_VTIM_INDEX 17
534 #define MAC_VLANTR_VTIM_WIDTH 1
535 #define MAC_VR_DEVID_INDEX 8
536 #define MAC_VR_DEVID_WIDTH 8
537 #define MAC_VR_SNPSVER_INDEX 0
538 #define MAC_VR_SNPSVER_WIDTH 8
539 #define MAC_VR_USERVER_INDEX 16
540 #define MAC_VR_USERVER_WIDTH 8
542 /* MMC register offsets */
543 #define MMC_CR 0x0800
544 #define MMC_RISR 0x0804
545 #define MMC_TISR 0x0808
546 #define MMC_RIER 0x080c
547 #define MMC_TIER 0x0810
548 #define MMC_TXOCTETCOUNT_GB_LO 0x0814
549 #define MMC_TXOCTETCOUNT_GB_HI 0x0818
550 #define MMC_TXFRAMECOUNT_GB_LO 0x081c
551 #define MMC_TXFRAMECOUNT_GB_HI 0x0820
552 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824
553 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828
554 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c
555 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830
556 #define MMC_TX64OCTETS_GB_LO 0x0834
557 #define MMC_TX64OCTETS_GB_HI 0x0838
558 #define MMC_TX65TO127OCTETS_GB_LO 0x083c
559 #define MMC_TX65TO127OCTETS_GB_HI 0x0840
560 #define MMC_TX128TO255OCTETS_GB_LO 0x0844
561 #define MMC_TX128TO255OCTETS_GB_HI 0x0848
562 #define MMC_TX256TO511OCTETS_GB_LO 0x084c
563 #define MMC_TX256TO511OCTETS_GB_HI 0x0850
564 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854
565 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858
566 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
567 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860
568 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864
569 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868
570 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
571 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870
572 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
573 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878
574 #define MMC_TXUNDERFLOWERROR_LO 0x087c
575 #define MMC_TXUNDERFLOWERROR_HI 0x0880
576 #define MMC_TXOCTETCOUNT_G_LO 0x0884
577 #define MMC_TXOCTETCOUNT_G_HI 0x0888
578 #define MMC_TXFRAMECOUNT_G_LO 0x088c
579 #define MMC_TXFRAMECOUNT_G_HI 0x0890
580 #define MMC_TXPAUSEFRAMES_LO 0x0894
581 #define MMC_TXPAUSEFRAMES_HI 0x0898
582 #define MMC_TXVLANFRAMES_G_LO 0x089c
583 #define MMC_TXVLANFRAMES_G_HI 0x08a0
584 #define MMC_RXFRAMECOUNT_GB_LO 0x0900
585 #define MMC_RXFRAMECOUNT_GB_HI 0x0904
586 #define MMC_RXOCTETCOUNT_GB_LO 0x0908
587 #define MMC_RXOCTETCOUNT_GB_HI 0x090c
588 #define MMC_RXOCTETCOUNT_G_LO 0x0910
589 #define MMC_RXOCTETCOUNT_G_HI 0x0914
590 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918
591 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c
592 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920
593 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924
594 #define MMC_RXCRCERROR_LO 0x0928
595 #define MMC_RXCRCERROR_HI 0x092c
596 #define MMC_RXRUNTERROR 0x0930
597 #define MMC_RXJABBERERROR 0x0934
598 #define MMC_RXUNDERSIZE_G 0x0938
599 #define MMC_RXOVERSIZE_G 0x093c
600 #define MMC_RX64OCTETS_GB_LO 0x0940
601 #define MMC_RX64OCTETS_GB_HI 0x0944
602 #define MMC_RX65TO127OCTETS_GB_LO 0x0948
603 #define MMC_RX65TO127OCTETS_GB_HI 0x094c
604 #define MMC_RX128TO255OCTETS_GB_LO 0x0950
605 #define MMC_RX128TO255OCTETS_GB_HI 0x0954
606 #define MMC_RX256TO511OCTETS_GB_LO 0x0958
607 #define MMC_RX256TO511OCTETS_GB_HI 0x095c
608 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960
609 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964
610 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
611 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c
612 #define MMC_RXUNICASTFRAMES_G_LO 0x0970
613 #define MMC_RXUNICASTFRAMES_G_HI 0x0974
614 #define MMC_RXLENGTHERROR_LO 0x0978
615 #define MMC_RXLENGTHERROR_HI 0x097c
616 #define MMC_RXOUTOFRANGETYPE_LO 0x0980
617 #define MMC_RXOUTOFRANGETYPE_HI 0x0984
618 #define MMC_RXPAUSEFRAMES_LO 0x0988
619 #define MMC_RXPAUSEFRAMES_HI 0x098c
620 #define MMC_RXFIFOOVERFLOW_LO 0x0990
621 #define MMC_RXFIFOOVERFLOW_HI 0x0994
622 #define MMC_RXVLANFRAMES_GB_LO 0x0998
623 #define MMC_RXVLANFRAMES_GB_HI 0x099c
624 #define MMC_RXWATCHDOGERROR 0x09a0
626 /* MMC register entry bit positions and sizes */
627 #define MMC_CR_CR_INDEX 0
628 #define MMC_CR_CR_WIDTH 1
629 #define MMC_CR_CSR_INDEX 1
630 #define MMC_CR_CSR_WIDTH 1
631 #define MMC_CR_ROR_INDEX 2
632 #define MMC_CR_ROR_WIDTH 1
633 #define MMC_CR_MCF_INDEX 3
634 #define MMC_CR_MCF_WIDTH 1
635 #define MMC_CR_MCT_INDEX 4
636 #define MMC_CR_MCT_WIDTH 2
637 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0
638 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23
639 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0
640 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1
641 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1
642 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1
643 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2
644 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1
645 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3
646 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1
647 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4
648 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1
649 #define MMC_RISR_RXCRCERROR_INDEX 5
650 #define MMC_RISR_RXCRCERROR_WIDTH 1
651 #define MMC_RISR_RXRUNTERROR_INDEX 6
652 #define MMC_RISR_RXRUNTERROR_WIDTH 1
653 #define MMC_RISR_RXJABBERERROR_INDEX 7
654 #define MMC_RISR_RXJABBERERROR_WIDTH 1
655 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8
656 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1
657 #define MMC_RISR_RXOVERSIZE_G_INDEX 9
658 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1
659 #define MMC_RISR_RX64OCTETS_GB_INDEX 10
660 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1
661 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11
662 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1
663 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12
664 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1
665 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13
666 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1
667 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14
668 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1
669 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15
670 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1
671 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16
672 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1
673 #define MMC_RISR_RXLENGTHERROR_INDEX 17
674 #define MMC_RISR_RXLENGTHERROR_WIDTH 1
675 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18
676 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1
677 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19
678 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1
679 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20
680 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1
681 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21
682 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1
683 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22
684 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1
685 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0
686 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18
687 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0
688 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1
689 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1
690 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1
691 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2
692 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1
693 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3
694 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1
695 #define MMC_TISR_TX64OCTETS_GB_INDEX 4
696 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1
697 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5
698 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1
699 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6
700 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1
701 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7
702 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1
703 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8
704 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1
705 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9
706 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1
707 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10
708 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1
709 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11
710 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1
711 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12
712 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1
713 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13
714 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1
715 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14
716 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1
717 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15
718 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1
719 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16
720 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1
721 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17
722 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1
724 /* MTL register offsets */
725 #define MTL_OMR 0x1000
726 #define MTL_FDCR 0x1008
727 #define MTL_FDSR 0x100c
728 #define MTL_FDDR 0x1010
729 #define MTL_ISR 0x1020
730 #define MTL_RQDCM0R 0x1030
731 #define MTL_TCPM0R 0x1040
732 #define MTL_TCPM1R 0x1044
734 #define MTL_RQDCM_INC 4
735 #define MTL_RQDCM_Q_PER_REG 4
736 #define MTL_TCPM_INC 4
737 #define MTL_TCPM_TC_PER_REG 4
739 /* MTL register entry bit positions and sizes */
740 #define MTL_OMR_ETSALG_INDEX 5
741 #define MTL_OMR_ETSALG_WIDTH 2
742 #define MTL_OMR_RAA_INDEX 2
743 #define MTL_OMR_RAA_WIDTH 1
745 /* MTL queue register offsets
746 * Multiple queues can be active. The first queue has registers
747 * that begin at 0x1100. Each subsequent queue has registers that
748 * are accessed using an offset of 0x80 from the previous queue.
750 #define MTL_Q_BASE 0x1100
751 #define MTL_Q_INC 0x80
753 #define MTL_Q_TQOMR 0x00
754 #define MTL_Q_TQUR 0x04
755 #define MTL_Q_TQDR 0x08
756 #define MTL_Q_RQOMR 0x40
757 #define MTL_Q_RQMPOCR 0x44
758 #define MTL_Q_RQDR 0x48
759 #define MTL_Q_RQFCR 0x50
760 #define MTL_Q_IER 0x70
761 #define MTL_Q_ISR 0x74
763 /* MTL queue register entry bit positions and sizes */
764 #define MTL_Q_RQDR_PRXQ_INDEX 16
765 #define MTL_Q_RQDR_PRXQ_WIDTH 14
766 #define MTL_Q_RQDR_RXQSTS_INDEX 4
767 #define MTL_Q_RQDR_RXQSTS_WIDTH 2
768 #define MTL_Q_RQFCR_RFA_INDEX 1
769 #define MTL_Q_RQFCR_RFA_WIDTH 6
770 #define MTL_Q_RQFCR_RFD_INDEX 17
771 #define MTL_Q_RQFCR_RFD_WIDTH 6
772 #define MTL_Q_RQOMR_EHFC_INDEX 7
773 #define MTL_Q_RQOMR_EHFC_WIDTH 1
774 #define MTL_Q_RQOMR_RQS_INDEX 16
775 #define MTL_Q_RQOMR_RQS_WIDTH 9
776 #define MTL_Q_RQOMR_RSF_INDEX 5
777 #define MTL_Q_RQOMR_RSF_WIDTH 1
778 #define MTL_Q_RQOMR_RTC_INDEX 0
779 #define MTL_Q_RQOMR_RTC_WIDTH 2
780 #define MTL_Q_TQDR_TRCSTS_INDEX 1
781 #define MTL_Q_TQDR_TRCSTS_WIDTH 2
782 #define MTL_Q_TQDR_TXQSTS_INDEX 4
783 #define MTL_Q_TQDR_TXQSTS_WIDTH 1
784 #define MTL_Q_TQOMR_FTQ_INDEX 0
785 #define MTL_Q_TQOMR_FTQ_WIDTH 1
786 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8
787 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3
788 #define MTL_Q_TQOMR_TQS_INDEX 16
789 #define MTL_Q_TQOMR_TQS_WIDTH 10
790 #define MTL_Q_TQOMR_TSF_INDEX 1
791 #define MTL_Q_TQOMR_TSF_WIDTH 1
792 #define MTL_Q_TQOMR_TTC_INDEX 4
793 #define MTL_Q_TQOMR_TTC_WIDTH 3
794 #define MTL_Q_TQOMR_TXQEN_INDEX 2
795 #define MTL_Q_TQOMR_TXQEN_WIDTH 2
797 /* MTL queue register value */
798 #define MTL_RSF_DISABLE 0x00
799 #define MTL_RSF_ENABLE 0x01
800 #define MTL_TSF_DISABLE 0x00
801 #define MTL_TSF_ENABLE 0x01
803 #define MTL_RX_THRESHOLD_64 0x00
804 #define MTL_RX_THRESHOLD_96 0x02
805 #define MTL_RX_THRESHOLD_128 0x03
806 #define MTL_TX_THRESHOLD_32 0x01
807 #define MTL_TX_THRESHOLD_64 0x00
808 #define MTL_TX_THRESHOLD_96 0x02
809 #define MTL_TX_THRESHOLD_128 0x03
810 #define MTL_TX_THRESHOLD_192 0x04
811 #define MTL_TX_THRESHOLD_256 0x05
812 #define MTL_TX_THRESHOLD_384 0x06
813 #define MTL_TX_THRESHOLD_512 0x07
815 #define MTL_ETSALG_WRR 0x00
816 #define MTL_ETSALG_WFQ 0x01
817 #define MTL_ETSALG_DWRR 0x02
818 #define MTL_RAA_SP 0x00
819 #define MTL_RAA_WSP 0x01
821 #define MTL_Q_DISABLED 0x00
822 #define MTL_Q_ENABLED 0x02
824 /* MTL traffic class register offsets
825 * Multiple traffic classes can be active. The first class has registers
826 * that begin at 0x1100. Each subsequent queue has registers that
827 * are accessed using an offset of 0x80 from the previous queue.
829 #define MTL_TC_BASE MTL_Q_BASE
830 #define MTL_TC_INC MTL_Q_INC
832 #define MTL_TC_ETSCR 0x10
833 #define MTL_TC_ETSSR 0x14
834 #define MTL_TC_QWR 0x18
836 /* MTL traffic class register entry bit positions and sizes */
837 #define MTL_TC_ETSCR_TSA_INDEX 0
838 #define MTL_TC_ETSCR_TSA_WIDTH 2
839 #define MTL_TC_QWR_QW_INDEX 0
840 #define MTL_TC_QWR_QW_WIDTH 21
841 #define MTL_TCPM0R_PSTC0_INDEX 0
842 #define MTL_TCPM0R_PSTC0_WIDTH 8
843 #define MTL_TCPM0R_PSTC1_INDEX 8
844 #define MTL_TCPM0R_PSTC1_WIDTH 8
845 #define MTL_TCPM0R_PSTC2_INDEX 16
846 #define MTL_TCPM0R_PSTC2_WIDTH 8
847 #define MTL_TCPM0R_PSTC3_INDEX 24
848 #define MTL_TCPM0R_PSTC3_WIDTH 8
849 #define MTL_TCPM1R_PSTC4_INDEX 0
850 #define MTL_TCPM1R_PSTC4_WIDTH 8
851 #define MTL_TCPM1R_PSTC5_INDEX 8
852 #define MTL_TCPM1R_PSTC5_WIDTH 8
853 #define MTL_TCPM1R_PSTC6_INDEX 16
854 #define MTL_TCPM1R_PSTC6_WIDTH 8
855 #define MTL_TCPM1R_PSTC7_INDEX 24
856 #define MTL_TCPM1R_PSTC7_WIDTH 8
858 /* MTL traffic class register value */
859 #define MTL_TSA_SP 0x00
860 #define MTL_TSA_ETS 0x02
862 /* PCS register offsets */
863 #define PCS_V1_WINDOW_SELECT 0x03fc
864 #define PCS_V2_WINDOW_DEF 0x9060
865 #define PCS_V2_WINDOW_SELECT 0x9064
866 #define PCS_V2_RV_WINDOW_DEF 0x1060
867 #define PCS_V2_RV_WINDOW_SELECT 0x1064
869 /* PCS register entry bit positions and sizes */
870 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
871 #define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14
872 #define PCS_V2_WINDOW_DEF_SIZE_INDEX 2
873 #define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4
875 /* SerDes integration register offsets */
876 #define SIR0_KR_RT_1 0x002c
877 #define SIR0_STATUS 0x0040
878 #define SIR1_SPEED 0x0000
880 /* SerDes integration register entry bit positions and sizes */
881 #define SIR0_KR_RT_1_RESET_INDEX 11
882 #define SIR0_KR_RT_1_RESET_WIDTH 1
883 #define SIR0_STATUS_RX_READY_INDEX 0
884 #define SIR0_STATUS_RX_READY_WIDTH 1
885 #define SIR0_STATUS_TX_READY_INDEX 8
886 #define SIR0_STATUS_TX_READY_WIDTH 1
887 #define SIR1_SPEED_CDR_RATE_INDEX 12
888 #define SIR1_SPEED_CDR_RATE_WIDTH 4
889 #define SIR1_SPEED_DATARATE_INDEX 4
890 #define SIR1_SPEED_DATARATE_WIDTH 2
891 #define SIR1_SPEED_PLLSEL_INDEX 3
892 #define SIR1_SPEED_PLLSEL_WIDTH 1
893 #define SIR1_SPEED_RATECHANGE_INDEX 6
894 #define SIR1_SPEED_RATECHANGE_WIDTH 1
895 #define SIR1_SPEED_TXAMP_INDEX 8
896 #define SIR1_SPEED_TXAMP_WIDTH 4
897 #define SIR1_SPEED_WORDMODE_INDEX 0
898 #define SIR1_SPEED_WORDMODE_WIDTH 3
900 /* SerDes RxTx register offsets */
901 #define RXTX_REG6 0x0018
902 #define RXTX_REG20 0x0050
903 #define RXTX_REG22 0x0058
904 #define RXTX_REG114 0x01c8
905 #define RXTX_REG129 0x0204
907 /* SerDes RxTx register entry bit positions and sizes */
908 #define RXTX_REG6_RESETB_RXD_INDEX 8
909 #define RXTX_REG6_RESETB_RXD_WIDTH 1
910 #define RXTX_REG20_BLWC_ENA_INDEX 2
911 #define RXTX_REG20_BLWC_ENA_WIDTH 1
912 #define RXTX_REG114_PQ_REG_INDEX 9
913 #define RXTX_REG114_PQ_REG_WIDTH 7
914 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14
915 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2
917 /* MAC Control register offsets */
918 #define XP_PROP_0 0x0000
919 #define XP_PROP_1 0x0004
920 #define XP_PROP_2 0x0008
921 #define XP_PROP_3 0x000c
922 #define XP_PROP_4 0x0010
923 #define XP_PROP_5 0x0014
924 #define XP_MAC_ADDR_LO 0x0020
925 #define XP_MAC_ADDR_HI 0x0024
926 #define XP_ECC_ISR 0x0030
927 #define XP_ECC_IER 0x0034
928 #define XP_ECC_CNT0 0x003c
929 #define XP_ECC_CNT1 0x0040
930 #define XP_DRIVER_INT_REQ 0x0060
931 #define XP_DRIVER_INT_RO 0x0064
932 #define XP_DRIVER_SCRATCH_0 0x0068
933 #define XP_DRIVER_SCRATCH_1 0x006c
934 #define XP_INT_EN 0x0078
935 #define XP_I2C_MUTEX 0x0080
936 #define XP_MDIO_MUTEX 0x0084
938 /* MAC Control register entry bit positions and sizes */
939 #define XP_DRIVER_INT_REQ_REQUEST_INDEX 0
940 #define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1
941 #define XP_DRIVER_INT_RO_STATUS_INDEX 0
942 #define XP_DRIVER_INT_RO_STATUS_WIDTH 1
943 #define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0
944 #define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8
945 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8
946 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8
947 #define XP_ECC_CNT0_RX_DED_INDEX 24
948 #define XP_ECC_CNT0_RX_DED_WIDTH 8
949 #define XP_ECC_CNT0_RX_SEC_INDEX 16
950 #define XP_ECC_CNT0_RX_SEC_WIDTH 8
951 #define XP_ECC_CNT0_TX_DED_INDEX 8
952 #define XP_ECC_CNT0_TX_DED_WIDTH 8
953 #define XP_ECC_CNT0_TX_SEC_INDEX 0
954 #define XP_ECC_CNT0_TX_SEC_WIDTH 8
955 #define XP_ECC_CNT1_DESC_DED_INDEX 8
956 #define XP_ECC_CNT1_DESC_DED_WIDTH 8
957 #define XP_ECC_CNT1_DESC_SEC_INDEX 0
958 #define XP_ECC_CNT1_DESC_SEC_WIDTH 8
959 #define XP_ECC_IER_DESC_DED_INDEX 0
960 #define XP_ECC_IER_DESC_DED_WIDTH 1
961 #define XP_ECC_IER_DESC_SEC_INDEX 1
962 #define XP_ECC_IER_DESC_SEC_WIDTH 1
963 #define XP_ECC_IER_RX_DED_INDEX 2
964 #define XP_ECC_IER_RX_DED_WIDTH 1
965 #define XP_ECC_IER_RX_SEC_INDEX 3
966 #define XP_ECC_IER_RX_SEC_WIDTH 1
967 #define XP_ECC_IER_TX_DED_INDEX 4
968 #define XP_ECC_IER_TX_DED_WIDTH 1
969 #define XP_ECC_IER_TX_SEC_INDEX 5
970 #define XP_ECC_IER_TX_SEC_WIDTH 1
971 #define XP_ECC_ISR_DESC_DED_INDEX 0
972 #define XP_ECC_ISR_DESC_DED_WIDTH 1
973 #define XP_ECC_ISR_DESC_SEC_INDEX 1
974 #define XP_ECC_ISR_DESC_SEC_WIDTH 1
975 #define XP_ECC_ISR_RX_DED_INDEX 2
976 #define XP_ECC_ISR_RX_DED_WIDTH 1
977 #define XP_ECC_ISR_RX_SEC_INDEX 3
978 #define XP_ECC_ISR_RX_SEC_WIDTH 1
979 #define XP_ECC_ISR_TX_DED_INDEX 4
980 #define XP_ECC_ISR_TX_DED_WIDTH 1
981 #define XP_ECC_ISR_TX_SEC_INDEX 5
982 #define XP_ECC_ISR_TX_SEC_WIDTH 1
983 #define XP_I2C_MUTEX_BUSY_INDEX 31
984 #define XP_I2C_MUTEX_BUSY_WIDTH 1
985 #define XP_I2C_MUTEX_ID_INDEX 29
986 #define XP_I2C_MUTEX_ID_WIDTH 2
987 #define XP_I2C_MUTEX_ACTIVE_INDEX 0
988 #define XP_I2C_MUTEX_ACTIVE_WIDTH 1
989 #define XP_MAC_ADDR_HI_VALID_INDEX 31
990 #define XP_MAC_ADDR_HI_VALID_WIDTH 1
991 #define XP_PROP_0_CONN_TYPE_INDEX 28
992 #define XP_PROP_0_CONN_TYPE_WIDTH 3
993 #define XP_PROP_0_MDIO_ADDR_INDEX 16
994 #define XP_PROP_0_MDIO_ADDR_WIDTH 5
995 #define XP_PROP_0_PORT_ID_INDEX 0
996 #define XP_PROP_0_PORT_ID_WIDTH 8
997 #define XP_PROP_0_PORT_MODE_INDEX 8
998 #define XP_PROP_0_PORT_MODE_WIDTH 4
999 #define XP_PROP_0_PORT_SPEEDS_INDEX 23
1000 #define XP_PROP_0_PORT_SPEEDS_WIDTH 4
1001 #define XP_PROP_1_MAX_RX_DMA_INDEX 24
1002 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5
1003 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8
1004 #define XP_PROP_1_MAX_RX_QUEUES_WIDTH 5
1005 #define XP_PROP_1_MAX_TX_DMA_INDEX 16
1006 #define XP_PROP_1_MAX_TX_DMA_WIDTH 5
1007 #define XP_PROP_1_MAX_TX_QUEUES_INDEX 0
1008 #define XP_PROP_1_MAX_TX_QUEUES_WIDTH 5
1009 #define XP_PROP_2_RX_FIFO_SIZE_INDEX 16
1010 #define XP_PROP_2_RX_FIFO_SIZE_WIDTH 16
1011 #define XP_PROP_2_TX_FIFO_SIZE_INDEX 0
1012 #define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16
1013 #define XP_PROP_3_GPIO_MASK_INDEX 28
1014 #define XP_PROP_3_GPIO_MASK_WIDTH 4
1015 #define XP_PROP_3_GPIO_MOD_ABS_INDEX 20
1016 #define XP_PROP_3_GPIO_MOD_ABS_WIDTH 4
1017 #define XP_PROP_3_GPIO_RATE_SELECT_INDEX 16
1018 #define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 4
1019 #define XP_PROP_3_GPIO_RX_LOS_INDEX 24
1020 #define XP_PROP_3_GPIO_RX_LOS_WIDTH 4
1021 #define XP_PROP_3_GPIO_TX_FAULT_INDEX 12
1022 #define XP_PROP_3_GPIO_TX_FAULT_WIDTH 4
1023 #define XP_PROP_3_GPIO_ADDR_INDEX 8
1024 #define XP_PROP_3_GPIO_ADDR_WIDTH 3
1025 #define XP_PROP_3_MDIO_RESET_INDEX 0
1026 #define XP_PROP_3_MDIO_RESET_WIDTH 2
1027 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 8
1028 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 3
1029 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 12
1030 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 4
1031 #define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 4
1032 #define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 2
1033 #define XP_PROP_4_MUX_ADDR_HI_INDEX 8
1034 #define XP_PROP_4_MUX_ADDR_HI_WIDTH 5
1035 #define XP_PROP_4_MUX_ADDR_LO_INDEX 0
1036 #define XP_PROP_4_MUX_ADDR_LO_WIDTH 3
1037 #define XP_PROP_4_MUX_CHAN_INDEX 4
1038 #define XP_PROP_4_MUX_CHAN_WIDTH 3
1039 #define XP_PROP_4_REDRV_ADDR_INDEX 16
1040 #define XP_PROP_4_REDRV_ADDR_WIDTH 7
1041 #define XP_PROP_4_REDRV_IF_INDEX 23
1042 #define XP_PROP_4_REDRV_IF_WIDTH 1
1043 #define XP_PROP_4_REDRV_LANE_INDEX 24
1044 #define XP_PROP_4_REDRV_LANE_WIDTH 3
1045 #define XP_PROP_4_REDRV_MODEL_INDEX 28
1046 #define XP_PROP_4_REDRV_MODEL_WIDTH 3
1047 #define XP_PROP_4_REDRV_PRESENT_INDEX 31
1048 #define XP_PROP_4_REDRV_PRESENT_WIDTH 1
1050 /* I2C Control register offsets */
1051 #define IC_CON 0x0000
1052 #define IC_TAR 0x0004
1053 #define IC_DATA_CMD 0x0010
1054 #define IC_INTR_STAT 0x002c
1055 #define IC_INTR_MASK 0x0030
1056 #define IC_RAW_INTR_STAT 0x0034
1057 #define IC_CLR_INTR 0x0040
1058 #define IC_CLR_TX_ABRT 0x0054
1059 #define IC_CLR_STOP_DET 0x0060
1060 #define IC_ENABLE 0x006c
1061 #define IC_TXFLR 0x0074
1062 #define IC_RXFLR 0x0078
1063 #define IC_TX_ABRT_SOURCE 0x0080
1064 #define IC_ENABLE_STATUS 0x009c
1065 #define IC_COMP_PARAM_1 0x00f4
1067 /* I2C Control register entry bit positions and sizes */
1068 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2
1069 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2
1070 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8
1071 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8
1072 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16
1073 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8
1074 #define IC_CON_MASTER_MODE_INDEX 0
1075 #define IC_CON_MASTER_MODE_WIDTH 1
1076 #define IC_CON_RESTART_EN_INDEX 5
1077 #define IC_CON_RESTART_EN_WIDTH 1
1078 #define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9
1079 #define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1
1080 #define IC_CON_SLAVE_DISABLE_INDEX 6
1081 #define IC_CON_SLAVE_DISABLE_WIDTH 1
1082 #define IC_CON_SPEED_INDEX 1
1083 #define IC_CON_SPEED_WIDTH 2
1084 #define IC_DATA_CMD_CMD_INDEX 8
1085 #define IC_DATA_CMD_CMD_WIDTH 1
1086 #define IC_DATA_CMD_STOP_INDEX 9
1087 #define IC_DATA_CMD_STOP_WIDTH 1
1088 #define IC_ENABLE_ABORT_INDEX 1
1089 #define IC_ENABLE_ABORT_WIDTH 1
1090 #define IC_ENABLE_EN_INDEX 0
1091 #define IC_ENABLE_EN_WIDTH 1
1092 #define IC_ENABLE_STATUS_EN_INDEX 0
1093 #define IC_ENABLE_STATUS_EN_WIDTH 1
1094 #define IC_INTR_MASK_TX_EMPTY_INDEX 4
1095 #define IC_INTR_MASK_TX_EMPTY_WIDTH 1
1096 #define IC_RAW_INTR_STAT_RX_FULL_INDEX 2
1097 #define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1
1098 #define IC_RAW_INTR_STAT_STOP_DET_INDEX 9
1099 #define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1
1100 #define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6
1101 #define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1
1102 #define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4
1103 #define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
1105 /* I2C Control register value */
1106 #define IC_TX_ABRT_7B_ADDR_NOACK 0x0001
1107 #define IC_TX_ABRT_ARB_LOST 0x1000
1109 /* Descriptor/Packet entry bit positions and sizes */
1110 #define RX_PACKET_ERRORS_CRC_INDEX 2
1111 #define RX_PACKET_ERRORS_CRC_WIDTH 1
1112 #define RX_PACKET_ERRORS_FRAME_INDEX 3
1113 #define RX_PACKET_ERRORS_FRAME_WIDTH 1
1114 #define RX_PACKET_ERRORS_LENGTH_INDEX 0
1115 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1
1116 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1
1117 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1
1119 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0
1120 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1
1121 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1
1122 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1123 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2
1124 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1
1125 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3
1126 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1
1127 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4
1128 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1
1129 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5
1130 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1
1131 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6
1132 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1
1134 #define RX_NORMAL_DESC0_OVT_INDEX 0
1135 #define RX_NORMAL_DESC0_OVT_WIDTH 16
1136 #define RX_NORMAL_DESC2_HL_INDEX 0
1137 #define RX_NORMAL_DESC2_HL_WIDTH 10
1138 #define RX_NORMAL_DESC3_CDA_INDEX 27
1139 #define RX_NORMAL_DESC3_CDA_WIDTH 1
1140 #define RX_NORMAL_DESC3_CTXT_INDEX 30
1141 #define RX_NORMAL_DESC3_CTXT_WIDTH 1
1142 #define RX_NORMAL_DESC3_ES_INDEX 15
1143 #define RX_NORMAL_DESC3_ES_WIDTH 1
1144 #define RX_NORMAL_DESC3_ETLT_INDEX 16
1145 #define RX_NORMAL_DESC3_ETLT_WIDTH 4
1146 #define RX_NORMAL_DESC3_FD_INDEX 29
1147 #define RX_NORMAL_DESC3_FD_WIDTH 1
1148 #define RX_NORMAL_DESC3_INTE_INDEX 30
1149 #define RX_NORMAL_DESC3_INTE_WIDTH 1
1150 #define RX_NORMAL_DESC3_L34T_INDEX 20
1151 #define RX_NORMAL_DESC3_L34T_WIDTH 4
1152 #define RX_NORMAL_DESC3_LD_INDEX 28
1153 #define RX_NORMAL_DESC3_LD_WIDTH 1
1154 #define RX_NORMAL_DESC3_OWN_INDEX 31
1155 #define RX_NORMAL_DESC3_OWN_WIDTH 1
1156 #define RX_NORMAL_DESC3_PL_INDEX 0
1157 #define RX_NORMAL_DESC3_PL_WIDTH 14
1158 #define RX_NORMAL_DESC3_RSV_INDEX 26
1159 #define RX_NORMAL_DESC3_RSV_WIDTH 1
1160 #define RX_NORMAL_DESC3_LD_INDEX 28
1161 #define RX_NORMAL_DESC3_LD_WIDTH 1
1163 #define RX_DESC3_L34T_IPV4_TCP 1
1164 #define RX_DESC3_L34T_IPV4_UDP 2
1165 #define RX_DESC3_L34T_IPV4_ICMP 3
1166 #define RX_DESC3_L34T_IPV6_TCP 9
1167 #define RX_DESC3_L34T_IPV6_UDP 10
1168 #define RX_DESC3_L34T_IPV6_ICMP 11
1170 #define RX_CONTEXT_DESC3_TSA_INDEX 4
1171 #define RX_CONTEXT_DESC3_TSA_WIDTH 1
1172 #define RX_CONTEXT_DESC3_TSD_INDEX 6
1173 #define RX_CONTEXT_DESC3_TSD_WIDTH 1
1175 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
1176 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1
1177 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1
1178 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1
1179 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2
1180 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1181 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3
1182 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1
1184 #define TX_CONTEXT_DESC2_MSS_INDEX 0
1185 #define TX_CONTEXT_DESC2_MSS_WIDTH 15
1186 #define TX_CONTEXT_DESC3_CTXT_INDEX 30
1187 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1
1188 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26
1189 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1
1190 #define TX_CONTEXT_DESC3_VLTV_INDEX 16
1191 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1
1192 #define TX_CONTEXT_DESC3_VT_INDEX 0
1193 #define TX_CONTEXT_DESC3_VT_WIDTH 16
1195 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0
1196 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14
1197 #define TX_NORMAL_DESC2_IC_INDEX 31
1198 #define TX_NORMAL_DESC2_IC_WIDTH 1
1199 #define TX_NORMAL_DESC2_TTSE_INDEX 30
1200 #define TX_NORMAL_DESC2_TTSE_WIDTH 1
1201 #define TX_NORMAL_DESC2_VTIR_INDEX 14
1202 #define TX_NORMAL_DESC2_VTIR_WIDTH 2
1203 #define TX_NORMAL_DESC3_CIC_INDEX 16
1204 #define TX_NORMAL_DESC3_CIC_WIDTH 2
1205 #define TX_NORMAL_DESC3_CPC_INDEX 26
1206 #define TX_NORMAL_DESC3_CPC_WIDTH 2
1207 #define TX_NORMAL_DESC3_CTXT_INDEX 30
1208 #define TX_NORMAL_DESC3_CTXT_WIDTH 1
1209 #define TX_NORMAL_DESC3_FD_INDEX 29
1210 #define TX_NORMAL_DESC3_FD_WIDTH 1
1211 #define TX_NORMAL_DESC3_FL_INDEX 0
1212 #define TX_NORMAL_DESC3_FL_WIDTH 15
1213 #define TX_NORMAL_DESC3_LD_INDEX 28
1214 #define TX_NORMAL_DESC3_LD_WIDTH 1
1215 #define TX_NORMAL_DESC3_OWN_INDEX 31
1216 #define TX_NORMAL_DESC3_OWN_WIDTH 1
1217 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19
1218 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4
1219 #define TX_NORMAL_DESC3_TCPPL_INDEX 0
1220 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18
1221 #define TX_NORMAL_DESC3_TSE_INDEX 18
1222 #define TX_NORMAL_DESC3_TSE_WIDTH 1
1224 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2
1226 /* MDIO undefined or vendor specific registers */
1227 #ifndef MDIO_PMA_10GBR_PMD_CTRL
1228 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
1231 #ifndef MDIO_PMA_10GBR_FECCTRL
1232 #define MDIO_PMA_10GBR_FECCTRL 0x00ab
1235 #ifndef MDIO_PCS_DIG_CTRL
1236 #define MDIO_PCS_DIG_CTRL 0x8000
1240 #define MDIO_AN_XNP 0x0016
1244 #define MDIO_AN_LPX 0x0019
1247 #ifndef MDIO_AN_COMP_STAT
1248 #define MDIO_AN_COMP_STAT 0x0030
1251 #ifndef MDIO_AN_INTMASK
1252 #define MDIO_AN_INTMASK 0x8001
1256 #define MDIO_AN_INT 0x8002
1259 #ifndef MDIO_VEND2_AN_ADVERTISE
1260 #define MDIO_VEND2_AN_ADVERTISE 0x0004
1263 #ifndef MDIO_VEND2_AN_LP_ABILITY
1264 #define MDIO_VEND2_AN_LP_ABILITY 0x0005
1267 #ifndef MDIO_VEND2_AN_CTRL
1268 #define MDIO_VEND2_AN_CTRL 0x8001
1271 #ifndef MDIO_VEND2_AN_STAT
1272 #define MDIO_VEND2_AN_STAT 0x8002
1275 #ifndef MDIO_VEND2_PMA_CDR_CONTROL
1276 #define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
1279 #ifndef MDIO_CTRL1_SPEED1G
1280 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
1283 #ifndef MDIO_VEND2_CTRL1_AN_ENABLE
1284 #define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12)
1287 #ifndef MDIO_VEND2_CTRL1_AN_RESTART
1288 #define MDIO_VEND2_CTRL1_AN_RESTART BIT(9)
1291 #ifndef MDIO_VEND2_CTRL1_SS6
1292 #define MDIO_VEND2_CTRL1_SS6 BIT(6)
1295 #ifndef MDIO_VEND2_CTRL1_SS13
1296 #define MDIO_VEND2_CTRL1_SS13 BIT(13)
1299 /* MDIO mask values */
1300 #define AXGBE_AN_CL73_INT_CMPLT BIT(0)
1301 #define AXGBE_AN_CL73_INC_LINK BIT(1)
1302 #define AXGBE_AN_CL73_PG_RCV BIT(2)
1303 #define AXGBE_AN_CL73_INT_MASK 0x07
1305 #define AXGBE_XNP_MCF_NULL_MESSAGE 0x001
1306 #define AXGBE_XNP_ACK_PROCESSED BIT(12)
1307 #define AXGBE_XNP_MP_FORMATTED BIT(13)
1308 #define AXGBE_XNP_NP_EXCHANGE BIT(15)
1310 #define AXGBE_KR_TRAINING_START BIT(0)
1311 #define AXGBE_KR_TRAINING_ENABLE BIT(1)
1313 #define AXGBE_PCS_CL37_BP BIT(12)
1315 #define AXGBE_AN_CL37_INT_CMPLT BIT(0)
1316 #define AXGBE_AN_CL37_INT_MASK 0x01
1318 #define AXGBE_AN_CL37_HD_MASK 0x40
1319 #define AXGBE_AN_CL37_FD_MASK 0x20
1321 #define AXGBE_AN_CL37_PCS_MODE_MASK 0x06
1322 #define AXGBE_AN_CL37_PCS_MODE_BASEX 0x00
1323 #define AXGBE_AN_CL37_PCS_MODE_SGMII 0x04
1324 #define AXGBE_AN_CL37_TX_CONFIG_MASK 0x08
1325 #define AXGBE_AN_CL37_MII_CTRL_8BIT 0x0100
1327 #define AXGBE_PMA_CDR_TRACK_EN_MASK 0x01
1328 #define AXGBE_PMA_CDR_TRACK_EN_OFF 0x00
1329 #define AXGBE_PMA_CDR_TRACK_EN_ON 0x01
1334 #define rmb() rte_rmb() /* dpdk rte provided rmb */
1335 #define wmb() rte_wmb() /* dpdk rte provided wmb */
1341 typedef unsigned char u8;
1342 typedef unsigned short u16;
1343 typedef unsigned int u32;
1344 typedef unsigned long long u64;
1345 typedef unsigned long long dma_addr_t;
1347 static inline uint32_t low32_value(uint64_t addr)
1349 return (addr) & 0x0ffffffff;
1352 static inline uint32_t high32_value(uint64_t addr)
1354 return (addr >> 32) & 0x0ffffffff;
1359 /* Bit setting and getting macros
1360 * The get macro will extract the current bit field value from within
1363 * The set macro will clear the current bit field value within the
1364 * variable and then set the bit field of the variable to the
1367 #define GET_BITS(_var, _index, _width) \
1368 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1370 #define SET_BITS(_var, _index, _width, _val) \
1372 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1373 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1376 #define GET_BITS_LE(_var, _index, _width) \
1377 ((rte_le_to_cpu_32((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1379 #define SET_BITS_LE(_var, _index, _width, _val) \
1381 (_var) &= rte_cpu_to_le_32(~(((0x1U << (_width)) - 1) << (_index)));\
1382 (_var) |= rte_cpu_to_le_32((((_val) & \
1383 ((0x1U << (_width)) - 1)) << (_index))); \
1386 /* Bit setting and getting macros based on register fields
1387 * The get macro uses the bit field definitions formed using the input
1388 * names to extract the current bit field value from within the
1391 * The set macro uses the bit field definitions formed using the input
1392 * names to set the bit field of the variable to the specified value
1394 #define AXGMAC_GET_BITS(_var, _prefix, _field) \
1396 _prefix##_##_field##_INDEX, \
1397 _prefix##_##_field##_WIDTH)
1399 #define AXGMAC_SET_BITS(_var, _prefix, _field, _val) \
1401 _prefix##_##_field##_INDEX, \
1402 _prefix##_##_field##_WIDTH, (_val))
1404 #define AXGMAC_GET_BITS_LE(_var, _prefix, _field) \
1405 GET_BITS_LE((_var), \
1406 _prefix##_##_field##_INDEX, \
1407 _prefix##_##_field##_WIDTH)
1409 #define AXGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \
1410 SET_BITS_LE((_var), \
1411 _prefix##_##_field##_INDEX, \
1412 _prefix##_##_field##_WIDTH, (_val))
1414 /* Macros for reading or writing registers
1415 * The ioread macros will get bit fields or full values using the
1416 * register definitions formed using the input names
1418 * The iowrite macros will set bit fields or full values using the
1419 * register definitions formed using the input names
1421 #define AXGMAC_IOREAD(_pdata, _reg) \
1422 rte_read32((uint8_t *)((_pdata)->xgmac_regs) + (_reg))
1424 #define AXGMAC_IOREAD_BITS(_pdata, _reg, _field) \
1425 GET_BITS(AXGMAC_IOREAD((_pdata), _reg), \
1426 _reg##_##_field##_INDEX, \
1427 _reg##_##_field##_WIDTH)
1429 #define AXGMAC_IOWRITE(_pdata, _reg, _val) \
1430 rte_write32((_val), \
1431 (uint8_t *)((_pdata)->xgmac_regs) + (_reg))
1433 #define AXGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1435 u32 reg_val = AXGMAC_IOREAD((_pdata), _reg); \
1437 _reg##_##_field##_INDEX, \
1438 _reg##_##_field##_WIDTH, (_val)); \
1439 AXGMAC_IOWRITE((_pdata), _reg, reg_val); \
1442 /* Macros for reading or writing MTL queue or traffic class registers
1443 * Similar to the standard read and write macros except that the
1444 * base register value is calculated by the queue or traffic class number
1446 #define AXGMAC_MTL_IOREAD(_pdata, _n, _reg) \
1447 rte_read32((uint8_t *)((_pdata)->xgmac_regs) + \
1448 MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))
1450 #define AXGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
1451 GET_BITS(AXGMAC_MTL_IOREAD((_pdata), (_n), (_reg)), \
1452 _reg##_##_field##_INDEX, \
1453 _reg##_##_field##_WIDTH)
1455 #define AXGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
1456 rte_write32((_val), (uint8_t *)((_pdata)->xgmac_regs) +\
1457 MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))
1459 #define AXGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
1461 u32 reg_val = AXGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
1463 _reg##_##_field##_INDEX, \
1464 _reg##_##_field##_WIDTH, (_val)); \
1465 AXGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
1468 /* Macros for reading or writing DMA channel registers
1469 * Similar to the standard read and write macros except that the
1470 * base register value is obtained from the ring
1472 #define AXGMAC_DMA_IOREAD(_channel, _reg) \
1473 rte_read32((uint8_t *)((_channel)->dma_regs) + (_reg))
1475 #define AXGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
1476 GET_BITS(AXGMAC_DMA_IOREAD((_channel), _reg), \
1477 _reg##_##_field##_INDEX, \
1478 _reg##_##_field##_WIDTH)
1480 #define AXGMAC_DMA_IOWRITE(_channel, _reg, _val) \
1481 rte_write32((_val), \
1482 (uint8_t *)((_channel)->dma_regs) + (_reg))
1484 #define AXGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
1486 u32 reg_val = AXGMAC_DMA_IOREAD((_channel), _reg); \
1488 _reg##_##_field##_INDEX, \
1489 _reg##_##_field##_WIDTH, (_val)); \
1490 AXGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
1493 /* Macros for building, reading or writing register values or bits
1494 * within the register values of XPCS registers.
1496 #define XPCS_GET_BITS(_var, _prefix, _field) \
1498 _prefix##_##_field##_INDEX, \
1499 _prefix##_##_field##_WIDTH)
1501 #define XPCS_SET_BITS(_var, _prefix, _field, _val) \
1503 _prefix##_##_field##_INDEX, \
1504 _prefix##_##_field##_WIDTH, (_val))
1506 #define XPCS32_IOWRITE(_pdata, _off, _val) \
1508 (uint8_t *)((_pdata)->xpcs_regs) + (_off))
1510 #define XPCS32_IOREAD(_pdata, _off) \
1511 rte_read32((uint8_t *)((_pdata)->xpcs_regs) + (_off))
1513 #define XPCS16_IOWRITE(_pdata, _off, _val) \
1515 (uint8_t *)((_pdata)->xpcs_regs) + (_off))
1517 #define XPCS16_IOREAD(_pdata, _off) \
1518 rte_read16((uint8_t *)((_pdata)->xpcs_regs) + (_off))
1520 /* Macros for building, reading or writing register values or bits
1521 * within the register values of SerDes integration registers.
1523 #define XSIR_GET_BITS(_var, _prefix, _field) \
1525 _prefix##_##_field##_INDEX, \
1526 _prefix##_##_field##_WIDTH)
1528 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \
1530 _prefix##_##_field##_INDEX, \
1531 _prefix##_##_field##_WIDTH, (_val))
1533 #define XSIR0_IOREAD(_pdata, _reg) \
1534 rte_read16((uint8_t *)((_pdata)->sir0_regs) + (_reg))
1536 #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \
1537 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \
1538 _reg##_##_field##_INDEX, \
1539 _reg##_##_field##_WIDTH)
1541 #define XSIR0_IOWRITE(_pdata, _reg, _val) \
1542 rte_write16((_val), \
1543 (uint8_t *)((_pdata)->sir0_regs) + (_reg))
1545 #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1547 u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \
1549 _reg##_##_field##_INDEX, \
1550 _reg##_##_field##_WIDTH, (_val)); \
1551 XSIR0_IOWRITE((_pdata), _reg, reg_val); \
1554 #define XSIR1_IOREAD(_pdata, _reg) \
1555 rte_read16((uint8_t *)((_pdata)->sir1_regs) + _reg)
1557 #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \
1558 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \
1559 _reg##_##_field##_INDEX, \
1560 _reg##_##_field##_WIDTH)
1562 #define XSIR1_IOWRITE(_pdata, _reg, _val) \
1563 rte_write16((_val), \
1564 (uint8_t *)((_pdata)->sir1_regs) + (_reg))
1566 #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1568 u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \
1570 _reg##_##_field##_INDEX, \
1571 _reg##_##_field##_WIDTH, (_val)); \
1572 XSIR1_IOWRITE((_pdata), _reg, reg_val); \
1575 /* Macros for building, reading or writing register values or bits
1576 * within the register values of SerDes RxTx registers.
1578 #define XRXTX_IOREAD(_pdata, _reg) \
1579 rte_read16((uint8_t *)((_pdata)->rxtx_regs) + (_reg))
1581 #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \
1582 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \
1583 _reg##_##_field##_INDEX, \
1584 _reg##_##_field##_WIDTH)
1586 #define XRXTX_IOWRITE(_pdata, _reg, _val) \
1587 rte_write16((_val), \
1588 (uint8_t *)((_pdata)->rxtx_regs) + (_reg))
1590 #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1592 u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \
1594 _reg##_##_field##_INDEX, \
1595 _reg##_##_field##_WIDTH, (_val)); \
1596 XRXTX_IOWRITE((_pdata), _reg, reg_val); \
1599 /* Macros for building, reading or writing register values or bits
1600 * within the register values of MAC Control registers.
1602 #define XP_GET_BITS(_var, _prefix, _field) \
1604 _prefix##_##_field##_INDEX, \
1605 _prefix##_##_field##_WIDTH)
1607 #define XP_SET_BITS(_var, _prefix, _field, _val) \
1609 _prefix##_##_field##_INDEX, \
1610 _prefix##_##_field##_WIDTH, (_val))
1612 #define XP_IOREAD(_pdata, _reg) \
1613 rte_read32((uint8_t *)((_pdata)->xprop_regs) + (_reg))
1615 #define XP_IOREAD_BITS(_pdata, _reg, _field) \
1616 GET_BITS(XP_IOREAD((_pdata), (_reg)), \
1617 _reg##_##_field##_INDEX, \
1618 _reg##_##_field##_WIDTH)
1620 #define XP_IOWRITE(_pdata, _reg, _val) \
1621 rte_write32((_val), \
1622 (uint8_t *)((_pdata)->xprop_regs) + (_reg))
1624 #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1626 u32 reg_val = XP_IOREAD((_pdata), (_reg)); \
1628 _reg##_##_field##_INDEX, \
1629 _reg##_##_field##_WIDTH, (_val)); \
1630 XP_IOWRITE((_pdata), (_reg), reg_val); \
1633 /* Macros for building, reading or writing register values or bits
1634 * within the register values of I2C Control registers.
1636 #define XI2C_GET_BITS(_var, _prefix, _field) \
1638 _prefix##_##_field##_INDEX, \
1639 _prefix##_##_field##_WIDTH)
1641 #define XI2C_SET_BITS(_var, _prefix, _field, _val) \
1643 _prefix##_##_field##_INDEX, \
1644 _prefix##_##_field##_WIDTH, (_val))
1646 #define XI2C_IOREAD(_pdata, _reg) \
1647 rte_read32((uint8_t *)((_pdata)->xi2c_regs) + (_reg))
1649 #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \
1650 GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \
1651 _reg##_##_field##_INDEX, \
1652 _reg##_##_field##_WIDTH)
1654 #define XI2C_IOWRITE(_pdata, _reg, _val) \
1655 rte_write32((_val), \
1656 (uint8_t *)((_pdata)->xi2c_regs) + (_reg))
1658 #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1660 u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \
1662 _reg##_##_field##_INDEX, \
1663 _reg##_##_field##_WIDTH, (_val)); \
1664 XI2C_IOWRITE((_pdata), (_reg), reg_val); \
1667 /* Macros for building, reading or writing register values or bits
1668 * using MDIO. Different from above because of the use of standardized
1669 * Linux include values. No shifting is performed with the bit
1670 * operations, everything works on mask values.
1672 #define XMDIO_READ(_pdata, _mmd, _reg) \
1673 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
1674 MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))
1676 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \
1677 (XMDIO_READ((_pdata), _mmd, _reg) & _mask)
1679 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \
1680 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \
1681 MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))
1683 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \
1685 u32 mmd_val = XMDIO_READ((_pdata), (_mmd), (_reg)); \
1686 mmd_val &= ~(_mask); \
1687 mmd_val |= (_val); \
1688 XMDIO_WRITE((_pdata), (_mmd), (_reg), (mmd_val)); \
1692 * time_after(a,b) returns true if the time a is after time b.
1694 * Do this with "<0" and ">=0" to only test the sign of the result. A
1695 * good compiler would generate better code (and a really good compiler
1696 * wouldn't care). Gcc is currently neither.
1698 #define time_after(a, b) ((long)((b) - (a)) < 0)
1699 #define time_before(a, b) time_after(b, a)
1701 #define time_after_eq(a, b) ((long)((a) - (b)) >= 0)
1702 #define time_before_eq(a, b) time_after_eq(b, a)
1704 static inline unsigned long msecs_to_timer_cycles(unsigned int m)
1706 return rte_get_timer_hz() * (m / 1000);
1709 #endif /* __AXGBE_COMMON_H__ */